JPH06259968A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] For example, regarding SRAM, bit line load circuit,
Transistors forming the bit line equalize circuit and the word line driver are efficiently arranged, and the wiring for contacts necessary for forming the bit line load circuit, the bit line equalize circuit and the word line driver is reduced. [Structure] The same number of memory cells 16 are arranged at the same array pitch,
Memory cell columns 125 ₁ , 125 _2, ... 12 in which memory cell sub-columns 126, 127 having different array phases and arranged in the row direction and having common word lines are arranged in the column direction.
5 _n are arranged in the column direction, the data input / output terminals 17 and 18 of the memory cells 16 of the memory cell sub-column 126 are connected to the column selection circuit 9, and the data input / output terminals 17 of the memory cells 16 of the memory cell sub-column 127 are connected. , 18 are connected to the column selection circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an SRAM (static ran).
dom access memory) and the like, and relates to a semiconductor memory device provided with memory cells configured to read stored data using a pair of bit lines.

[0002]

2. Description of the Related Art Conventionally, as an SRAM, one whose main part is shown in FIG. 13 is known. In the figure, 1 is SRA
An M body 2 is a memory cell array portion in which memory cells are arranged.

Reference numeral 3 denotes an internal structure in which row address signals A _X1 , A _X2 ... A _Xn supplied from the outside are input and these row address signals A _X1 , A _X2 ... A _Xn are converted into complementary signals. A row address buffer that outputs a row address signal.

Reference numeral 4 is a row decoder for decoding the internal row address signal output from the row address buffer 3, and reference numeral 5 is a word line driver for driving the word line selected by the row decoder 4.

Reference numeral 6 denotes an internal structure in which column address signals A _Y1 , A _Y2 ... A _Yn supplied from the outside are input and these column address signals A _Y1 , A _Y2 ... A _Yn are converted into complementary signals. The column address buffer outputs a column address signal.

Column address buffers 6 and 7 are also provided.
Column decoders for decoding the internal column address output from the column decoder and outputting a column selection signal, and 9 and 10 are column selection circuits for selecting columns.

Further, D ₁ , D ₂ ... D _2n are input / output data, 11 is a data input / output buffer for input / output data D ₂ , D ₄ ... D _2n , 12 is input / output data D ₁ , D ₃ ... D
_This is a data input / output buffer for _2n-1 .

Further, 13 is a chip select signal / CS buffer (CS buffer), and 14 and 15 are write enable signal / WE and output enable signal / O.
It is a buffer for E (WE / OE buffer).

FIG. 14 is a plan view schematically showing an arrangement mode of memory cells in the memory cell array section 2. In the figure, 16 is a memory cell, 17 and 18 are data input / output terminals of the memory cell 16, BL _i , / BL _i ... / BL
_{i + 3} is a bit line, WL ₁ , WL ₂ ... WL _n are word lines, and the memory cell 16 is configured as shown in FIG.

In the figure, 19 is a high resistance load type flip-flop, 20 and 21 are nMOS transistors which are driving transistors, 22 and 23 are high resistances which load the nMOS transistors 20 and 21, and 24 is a power supply. Voltage V
It is a VCC power supply line for supplying CC.

Reference numerals 25 and 26 are nMOS transistors which are transistors for selecting memory cells.

In this example, the memory cells 16 are arranged in the row direction, and one word data is stored in each of the memory cell columns 27 ₁ , 27 ₂ ... 27 _n having a common word line. Has been

Further, FIG. 16 shows bit lines BL _i and / BL _i.
... / BL _{i + 3} peripheral circuits, 28 ₀ to 2
8 _3, 29 _{0-29 3} 30 ₀ - 30 _3, 31 _{0-31 3} is a pMOS transistor constituting the bit line load circuit.

[0014] 32 _{0-32 3} 33 _{0-33 3} pMOS transistors forming the bit line equalize circuit,
SE is pMOS transistors 32 _{0 to} 32 ₃ and 33 _{0 to} 3
This is a signal for controlling ON / OFF of 3 ₃ .

[0015] 34 _{0-34 3} 35 _{0-35 3} are analog switches constituting the column selection circuits 9 and 10, 36 _{0-36 3} 37 _{0-37 3} nMOS transistors, 38 ₀ ~ 38 _3, 39 _{0-39 3} is a pMOS transistor.

FIG. 17 shows the bit line B shown in FIG.
FIG. 18 is a layout diagram of transistors corresponding to FIG. 16 and FIG. 18 is a plan view showing a wiring layout of a part of a peripheral circuit of L _i , / BL _i ... / BL _{i + 3} .

In FIG. 17, 40 to 61 are P type diffusion layers, 62 to 69 are N type diffusion layers, 70 to 73 are gate layers,
Reference numerals 74 and 75 are contact wirings, 76 is a VCC power supply line, 77 to 116 are contact portions between the diffusion layer and the first layer metal wiring, and 117 to 124 are contacts between the first layer metal wiring and the second layer metal wiring. It is a department.

The bit lines BL _i , / BL _i ... / B
L _{i + 3} , the contact wirings 74 and 75, etc. are the first layer metal wirings, and the VCC power supply line 76, the data buses DB ₁ , / DB ₁ etc. are the second layer metal wirings.

[0019]

Such a conventional SRAM
In FIG. 14, the memory cell 16 is
They were arranged in a matrix. As a result, the distance between the two bit lines forming the bit line pair and the distance between the word lines have to be narrowed.

Therefore, if the integration is continued as it is, it should be formed adjacent to the bit line load circuit and the bit line equalize circuit to be formed between the two bit lines forming the bit line pair, and the memory cell array section 2. It is impossible to efficiently arrange the transistors forming the word line driver 5, and it is necessary to increase the number of contact wirings in order to form the bit line load circuit, the bit line equalize circuit and the word line driver 5. There was a problem.

In view of the above point, the present invention arranges the first column selection circuit, the memory cell array portion, and the second column selection circuit in the column direction in order, and uses a pair of bit lines in the memory cell array portion. And a bit line equalizing circuit and a bit line load circuit to be formed between two bit lines forming a bit line pair. Wiring for contacts necessary for efficiently disposing transistors forming a word line driver to be formed adjacent to the memory cell array portion and forming the bit line load circuit, the bit line equalize circuit and the word line driver It is an object of the present invention to provide a semiconductor memory device capable of reducing the number of charges.

[0022]

In a semiconductor memory device according to the present invention, a first column selection circuit, a memory cell array portion, and a second column selection circuit are sequentially arranged in a column direction, and the memory cell array portion includes: An equal number of memory cells configured to read stored data using two bit lines,
A plurality of memory cells arranged in the row direction with the same arrangement pitch and different arrangement phases, and the first and second memory cell sub-columns having a common word line are arranged in the column direction in an arbitrary order. The columns are arranged in the column direction, the memory cells of the first sub-column of memory cells are connected to the first column selection circuit via the bit line, and the memory cells of the second sub-column of memory cell are connected to the bit line. It is configured to include a portion connected to the second column selection circuit via the above.

[0023]

According to the present invention, the first and second memory cell sub-columns in which the same number of memory cells are arranged in the row direction with the same arrangement pitch and different arrangement phases are arranged in the column direction in any order. To form a memory cell column.

Further, the memory cells of the first memory cell sub-column are connected to the first column selection circuit via a bit line,
The memory cells in the second memory cell sub-column are connected to the second column selection circuit via the bit line.

As a result, the memory cell can be formed in a large size in the row direction and a small size in the column direction, and the distance between two bit lines forming a bit line pair can be reduced without reducing the degree of integration. Can be increased.

Therefore, the transistors forming the bit line load circuit and the bit line equalize circuit to be formed between the two bit lines forming the bit line pair can be efficiently arranged, and the bit line load circuit and the bit lines can be efficiently arranged. It is possible to reduce the number of contact wirings required to form the line equalizing circuit.

Further, in the present invention, the pair of first and second memory cell sub-columns forming the memory cell column have common word lines. As a result, the distance between word lines can be increased.

Therefore, the transistors forming the word line driver to be formed adjacent to the memory cell array portion can be efficiently arranged, and the contact wiring required for forming the word line driver can be reduced. it can.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to third embodiments of the present invention will be described below with reference to FIGS. 1 to 12 as an example in which the present invention is applied to an SRAM. Note that FIG. 1, FIG. 5, and FIG.
In FIG. 14, parts corresponding to those in FIG.
The duplicate description will be omitted.

First Embodiment FIG. 1 to FIG. 4 FIG. 1 is a plan view schematically showing a main portion of a first embodiment of the present invention, in which a memory cell 16 in a memory cell array portion 2 is shown.
FIG.

In the figure, 125 ₁ , 125 _2, ... 125 _n are memory cell columns each storing one word of data, 126 and 127 are these memory cell columns 125 ₁ , 1
25 ₂ ... 125 _n is a memory cell sub-column.

Here, these memory cell sub-columns 126, 1
27 is the same number of memory cells 16 with the same arrangement pitch,
It is configured by arraying in the row direction with different array phases,
Memory cell sub-columns 126 forming the same memory cell column,
Reference numeral 127 is configured to have a common word line.

In this example, the memory cell sub-column 12 is
6, 127 are arranged alternately in the column direction. That is,
Memory cell sub-column 126, memory cell sub-column 127, memory cell sub-column 126, memory cell sub-column 127 ... Memory cell sub-column 126, memory cell sub-column 127 are arranged in this order from the column selection circuit 9 side in the column direction. ing.

FIG. 2 is a plan view showing a part of an example of the wiring layout of the memory cell array portion 2 in the first embodiment, FIG. 3 is a layout diagram of transistors corresponding to FIG. 2, and FIG. FIG. 3 is a sectional view taken along the line AA of FIG. 2.

In FIG. 2, 128 to 143 are N type diffusion layers, 144 to 151 are gate layers, 152 to 157 are contact portions between diffusion layers and bit lines, and 158 to 163 are contact portions between diffusion layers and gate layers. Reference numerals 164 to 167 are contact portions between the diffusion layer and the VSS power supply layer.

Further, in FIG. 4, the P-type silicon substrate 168, 169 is VSS power supply layer, 170 an element isolation layer formed of SiO _2, 171-173 is an interlayer insulating film made of SiO _2.

In the first embodiment, the same number of memory cells 1
6 are arranged in the row direction with the same arrangement pitch and different arrangement phase in the row direction, and the memory cell row 125 has a scale for storing 1-word data. ₁ , 125 _2, ... 125 _n are configured.

Further, the data input / output terminals 17 and 18 of the memory cells 16 of the memory cell sub-column 126 are connected to the column selection circuit 9 via the bit line, and the data input / output terminals of the memory cells 16 of the memory cell sub-column 127 are connected. The columns 17 and 18 are connected to the column selection circuit 10 via bit lines.

As a result, the memory cell 16 can be formed to have a large size in the row direction and a small size in the column direction, and the distance between two bit lines forming a bit line pair can be maintained without lowering the degree of integration. Can be increased.

Therefore, according to the first embodiment, the transistors forming the bit line load circuit and the bit line equalize circuit to be formed between the two bit lines forming the bit line pair can be efficiently arranged. Therefore, it is possible to reduce the number of contact wirings required to configure the bit line load circuit and the bit line equalize circuit.

Further, in the first embodiment, the pair of memory cell sub-columns 126, 127 forming the memory cell columns 125 ₁ , 125 _2, ... 125 _n have common word lines. . As a result, the distance between word lines can be increased.

Therefore, according to the first embodiment, the transistors forming the word line driver to be formed adjacent to the memory cell array portion 2 can be efficiently arranged, and the word line driver can be formed. The required wiring for contacts can be reduced.

Second Embodiment FIG. 5 to FIG. 8 FIG. 5 is a plan view schematically showing a main portion of a second embodiment of the present invention. As in FIG. 1, the memory cells in the memory cell array unit 2 are shown. 16 shows 16 arrangement modes.

In the second embodiment, the memory cell sub-column 12 is
Unlike the case of the first embodiment, the memory cells 6 and 127 are arranged not to alternate in the column direction but to be arranged so that two memory cell sub-rows having the same arrangement phase continue except for both ends.

That is, from the column selection circuit 9 side, the memory cell sub-column 126, the memory cell sub-column 127, the memory cell sub-column 1
27, memory cell sub-column 126, memory cell sub-column 126,
Memory cell sub-column 127 ... Memory cell sub-column 126 and memory cell sub-column 127 are arranged in this order in the column direction.

FIG. 6 is a plan view showing a part of an example of the wiring layout of the memory cell array portion 2 in the second embodiment, FIG. 7 is a layout view of transistors corresponding to FIG. 6, and FIG. It is sectional drawing which followed CC line of FIG.

In FIG. 6, 176 to 204 are N-type diffusion layers, 205 to 218 are gate layers, 219 to 226 are contact portions between diffusion layers and bit lines, and 227 to 238 are contact portions between diffusion layers and gate layers. 239 to 245 are contact portions between the diffusion layer and the VSS power supply layer.

In FIG. 8, 246 is a VSS power source layer, and 247 to 249 are interlayer insulating films made of SiO ₂ .

Also in the second embodiment, the same number of memory cells 16 are arranged with the same arrangement pitch and different arrangement phase.
The memory cell columns 125 ₁ , 125 _2, ... Having a scale for storing one word of data by arranging the memory cell sub-columns 126, 127 arranged in the row direction in the column direction, respectively.
・ 125 _n is configured.

Further, the data input / output terminals 17 and 18 of the memory cells 16 of the memory cell sub-column 126 are connected to the column selection circuit 9 via the bit line, and the data input / output terminals of the memory cells 16 of the memory cell sub-column 127 are connected. The columns 17 and 18 are also connected to the column selection circuit 10 via bit lines.

As a result, as in the case of the first embodiment, the memory cell 16 can be formed to have a large size in the row direction and a small size in the column direction, and the bit line can be formed without lowering the integration degree. The distance between two paired bit lines can be increased.

Therefore, according to this second embodiment as well,
As in the case of the first embodiment, the transistors forming the bit line load circuit and the bit line equalize circuit to be formed between the two bit lines forming the bit line pair can be efficiently arranged. It is possible to reduce the number of contact wirings required to form the line load circuit and the bit line equalize circuit.

Also in the second embodiment, as in the case of the first embodiment, the memory cell columns 125 ₁ , 125 ₂ ,.
.... A pair of memory cell sub-columns 126 forming 125 _n ,
The word lines 127 are commonly used. As a result, the distance between word lines can be increased.

Therefore, according to this second embodiment as well,
As in the case of the first embodiment, the transistors forming the word line driver to be formed adjacent to the memory cell array portion 2 can be efficiently arranged, and the contact wiring for forming the word line driver can be arranged. Can be reduced.

Third Embodiment ... FIG. 9 to FIG. 12 FIG. 9 is a plan view schematically showing a main portion of a third embodiment of the present invention. As in FIG. 1, memory cells in the memory cell array unit 2 are shown. 16 shows 16 arrangement modes.

In this third embodiment, the memory cell sub-column 12 is
6, 127 are arranged alternately in the column direction as in the case of the first embodiment. That is, the memory cell sub-column 126, the memory cell sub-column 127, the memory cell sub-column 126, the memory cell sub-column 127, ... It is arranged.

However, in this third embodiment, the word line is branched, the memory cell sub-column 126 makes one of the branched word lines common, and the memory cell sub-column 127 makes the other of the branched word lines common. Thus, the memory cell sub-columns 126 and 127 forming the same memory cell column are configured to share the word line.

Further, FIG. 10 is a plan view showing a part of an example of the wiring layout of the memory cell array portion 2 in the third embodiment, FIG. 11 is a layout view of transistors corresponding to FIG. 10, and FIG. FIG. 10 is a sectional view taken along line FF of FIG.

In FIG. 10, reference numerals 254 to 269 are N-type diffusion layers, 270 to 277 are gate layers, 278 to 283 are contact portions between diffusion layers and bit lines, and 284 to 289 are contact portions between diffusion layers and gate layers. , 290 to 293 are contact portions between the diffusion layer and the VSS power supply layer.

Further, in FIG. 12, 294 is a VSS power source layer, 295 is an element isolation layer made of SiO ₂ , and 296-2.
Reference numeral 98 is an interlayer insulating film made of SiO ₂ .

Also in this third embodiment, the same number of memory cells 16 are arranged with the same arrangement pitch and different arrangement phase.
The memory cell columns 125 ₁ , 125 _2, ... Having a scale for storing one word of data by arranging the memory cell sub-columns 126, 127 arranged in the row direction in the column direction, respectively.
・ 125 _n is configured.

Further, the data input / output terminals 17 and 18 of the memory cells 16 of the memory cell sub-column 126 are connected to the column selection circuit 9 through the bit lines, and the data input / output terminals of the memory cells 16 of the memory cell sub-column 127 are connected. The columns 17 and 18 are also connected to the column selection circuit 10 via bit lines.

As a result, as in the case of the first embodiment, the memory cell 16 can be formed to have a large size in the row direction and a small size in the column direction, and the bit line can be formed without lowering the integration degree. The distance between two paired bit lines can be increased.

Therefore, according to the third embodiment as well,
As in the case of the first embodiment, the transistors forming the bit line load circuit and the bit line equalize circuit to be formed between the two bit lines forming the bit line pair can be efficiently arranged. It is possible to reduce the number of contact wirings required to form the line load circuit and the bit line equalize circuit.

Also in the third embodiment, similarly to the case of the first embodiment, the memory cell columns 125 ₁ , 125 ₂ ,.
.... A pair of memory cell sub-columns 126 forming 125 _n ,
The word lines 127 are commonly used. As a result, the distance between word lines can be increased.

Therefore, according to the third embodiment as well,
As in the case of the first embodiment, the transistors forming the word line driver to be formed adjacent to the memory cell array portion 2 can be efficiently arranged, and the contact wiring for forming the word line driver can be arranged. The layers can be reduced.

[0067]

As described above, according to the present invention, the size of the memory cells in the row direction can be increased, the bit line interval can be increased, and the word line interval can be increased. , A transistor forming a bit line load circuit and a bit line equalizing circuit to be formed between two bit lines forming a bit line pair, and a transistor forming a word line driver to be formed adjacent to the memory cell array portion are efficiently used. It is possible to reduce the number of contact wirings required to form the bit line load circuit, the bit line equalize circuit and the word line driver.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a main part of a first embodiment of the present invention.

FIG. 2 is a plan view showing a part of an example of a wiring layout of a memory cell array portion in the first embodiment of the present invention.

FIG. 3 is a layout view of transistors corresponding to FIG.

FIG. 4 is a cross-sectional view taken along the line AA of FIG.

FIG. 5 is a plan view schematically showing a main part of a second embodiment of the present invention.

FIG. 6 is a plan view showing a part of an example of a wiring layout of a memory cell array portion in a second embodiment of the present invention.

FIG. 7 is a layout diagram of transistors corresponding to FIG. 6;

8 is a cross-sectional view taken along the line CC of FIG.

FIG. 9 is a plan view schematically showing a main part of a third embodiment of the present invention.

FIG. 10 is a plan view showing a part of an example of a wiring layout of a memory cell array section in a third embodiment of the present invention.

FIG. 11 is a layout view of transistors corresponding to FIG.

12 is a cross-sectional view taken along the line FF of FIG.

FIG. 13 is a block diagram showing a main part of an example of a conventional SRAM.

FIG. 14 is a diagram showing an arrangement mode of memory cells in a conventional SRAM.

FIG. 15 is a diagram showing a circuit configuration of a memory cell.

FIG. 16 is a diagram showing a peripheral circuit of a bit line.

17 is a plan view showing a wiring layout of a part of a peripheral circuit of the bit line shown in FIG.

FIG. 18 is a layout view of transistors corresponding to FIG. 16;

[Explanation of symbols]

2 memory cell array section 9, 10 column selection circuit 16 memory cell 17, 18 memory cell data input / output terminal 125 ₁ , 125 ₂ , 125 _n memory cell column 126, 127 memory cell small column

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 27/11 7514-4M H01L 21/88 Z 7210-4M 27/10 381

Claims (4)

[Claims] 1. A first column selection circuit, a memory cell array section, and a second column selection circuit are sequentially arranged in a column direction, and storage data is stored in the memory cell array section using a pair of bit lines. The same number of memory cells configured to be read are arranged in the row direction with the same arrangement pitch and different arrangement phase, and the first and second memory cell sub-columns having the common word line are arbitrarily arranged. A plurality of memory cell columns sequentially arranged in the column direction are arranged in the column direction, and the memory cells of the first memory cell sub-column are connected to the first column selection circuit via a bit line, 2. The semiconductor memory device according to claim 2, wherein the memory cells of the second memory cell sub-column include a portion connected to the second column selection circuit via a bit line. 2. The semiconductor memory according to claim 1, wherein the plurality of memory cell columns are formed by alternately arranging the first and second memory cell sub-columns in a column direction. apparatus. 3. The first and second memory cell sub-columns are arranged in the column direction so that the first and second memory cell sub-columns continue in two columns in the column direction except for both ends in the column direction. 2. The semiconductor memory device according to claim 1, wherein the plurality of memory cell columns are formed by arranging them. 4. The first and second memory cell sub-columns are arranged alternately in the column direction, and the word line of each row is branched into first and second word lines, and the first memory cell sub-column is divided. The columns are
The plurality of memory cell columns are configured by making the first word line common and making the second memory cell sub-column common to the second word line. The semiconductor memory device according to claim 1.