JPH06252286A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH06252286A JPH06252286A JP5031894A JP3189493A JPH06252286A JP H06252286 A JPH06252286 A JP H06252286A JP 5031894 A JP5031894 A JP 5031894A JP 3189493 A JP3189493 A JP 3189493A JP H06252286 A JPH06252286 A JP H06252286A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- chip carrier
- circuit
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 239000011347 resin Substances 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920001225 polyester resin Polymers 0.000 description 2
- 239000004645 polyester resin Substances 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電子機器、電気機器に利
用される半導体チップを搭載するプリント配線板の背面
に、外部入出力の端子であるバンプを形成したチップキ
ャリアに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier in which bumps, which are terminals for external input / output, are formed on the back surface of a printed wiring board on which semiconductor chips used in electronic equipment and electric equipment are mounted.
【０００２】[0002]
【従来の技術】従来のチップキャリアを用いた半導体装
置の一例を図２に基づいて説明する。導電回路（４）を
形成したプリント配線板（１）と、半導体チップ（３）
を搭載する上記プリント配線板（１）の背面に、半田バ
ンプ（２）を設けて入出力の端子が形成されたチップキ
ャリアが知られている。このチップキャリアは、上記導
電回路（４）と搭載した半導体チップ（３）をボンデイ
ングワイヤー（９）により接続し、その上に耐湿性を高
めるために封止剤（１０）により封止して半導体装置が
構成されている。2. Description of the Related Art An example of a conventional semiconductor device using a chip carrier will be described with reference to FIG. A printed wiring board (1) on which a conductive circuit (4) is formed, and a semiconductor chip (3)
There is known a chip carrier in which solder bumps (2) are provided on the back surface of the printed wiring board (1) on which the ICs are mounted to form input / output terminals. In this chip carrier, the conductive circuit (4) and the mounted semiconductor chip (3) are connected by a bonding wire (9), and a semiconductor (10) is sealed on the semiconductor chip to enhance moisture resistance. The device is configured.
【０００３】この半導体装置の半田バンプ（２）は、上
記プリント配線板（１）とマザーボードの導電回路間の
絶縁性の確保のために、マザーボードの間に間隔を設け
る働きをし、近年は端子ピンに替えて、上述の半田バン
プ（２）を用い、半導体装置とマザーボードに間隔を保
持する方法が多用されている。The solder bumps (2) of this semiconductor device function to provide a space between the printed wiring board (1) and the motherboard to secure insulation between the conductive circuits of the motherboard. A method of maintaining a gap between the semiconductor device and the motherboard by using the solder bumps (2) described above instead of the pins is widely used.
【０００４】上記半田バンプ（２）の形成法として、プ
リント配線板（１）の背面に形成された回路パッド
（５）に半田ボールを置き、リフロー機を通す方法や、
上記回路パッド（５）にループ状のボンデイングワイヤ
ーを設けた後に半田浸漬する方法がある。しかし、いず
れの場合も、マザーボードの回路との間隔が不十分で、
絶縁性が確保されずショートが発生する問題があり、さ
らには半田バンプ（２）の形状が不均一になったりする
と、仮にプリント配線板（１）の背面に導電回路（４）
が形成されている場合には、半田バンプ（２）が導電回
路（４）と短絡する恐れがある。As a method of forming the solder bumps (2), a solder ball is placed on a circuit pad (5) formed on the back surface of the printed wiring board (1) and passed through a reflow machine,
There is a method of immersing solder after providing a loop-shaped bonding wire on the circuit pad (5). However, in both cases, the distance from the motherboard circuit is insufficient,
If there is a problem that insulation is not ensured and a short circuit occurs, and if the solder bumps (2) have a non-uniform shape, the conductive circuit (4) is temporarily provided on the back surface of the printed wiring board (1).
, The solder bumps (2) may be short-circuited with the conductive circuit (4).
【０００５】[0005]
【発明が解決しようとする課題】本発明は上述の問題を
解消するためになされたもので、その目的とするところ
は、半導体チップを搭載するプリント配線板とマザーボ
ードの回路との間の絶縁性を確保したチップキャリアを
提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to provide an insulating property between a printed wiring board on which a semiconductor chip is mounted and a circuit of a mother board. It is to provide a chip carrier that secures.
【０００６】[0006]
【課題を解決するための手段】本発明に係るチップキャ
リアは、半導体チップ（３）を搭載するプリント配線板
（１）の背面に、外部入出力の端子であるバンプ（２）
を形成するチップキャリアにおいて、上記プリント配線
板（１）の背面に、回路パッド（５）の位置にスルホー
ル（８）を備えた絶縁層（６）が形成され、且つこのス
ルホール（８）を貫通する上記バンプ（２）が形成され
ていることを特徴とする。A chip carrier according to the present invention comprises a bump (2), which is a terminal for external input / output, on the back surface of a printed wiring board (1) on which a semiconductor chip (3) is mounted.
In a chip carrier for forming a substrate, an insulating layer (6) having a through hole (8) at a position of a circuit pad (5) is formed on the back surface of the printed wiring board (1) and penetrates the through hole (8). The above-mentioned bump (2) is formed.
【０００７】[0007]
【作用】本発明は、チップキャリアを構成するプリント
配線板（１）の背面に絶縁層（６）を形成し、この絶縁
層（６）でプリント配線板とマザーボードの回路との絶
縁性を確保することができる。According to the present invention, the insulating layer (6) is formed on the back surface of the printed wiring board (1) constituting the chip carrier, and the insulating layer (6) ensures insulation between the printed wiring board and the circuit of the motherboard. can do.
【０００８】[0008]
【実施例】以下本発明を実施例に係る図面に基づいて説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings related to the embodiments.
【０００９】図１は本発明の一実施例に係るチップキャ
リアを用いた半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device using a chip carrier according to an embodiment of the present invention.
【００１０】本発明のチップキャリアは、プリント配線
板（１）と、このプリント配線板（１）の背面に形成さ
れた回路パッド（５）の位置にスルホール（８）を備え
た絶縁層（６）、及び、このスルホール（８）を貫通す
るバンプ（２）から構成されている。The chip carrier of the present invention comprises a printed wiring board (1) and an insulating layer (6) having through holes (8) at the positions of the circuit pads (5) formed on the back surface of the printed wiring board (1). ) And a bump (2) penetrating the through hole (8).
【００１１】本発明のチップキャリアを構成する上記プ
リント配線板（１）としては、基材に樹脂を含浸乾燥し
て得られるプリプレグの樹脂を硬化させた有機系の絶縁
板、又はアルミナ等のセラミック系の絶縁板が用いられ
る。この有機系の絶縁板の樹脂としてはエポキシ樹脂、
ポリイミド樹脂、フッ素樹脂、フェノール樹脂、付飽和
ポリエステル樹脂、ＰＰＯ樹脂等の単独、変成物、混合
物等が用いられる。有機系の絶縁板の基材としては、特
に限定するものではないが、ガラス繊維などの無機材料
の方が耐熱性、耐湿性などに優れて好ましい。また、耐
熱性に優れる有機繊維布基材及びこれらの混合物を用い
ることもできる。上記プリント配線板（１）の表面及び
背面には、導電回路（４）を備えている。この導電回路
（４）はプリント配線板（１）の表面に配設された金属
箔をエッチングして形成された回路、その他メッキで形
成した回路など制限がない。As the printed wiring board (1) constituting the chip carrier of the present invention, an organic insulating plate obtained by curing a resin of a prepreg obtained by impregnating a base material with a resin and drying, or a ceramic such as alumina. A system insulation plate is used. Epoxy resin as the resin of this organic insulating plate,
A polyimide resin, a fluororesin, a phenol resin, a saturated polyester resin, a PPO resin, etc. may be used alone, or as a modified product or mixture thereof. The base material of the organic insulating plate is not particularly limited, but an inorganic material such as glass fiber is preferable because it is excellent in heat resistance and moisture resistance. Further, an organic fiber cloth base material having excellent heat resistance and a mixture thereof can also be used. Conductive circuits (4) are provided on the front and back surfaces of the printed wiring board (1). The conductive circuit (4) is not limited to a circuit formed by etching a metal foil provided on the surface of the printed wiring board (1) or a circuit formed by plating.
【００１２】このプリント配線板（１）の導電回路
（４）にボンデイングワイヤー（９）で接続される半導
体チップ（３）が搭載される。この半導体チップ（３）
が搭載される面は図１に示された如く平面でもよいし、
プリント配線板（１）の表面を座ぐった凹部面（図示せ
ず）でもよい。さらに、上記半導体チップ（３）を搭載
するプリント配線板（１）の背面に、回路パッド（５）
が設けらている。この回路パッド（５）の位置にスルホ
ール（８）を有する絶縁層（６）がプリント配線板
（１）の背面に形成されている。A semiconductor chip (3) connected to a conductive circuit (4) of the printed wiring board (1) by a bonding wire (9) is mounted. This semiconductor chip (3)
The surface on which is mounted may be a flat surface as shown in FIG.
It may be a recessed surface (not shown) which is formed by boring the surface of the printed wiring board (1). Further, a circuit pad (5) is provided on the back surface of the printed wiring board (1) on which the semiconductor chip (3) is mounted.
Is provided. An insulating layer (6) having a through hole (8) at the position of the circuit pad (5) is formed on the back surface of the printed wiring board (1).
【００１３】上記絶縁層（６）としては、例えば絶縁樹
脂基板、絶縁樹脂層、及びこれらの組合せ等が挙げられ
る。さらに上記絶縁樹脂基板を具体的に示せば、基材に
樹脂を含浸乾燥して得られるプリプレグの樹脂を硬化さ
せた有機系の絶縁板が挙げられる。又、この絶縁樹脂基
板とプリント配線板（１）を構成する絶縁板の材種の同
一性は問わない。すなわち、絶縁樹脂基板はプリント配
線板（１）を構成する絶縁板でもよいし、絶縁樹脂基板
はガエス不織布付飽和ポリエステル樹脂基板で上記プリ
ント配線板（１）はガラス布エポキシ樹脂基板等、異な
った材料でもよい。上記絶縁樹脂層としては、液状エポ
キシ樹脂、エポキシ樹脂を含有したソルダーレジストが
挙げられる。さらに、上記絶縁樹脂を硬化した樹脂層を
接着層（７）として上記絶縁樹脂基板と組合せてもよ
い。この絶縁層（６）は、実装後にプリント配線板
（１）とマザーボードの回路との間隔を確保し、最小限
絶縁層（６）の層厚分の絶縁性を保持する。Examples of the insulating layer (6) include an insulating resin substrate, an insulating resin layer, and combinations thereof. More specifically, the insulating resin substrate may be, for example, an organic insulating plate obtained by curing a resin of a prepreg obtained by impregnating and drying a base material with a resin. Further, the same kind of material may be used for the insulating resin substrate and the insulating plate constituting the printed wiring board (1). That is, the insulating resin substrate may be an insulating plate constituting the printed wiring board (1), or the insulating resin substrate may be a saturated polyester resin substrate with a GAES nonwoven fabric, and the printed wiring board (1) may be a glass cloth epoxy resin substrate or the like. Material may be used. Examples of the insulating resin layer include a liquid epoxy resin and a solder resist containing an epoxy resin. Further, a resin layer obtained by curing the insulating resin may be combined with the insulating resin substrate as an adhesive layer (7). The insulating layer (6) secures a distance between the printed wiring board (1) and the circuit of the mother board after mounting, and maintains the insulating property of the minimum thickness of the insulating layer (6).
【００１４】回路パッド（５）に位置する絶縁層（６）
のスルホール（８）を貫通するバンプ（２）の形成は、
例えば、予め上記回路パッド（５）に位置するスルホー
ル（８）に半田ボールを仮置きし、リフロー機を通す方
法、スルホール（８）を貫通するループ状のボンデイン
グワイヤーを設け、半田浸漬する方法等が挙げられる。Insulating layer (6) located on the circuit pad (5)
The formation of the bump (2) that penetrates the through hole (8) of
For example, a method of temporarily placing a solder ball in the through hole (8) located on the circuit pad (5) in advance and passing it through a reflow machine, a method of providing a loop-shaped bonding wire passing through the through hole (8), and immersing the solder in it, etc. Is mentioned.
【００１５】上述の如く、本発明のチップキャリアは、
半導体チップ（３）が搭載され、上記導電回路（４）の
一部と半導体チップ（３）をボンデイングワイヤー
（９）により接続し、その上に耐湿性を高めるために封
止剤（１０）により封止して半導体装置を構成するのに
有用である。As described above, the chip carrier of the present invention is
A semiconductor chip (3) is mounted, a part of the conductive circuit (4) and the semiconductor chip (3) are connected by a bonding wire (9), and a sealing agent (10) is added on the semiconductor chip (3) to improve moisture resistance. It is useful for forming a semiconductor device by sealing.
【００１６】[0016]
【発明の効果】本発明のチップキャリアは、プリント配
線板（１）の背面にスルホール（８）を有する絶縁層
（６）を備えているので、プリント配線板（１）とマザ
ーボードの回路との間の絶縁性を確保できるので、ショ
ート不良が起こらない。Since the chip carrier of the present invention is provided with the insulating layer (6) having the through holes (8) on the back surface of the printed wiring board (1), the printed wiring board (1) and the circuit of the mother board are separated from each other. Insulation between them can be secured, so short-circuit defects do not occur.
【図１】本発明の一実施例に係るチップキャリアを用い
た半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device using a chip carrier according to an embodiment of the present invention.
【図２】従来例のチップキャリアを用いた半導体装置の
断面図である。FIG. 2 is a cross-sectional view of a semiconductor device using a conventional chip carrier.
１ プリント配線板 ２ バンプ ３ 半導体チップ ４ 導電回路 ５ 回路パッド ６ 絶縁層 ８ スルホール ９ ボンデイングワイヤー １０ 封止剤 1 Printed Wiring Board 2 Bump 3 Semiconductor Chip 4 Conductive Circuit 5 Circuit Pad 6 Insulating Layer 8 Through Hole 9 Bonding Wire 10 Sealant
Claims (2)
配線板（１）の背面に、外部入出力の端子であるバンプ
（２）を形成するチップキャリアにおいて、上記プリン
ト配線板（１）の背面に、回路パッド（５）の位置にス
ルホール（８）を備えた絶縁層（６）が形成され、且つ
このスルホール（８）を貫通する上記バンプ（２）が形
成されていることを特徴とするチップキャリア。1. A chip carrier in which bumps (2) which are terminals for external input / output are formed on the back surface of a printed wiring board (1) on which a semiconductor chip (3) is mounted, the back surface of the printed wiring board (1). An insulating layer (6) having a through hole (8) at the position of the circuit pad (5), and the bump (2) penetrating the through hole (8). Chip carrier.
備えた絶縁樹脂基板であることを特徴とするチップキャ
リア。2. A chip carrier, wherein the insulating layer (6) is an insulating resin substrate having through holes (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5031894A JPH06252286A (en) | 1993-02-22 | 1993-02-22 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5031894A JPH06252286A (en) | 1993-02-22 | 1993-02-22 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06252286A true JPH06252286A (en) | 1994-09-09 |
Family
ID=12343731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5031894A Pending JPH06252286A (en) | 1993-02-22 | 1993-02-22 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06252286A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0729182A3 (en) * | 1995-02-23 | 1997-02-19 | Matsushita Electric Industrial Co Ltd | Chip carrier, associated manufacturing and assembly |
-
1993
- 1993-02-22 JP JP5031894A patent/JPH06252286A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0729182A3 (en) * | 1995-02-23 | 1997-02-19 | Matsushita Electric Industrial Co Ltd | Chip carrier, associated manufacturing and assembly |
| US6229209B1 (en) | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
| US6365499B1 (en) | 1995-02-23 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | Chip carrier and method of manufacturing and mounting the same |
| US6372547B2 (en) | 1995-02-23 | 2002-04-16 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board |
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