JPH06275696A - Semiconductor failure analysis system and compression method of analysis data thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] In a semiconductor failure analysis system, analysis with higher measurement accuracy is performed in response to higher integration of semiconductors. It also provides an easy-to-use user interface to facilitate analysis. Furthermore, the analysis data is compressed efficiently. [Structure] An LSI for data analysis having an FB analysis system 105, an inspection data analysis system 101, and a tester
It has design information 107. Further, the defect information, analysis data, or inspection conditions are displayed on the display device using a multi-window. Further, the storage form is made different depending on the form in which a defective bit is generated during data compression of analysis data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect analysis system, and more particularly to a system suitable for analyzing the cause of defects in a wafer process in semiconductor manufacturing technology.

[0002]

2. Description of the Related Art Conventionally, a failure analysis method and system in semiconductor manufacturing technology is disclosed in, for example, Japanese Patent Laid-Open No. 62-62.
No. 169342, JP-A-61-243378, JP-A-59-228726, and JP-A-3-44054.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Japanese Patent No. 28726 and Japanese Patent Laid-Open No. 3-44054 disclose a technique of analyzing a failure of a semiconductor wafer using a computer system. However, the above-mentioned conventional technique relates to a method of performing semiconductor failure analysis on a chip-by-chip basis. Therefore, especially when analyzing a semiconductor memory device for defects, it is not only necessary to analyze the product characteristics of the chip,
No consideration is given to the need to analyze defects.

Therefore, a defective bit (fail bit,
In order to analyze the cause of the "FB" (hereinafter abbreviated as "FB"), the product characteristic inspection device for the chip (hereinafter referred to as "tester")
The address of each defective bit is found on the chip by referring to the chip size, the memory allocation method on the chip, etc. I was observing. For example, when a worker observes a microscope and finds a foreign matter in a defective portion, he concludes that the defectiveness is caused by the foreign matter.

As described above, in the past, a great deal of labor was required to analyze the FB bit by bit. Therefore, it is necessary to reduce the labor and meet the demand for smoothly performing the failure analysis as a system bit by bit. In that case, conventionally, since the coordinates for measuring at the defective position are provided for each wafer, there is a problem that an error becomes large when the position of the memory cell in the chip is known.

Especially, in recent years, since the integration degree of the semiconductor memory tends to be large, such an error becomes a large barrier for failure analysis. Further, in the above-mentioned conventional technology, the characteristics such as the arrangement of the memory mat in the chip and the size of the memory cell are different depending on the type of chip.
There is no consideration for smooth response. Further, in a semiconductor failure analysis system, an observation device such as an electron microscope and an analysis device such as an infrared absorption spectroscopy spectroscope are used.
When analyzing the above, there is a problem that even if the origins on the memory cells are made to coincide with each other, a minute shift occurs due to the characteristics of each device.

Next, JP-A-62-169342 and JP-A-61-243378 relate to compression of data concerning FB information on a cell of a semiconductor memory to be inspected. However, JP-A-62-169
The data compression method disclosed in Japanese Patent No. 342 is not necessarily suitable for analyzing a large capacity memory cell. The reason is that in this compression method, memory cells are divided into blocks and a model reduced to 1 / n ² is made.
For example, even if n = 100, only a compression ratio of at most 1 / 10,000 can be obtained, and a huge amount of data is required in the case of a memory having a capacity of several Mbits.

Another reason is that, regardless of the defective pattern in one block, the defective pattern is compressed into the same format, and the detailed information of the bit position is lost. Furthermore, JP-A-61-1
The data compression method disclosed in Japanese Patent No. 243378 does not lose information as described above, but it is not necessarily an efficient data compression method suitable for a large capacity memory cell.

The reason is that the FB information is held as a pair of the coordinate position of the start point and the coordinate position of the end point, so that the efficiency is improved when the FB is continuous, but the isolated F is isolated.
This is because the same storage capacity is required for B as well, so that if there are many isolated FBs, the data compression rate will be poor as a result. This inefficiency is because data compression is performed uniformly regardless of the pattern in which FB occurs. Therefore, there is a demand for a method of compressing data according to the FB generation pattern and storing it.

Next, Japanese Patent Application Laid-Open No. 3-44054 discloses a technique for displaying an analysis result on a display device of a computer system. However, the above-mentioned related art does not consider a means for systematically considering defect analysis result information from a number of viewpoints regarding the system user interface.

That is, a display showing the analysis of defective bits on the entire wafer, a display showing the distribution of defective bits on an arbitrary chip, an enlarged display of the distribution of defective bits in a partial area within the chip, on an arbitrary shot. It is not taken into consideration that the failure analysis result information such as the display showing the distribution of the defective bits and the display showing the distribution of the defective bits in a partial area in the shot are enlarged quickly and smoothly. Even when these pieces of information are not displayed on the display device or are displayed, an operation such as screen switching is required. Therefore, it is often necessary for the user to perform a very troublesome operation.

Further, regarding the user interface of the system, no method has been proposed in the above prior art for visually confirming the size of the memory cell when displaying on the display device. Further, in the above-mentioned conventional technique, it is not taken into consideration that the test condition at the time of inspection is an important factor for a person who performs failure analysis.

That is, a method for a person who conducts a failure analysis to find out the cause of the failure by variously changing the test conditions is usually performed. In such a case, it would be very inefficient if the inspection target and the test condition were collated in writing or the like.

Next, as a semiconductor defect analysis technique, a method of stacking wafers and analyzing the cause of the defect is known. However, when there is a defect in the photomask during exposure of the wafer, no consideration has been given to means for effectively determining the cause of the defect.

Next, Japanese Laid-Open Patent Publication No. 3-44054 describes a technique of processing a semiconductor failure analysis result by using a computer system and editing the result. However, the above-mentioned conventional technique does not indicate past inspection history or inspection method to be performed in the future.

Therefore, conventionally, it has been necessary for a person who performs failure analysis to collate the inspection history of the object to be inspected. Further, since the semiconductor manufacturing process is divided into many stages, it is necessary to make an inspection plan for which process is to be re-inspected according to the inspection result. This planning is extremely difficult even for a skilled person because of various patterns.

The present invention has been made to solve the above-mentioned problems of the prior art. A first object of the present invention is to cope with high integration of a semiconductor memory and to analyze FB defects.
A failure analysis method with higher measurement accuracy, and a failure analysis method capable of smoothly responding to characteristics caused by the type of each chip,
An object of the present invention is to provide a semiconductor failure analysis system capable of correcting a measurement deviation selected for the characteristics of the observation device and analysis device used in the system.

The second purpose is to cope with the recent high integration of semiconductor memory, and regardless of the pattern of FB generated in a memory cell, a semiconductor that efficiently compresses data without loss of information. The object of the present invention is to provide a data compression method of analysis data used in the defect analysis system of.

A third object of the present invention is to provide a semiconductor failure analysis system capable of simultaneously or immediately acquiring various inspection results regarding the system user interface.

A fourth object of the invention is to provide a semiconductor failure analysis system for simultaneously displaying test conditions and inspection results.

A fifth object is to provide a semiconductor failure analysis system capable of visually confirming the size of a memory cell when displaying on a display device.

A sixth object of the present invention is to provide a failure analysis method of a semiconductor failure analysis system capable of effectively determining the cause of a failure when a photomask has a failure during exposure of a wafer.

A seventh object thereof is a failure analysis method for immediately obtaining an inspection history of an object to be inspected at the time of failure analysis, and a semiconductor analysis method for automatically obtaining a future inspection method according to the inspection result. It is to provide a failure analysis system. ,

[0024]

In order to achieve the above first object, the structure of the first invention relating to the semiconductor failure analysis system of the present invention has a means for collecting semiconductor failure information and a semiconductor failure information collecting means. It is a semiconductor defect analysis system characterized by having means for inspecting defect information and means for performing data analysis of the defect information, and having semiconductor design information used for the data analysis.

As another configuration, a means for collecting semiconductor defect information, a means for inspecting semiconductor defect information, a means for data analysis of the defect information, and the defect information are displayed. And a design information of a semiconductor used for displaying the defect information.

Further, as another configuration, there are provided means for collecting semiconductor defect information, a device for inspecting semiconductor defect information, and means for performing data analysis of the defect information, and data analysis thereof. The semiconductor defect analysis system is characterized by having information of the inspection device used at the time.

In order to achieve the above second object, the structure of the invention relating to the data compression method of analysis data used in the semiconductor defect analysis system of the present invention has a means for collecting semiconductor defect information and a semiconductor defect. A means for inspecting information, a means for storing the defect information, a means for compressing the defect information, and a storage mode that is different depending on the mode in which the defect information is generated when the compression is performed. It is a data compression method of analysis data used in a semiconductor failure analysis system.

In order to achieve the above third object, the configuration of the second invention relating to the semiconductor failure analysis system of the present invention is a means for collecting semiconductor failure information and a means for inspecting semiconductor failure information. And a means for performing data analysis of the defect information, and a device for displaying the defect information, analysis data, or inspection conditions.
A defect analysis system for a semiconductor, wherein defect information, analysis data, or inspection conditions are simultaneously displayed in a plurality of windows or individual windows.

In order to achieve the above-mentioned fourth object, the structure of the third invention relating to the semiconductor failure analysis system of the present invention relates to a semiconductor failure analysis system, and means for collecting semiconductor failure information, The semiconductor device has a means for inspecting defect information of a semiconductor, a means for analyzing data of the defect information, and a device for displaying the defect information or analysis data or inspection conditions. It is a semiconductor failure analysis system characterized by simultaneously displaying data and inspection conditions on the same screen of the display device.

In order to achieve the above fifth object, the configuration of the fourth invention relating to the semiconductor failure analysis system of the present invention is a means for collecting semiconductor failure information and a means for inspecting semiconductor failure information. And a unit for performing data analysis of the defect information and a device for displaying the defect information or analysis data, and displaying the inspection target and the scale of the inspection target at the same time on the display device. It is a semiconductor failure analysis system characterized by:

In order to achieve the sixth object, the configuration of the invention relating to the failure analysis method of the semiconductor failure analysis system of the present invention has a means for collecting semiconductor failure information and an inspection of the semiconductor failure information. Means, a means for performing data analysis of defect information thereof, and a semiconductor defect analysis method characterized by superposing the inspection results for each exposure unit.

More specifically, means for collecting semiconductor defect information, means for inspecting semiconductor defect information, means for data analysis of the defect information, and apparatus for displaying the defect information or analysis data. The semiconductor defect analysis method is characterized in that the inspection result is superposed for each exposure unit and the result is displayed on the display device.

In order to achieve the seventh object, the configuration of the fifth invention relating to the semiconductor failure analysis system of the present invention is a means for collecting semiconductor failure information and a means for inspecting semiconductor failure information. And a means for specifying the inspection target, a means for managing the inspection history of the inspection target, an inspection history database for the inspection target, and a device for displaying the inspection history, and a display device thereof. The semiconductor defect analysis system is characterized in that the inspection history of the object to be inspected is displayed on.

In order to achieve the seventh object, the configuration of the sixth invention relating to the semiconductor failure analysis system of the present invention is a means for collecting semiconductor failure information and a means for inspecting semiconductor failure information. And a means for specifying the inspected object, a means for managing the inspection history of the inspected object, an inspection history database of the inspected object, and an inspection content or an inspection process by the inspection history of the inspected object And a device for displaying the inspection content or the instruction of the inspection process, and displaying the inspection content of the inspection target or the instruction of the inspection process on the display device. Is.

[0035]

As the invention relating to the first semiconductor failure analysis system, since the configuration is such that the design information such as the layout information of the memory cells corresponding to each chip type is referred to, the coordinate system based on one chip can be adopted. The measurement accuracy can be improved. Further, since the configuration is such that the design information such as the correction value according to the characteristics of each observation device and the analysis device is referred to, the correction related to the device becomes easy, and the measurement accuracy is improved also from this point.

As an invention relating to a data compression method of analysis data used in a semiconductor failure analysis system, the data compression method is made different for each FB generation pattern so that only the minimum necessary information is held. The efficiency of compression can be improved. Further, since the storage files are made different for each generation pattern of each FB, the data does not have to have a pattern type, which also contributes to the efficiency of data compression. Furthermore, there is no loss of information found in the prior art.

As an invention relating to the second semiconductor failure analysis system, since the inspection result is displayed by using the multi-window on the display device, the user can obtain the inspection result at the same time or immediately, and the work is easy. Therefore, the accuracy of the judgment can be expected.

As an invention relating to a third semiconductor failure analysis system, since the inspection result and the test condition are simultaneously displayed on the display device, the labor for investigation is reduced, and the test condition is changed and the inspection is performed again. Will be easier.

According to the fourth semiconductor defect analysis system of the present invention, since the scale is displayed on the display screen of the memory cell displayed on the display device, it is easy to understand visually.
As an invention relating to a failure analysis method of a semiconductor failure analysis system, by stacking wafers for each exposure shot unit,
Since the defect is identified, it becomes easier to identify the defect caused in the defect of the mask during the exposure.

In the invention relating to the fifth semiconductor failure analysis system, since the history of the object to be inspected is immediately acquired, it is not necessary to examine the inspection history.

In the invention relating to the sixth semiconductor failure analysis system, an inspection method to be performed in the future can be automatically obtained according to the inspection result, so that it is not necessary to carry out planning for reinspection. It is possible to omit various inspections, and more appropriate and quick inspections can be performed.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS.

[I] First, the basic concept of the failure analysis system according to the present invention will be described with reference to FIG. FIG. 1 is a basic conceptual diagram of a failure analysis system according to the present invention.

The inspection data analysis system 101 performs analysis based on the data obtained from the foreign substance inspection 102 and the appearance inspection 103 on the manufacturing line and the data obtained from the tester 1 (104) in the final wafer inspection.

The FB analysis system 105 uses the data obtained from the tester 2 (106) and the L
The SI design information 107 is used to extract defective points and defective points from the FB distribution shape, and the defective cause is estimated by referring to the defective cause know-how information 108.

Further, the observing device 109 observes the coordinates of the defective portion and the defective induction point portion passed from the FB analysis system, and specifies the defective cause and the defective process. Analyzer 1
Reference numeral 10 analyzes a component such as a foreign substance detected by the observation device 109 to identify a cause of a defect and a defective process.

[II] Next, the FB analysis system and the chips and L on the semiconductor wafer (hereinafter simply referred to as “wafer”).
The SI design information will be described with reference to FIGS. First, the FB analysis system 105 will be described with reference to FIG. FIG. 2 is a conceptual diagram showing a detailed configuration of the FB analysis system.

The FB analysis system 105 uses the LSI design information a20 having LSI design data (product type, array information).
1 and a physical conversion 202 for converting the test data into physical data. Further, the data compression means 203
, Data management means 204, pixel conversion means 205, and L
It has SI design information b206, FB distribution feature extraction means 207, means 208 for estimating the cause of defects, and a display device 209. The FB analysis system 105 has a function of compressing physical data and storing it in the FB database 111.

Further, if necessary, the data management means 204
Search and recall the saved data via. When the operation is performed using the mouse 211, workability is improved. Next, pixel conversion 205 is performed, and the position of the defective bit within the wafer or within the chip is displayed on the display device 209. At this time, the FB distribution feature extraction means 207 is operated, the defect cause know-how information 108 is referred to, and the defect cause is estimated 208.
Furthermore, in the case of performing detailed analysis, the feature-extracted coordinates are passed to the observation device 109 and the analysis device 111. Then, from the tester 2 (106), the product type, date, lot number, wafer number, bit address,
Various kinds of information such as good and bad bits are transferred.

Next, with reference to FIGS. 3 and 4, the state of chips on a semiconductor wafer (hereinafter simply referred to as “wafer”),
The structure in the chip is shown. FIG. 3 is a diagram showing the state of the chips arranged on the wafer.

It is in a state of being built in a rectangular plate-shaped chip which is vertically and horizontally arranged on a semiconductor wafer to be inspected. The position of the chip in the wafer can be expressed as (4, 3) as shown in FIG.

FIG. 4 is a diagram showing the internal structure of the chip.
A mark 401 indicating the origin of the chip is shown at the end of the chip. A plurality of external terminals 40 are provided around the chip.
3 (bonding pads) are arranged.

A memory mat having a large capacity of 4 megabits, for example, is arranged in the central portion of the chip. This memory mat is divided into four from the first memory mat 404 to the fourth memory mat 407. Each of the four divided memory mats has a capacity of 1 megabit. A peripheral circuit 402 including a decoder circuit is provided between the first memory mat 404 and the second memory mat 405.
Are arranged. Similarly, the peripheral circuit 408 is also arranged between the third memory mat 406 and the fourth memory mat 407.

Further, in the first memory mat 404, memory cells (hereinafter, simply referred to as "cells") are arranged on a square as shown in FIG. The cells are sequentially arranged in the horizontal / forward direction Xa and the vertical / forward direction Y from the left side to the right side in the figure. In the second memory mat 405, the cell groups are sequentially arranged in the horizontal / reverse direction Xb and the vertical / forward direction Y from the right side to the left side in the drawing with the peripheral circuit 402 interposed. That is, in the second memory mat 405, the cell group is the first
The coordinate system is set by the mirror inversion pattern of the memory mat 404.

The third memory mat 406 is similar to the first memory mat 404, and the fourth memory mat 4 is
Similarly to the second memory mat 405, cell group 07 is sequentially arranged.

Now, the LSI design information 107 will be described. The addition of this LSI design information 107 to the system is the core of the present invention. The LSI design information 107 includes wafer size, chip size, memory cell size, chip arrangement information in a wafer, number of memory mats in a chip, and memory in a memory mat, in addition to the above-mentioned arrangement position and size information of the memory mat. Number of cells,
It includes the position coordinates of a coordinate reference pattern for determining the coordinates within the chip, correction values caused by the characteristics of the individual observing device and analyzer during measurement, and other information for conducting defect analysis of many semiconductors.

In the FB analysis system 105, this L
The FB is analyzed with reference to the SI design information 107. The advantages of having the LSI design information 107 are as follows.

The first advantage is that by displaying the wafers, chips, etc. based on the design information, the user can perform an analysis under the actual display, and the cause of failure can be investigated. Easy to do.

The second advantage is that the measurement accuracy is improved because the origin can be taken in the memory chip to identify the FB because it has the arrangement information in the memory chip. In the prior art, since the coordinates shown in FIG. 3 were taken, the sizes of the grooves between the chips tended to be uneven, and the error was large.

A third advantage is that since the LSI design information 107 needs to be replaced for each type of chip, the flexibility of the system is improved and a defect analysis system for chips of different types can be constructed more easily. Is.

The fourth advantage is that the LSI design information 10
Since the correction values when the observation device and the analysis device are used are held in 7, the improvement of the accuracy when these devices are used can be expected.

The fourth advantage is that the LSI design information 10
Since the correction values when the observation device and the analysis device are used are held in 7, the improvement of the accuracy when these devices are used can be expected.

As a fifth advantage, by holding the size of each memory cell as the LSI design information 107, the cell address information and the length information using the observing device and the analyzing device can be easily and accurately converted. It is possible to convert.

By adding the LSI design information 107 to the system, the advantages described above are obtained, and the availability and flexibility of the system are improved.

[III] Next, the data processing steps of the FB, particularly the data compression method and its decompression method will be described in detail with reference to FIGS. 5 to 9 and Tables 1 and 2. First, the concept of the data compression method according to the present embodiment and the method of holding compressed data will be described with reference to FIG. 6 and Tables 1 and 2.

FIG. 6 is a diagram showing various FB patterns in the chip. As internal data, it is common to have a good bit as 0 and a bad bit (FB) as 1 and have it as 1-bit information, but in FIG. 6, the good bit is blank and the problematic bad bit (FB) is 1 Is displayed.

Table 1 is a table showing how to compress each pattern of FIG.

[Table 1]

Table 2 is a table showing the number of bits required for compression in accordance with each pattern of FIG.

[Table 2]

As shown in FIG. 6, the present compression method is characterized in that the pattern generated in the cell is divided into six types, and the compression methods are made different. Table 1 shows how to compress each pattern in FIG.
Note that each pattern in FIG. 6 will be referred to by the notation described in the second column of Table 1.

Here, it is necessary to keep in mind that the data is held without information about the shape pattern. This is because the compressed data can be identified by taking measures such as making the stored files different. In this respect as well, improvement of the data compression rate can be expected. The number of bits required for storage is as shown in Table 2,
Since only the optimum stored bit is required according to each pattern, the effect of memory compression becomes greater as the FB to be compressed has a larger capacity.

Here, a method of actually compressing the data thus classified will be described with reference to FIGS. 7 and 9. FIG. 7 is a diagram showing a method of dividing the FB group (diagonalization). FIG. 8 is a diagram showing how to hold diagonalization data. FIG. 9 is a diagram showing an FB group division method (vectorization) and a data holding method.

In the following, it will also be explained that the above six types of patterns can be covered by a technique called diagonalization and vectorization in order to perform compression easily. In this case, 2
Since the compression is performed according to the type, the compression rate is slightly worse than when performing compression for every six types, but there is an advantage that the algorithm (a program for realizing) is simple.

In the method called diagonalization, as shown in FIG. 7, an FB block (hereinafter referred to as "FB group") is divided into several rectangles. Then, each rectangular FB data is compressed. As a method of holding data, as shown in FIG. 8, (x1, y1, x2, y2) is set, and (x1, y
1) and (x2, y2) are diagonal coordinates of a rectangle. When a line is missing or a pair of bits is missing when the rectangle is divided, the leading bit and the ending bit are used as diagonal coordinates. When it becomes an isolated point, (x1, y1) = (x2,
y2).

Next, a method called vectorization will be described. In this method, as shown in FIG. 9, the FB group is divided into several line-misses, and the coordinates (x, y) of the leading bit of each line-miss and the number k of FBs forming the line-misses are taken as data values. To do. That is, the compressed data has a form of (x, y, k). When an isolated point is generated by dividing the line into missing lines, it is sufficient to have the data as (x, y, 1).

Next, a data compression algorithm will be described with reference to FIGS. 5 and 10 to 13. First, the physical conversion algorithm will be described. The physical conversion is to replace the information in the logical coordinate system in FIG. 4 with information in which memory cells are arranged in a unified manner.

FIG. 5 is a diagram showing a schematic flow of physical conversion. First, read the data (step 50
1). Next, the LSI design data of the corresponding product type is called in (step 502). Next, the design information of the memory configured in the mirror inversion pattern is rearranged in the forward direction (step 503).

Next, 1 is set in the Y direction from the lower left bit in FIG.
Each bit is recorded as good or bad (step 50).
4). When one column has been read in the Y direction, it is shifted one by one in the X direction, and similarly, one bit in the Y direction is recorded as good and one defect in each bit. When all the bits are recorded as good or bad, the process ends (step 505). Next, the entire flow from reading the data to compression storage, decompression, and display will be described.

FIG. 10 is a diagram showing a flow of a method of selectively using some compression methods for each FB shape in the chip. More specifically, FIG. 10 shows a method of selectively using several compression methods for each FB shape in the chip as described above, that is, diagonalization in the case of block missing, and vector in the case of vertical and horizontal line missing. Is a flow chart of a method in which the coordinate (x, y) of the leading bit is used as a data value in the case of verticalization, vertical, and horizontal pair bits are missing, and the bit value (x, y) is used as a data value in the case of an isolated point.

However, these flow charts are for compression, decompression, and display for one wafer. Therefore, when performing on multiple wafers,
You just have to repeat this flow.

In the following, with reference to FIG. 10, description will be given on the general procedure for properly storing some compression methods for each shape in the chip.

First, the type of data to be handled is recognized (step 1001). Next, put the test data on the memory.
Bit by bit is read (step 1002). Then, in order to give the data two-dimensional coordinates, a return code is inserted every N bytes (step 1003). However, N
Is the number of bits arranged in the horizontal direction of the chip, and the position where the return code is inserted differs depending on the product type.

Next, the shape of the FB in the chip is recognized (step 1004). And (step 1004)
A compression method is used for each shape, such as block missing is diagonalization and line missing is vectorization (step 10).
05). Then, data compression is performed (step 100).
6). Next, it is checked whether data compression has been performed for all the shapes in the chip (step 1007).

If all the data in the chip have not been compressed, the loop of (step 1008) is repeated. If the compression has been completed, the compressed data for one chip is stored in the hard disk (step 1009).
It should be noted that the created compressed data does not need to intentionally have a parameter for distinguishing the shapes in the compressed data if the storage area is changed for each shape in the chip.

Next, it is checked whether the data of all chips have been saved (step 1010). If the storage for all chips has not been completed, the loop of step 1011 is repeated.

Next, with reference to FIG. 11, a schematic procedure for selecting a compression method for each chip and storing it will be described. That is, it is a compression method in which the shape is recognized on a chip-by-chip basis and the optimum method of vectorization or diagonalization is selected.

FIG. 11 is a diagram showing a flow of a method for selecting a compression method for each chip. First, the type of data to be handled is recognized (step 1101). Next, the test data is read into the memory in units of 8 bits (step 110).
2). Then, in order to give the data two-dimensional coordinates, N
Enter a return code for each byte (step 110)
3). However, N is the number of bits lined up in the horizontal direction of the chip, and therefore the position where the return code is inserted differs depending on the product type.

Next, the shape of the FB in the chip is recognized (step 1104). At this time, the number of each shape is counted. Next, one compression method is selected according to the situation of (step 1104) (step 1105). That is, 1
If the total amount of line loss before compression in the chip is higher than that of other shapes, select the vectorization method, and if the total amount of block loss before compression is high, select the diagonalization method. That is. In the case of an isolated point, whichever method is used, the format of the stored data is the same as (x, y), so either method may be selected. In this embodiment, a diagonal ratio method is selected. Then, data compression is performed (step 1106).

Next, the compressed data for one chip is stored in the hard disk (step 1107). Next, it is checked whether the data for one wafer has been stored (step 1108). If the data of all the chips has not been stored yet, the loop of (step 1109) is repeated. You may replace with the method of selecting a compression method for every wafer. Next, decompression and display of compressed data will be described with reference to FIG. Through the following data processing, the operator can display the tester data on the display device, and
It becomes possible to analyze the distribution of B.

FIG. 12 is a diagram showing a flow for restoring and displaying data for one wafer. In this embodiment, in particular, as a display device, there are approximately 480 vertical pixels and 6 horizontal pixels.
An example using a 40-pixel CRT is shown.

The compressed data for one wafer is called from the hard disk (step 1201). Next, in order to perform high-speed screen display, an operation called pixel conversion is performed (step 1202). Then, the obtained coordinates are displayed (step 1203).

The pixel conversion will be supplemented below. This pixel conversion is performed using only compressed data. Due to the resolution of the CRT, the wafer (in the case of a chip with a memory capacity of 1 mega, the vertical length of the chip is 2048 bits,
(The width is 512 bits, about 150 chips per wafer)
Depending on the standard, one memory cell may not be displayed by one pixel. Therefore, image compression is performed and the entire wafer is displayed. The processing at this time is pixel conversion.

In the case of displaying a wafer of chips having m bits in the vertical direction and n bits in the horizontal direction, this processing is 1 / s in the vertical direction and 1 in the horizontal direction.
Reduced display at / t. Therefore, an area of vertical s bits and horizontal t bits is displayed by one pixel on the CRT. Therefore, if even one bit of FB is included in this area, the entire area is displayed as an FB area. Taking block missing data (x1, y1, x2, y2) as an example of actual processing, the diagonal coordinates of the compressed data are each divided by the number of bits k per pixel, and the coordinates on the CRT (x1 / k, y1 /
k, x2 / k, y2 / k) may be obtained.

Next, the detailed algorithm of compression will be described with reference to FIG. As described above, this method divides the compression method for each shape of the FB and efficiently performs data compression. That is, this is the most efficient compression method in which the storage method is changed for each of the 6 types of FB patterns. Here, a specific compression algorithm for that purpose will be shown.

FIG. 13 is a diagram showing a detailed flow in the case of performing data compression for each FB shape in the chip. Here, the method of obtaining the coordinates follows FIG. Therefore, the origin is the bit at the lower left corner of FIG. This method is
Although the compression method is selected for each shape of B to efficiently perform data compression, the compression method may be selected for each wafer or each chip.

First, the data obtained from the tester is read, and all bits have two-dimensional coordinates (step 130).
1). Then, the variables k, p, and r are given an initial value of 1, and the variable q is given an initial value of 0 (step 1302).
Next, the bit value (0 or 1) is sequentially read from the origin (0, 0), and the reading is continued until the bit value becomes 0 (step 1303). It is checked whether or not all the bits of the read bit are 0 (step 1304).

If this condition is not satisfied, the coordinates of the bit whose value is 1 are set to A (i, j) and the A (i, j)
bit A (i + k, j) on the right of j) = 1 (where k =
It is checked whether it is 1) (step 1305). If this condition is satisfied, the value of k is updated by 1 (step 130).
6) Repeat this operation until the value of A (i + k, j) becomes 0. Then, in (step 1305), A (i +
When the value of k, j) becomes 0, it is checked whether k = 1 (step 1307),

If this condition is satisfied, the value A (i, j + p) = 1 (where p = 1) immediately above A (i, j) is checked (step 1308). If A (i, j + p) = 1
If so, the value of p is updated by 1 (step 1309), and A
This operation is repeated until (i, j + p) = 0.
At (step 1308), when A (i, j + p) = 0, it is checked whether p = 1 (step 1310). If the condition is satisfied, the compressed data A (i,
j) is created (step 1311),

This data is saved (step 1312). Then, the value of the data in the compressed area is rewritten from 1 to 0 (step 1313). (Step 1314)
If p ≠ 2, compressed data A (i, j, p) is created as vertical line missing data (step 1315) and the data is saved (step 1312).

Then, the value of the data in the compressed area is rewritten from 1 to 0 (step 1313). (Step 1
If k ≠ 1 in 307), the value A just above A (i, j)
It is checked whether (i, j + p) = 1 (where p = 1) (step 1317), and if the condition is satisfied, the value of p is set to 1
It is updated (step 1318) and this operation is repeated until A (i, j + p) ≠ 1. When A (i, j + p) ≠ 1, it is checked whether p = 1 (step 1319),
If the condition is satisfied, it is checked whether k = 2 (step 132).
0).

If the condition is satisfied, horizontal pair bit missing data is created (step 1311) and compressed data A
(I, j) is created (step 1321) and the data is saved (step 1312). Then, the value of the data in the compressed area is rewritten from 1 to 0 (step 131).
3). If k ≠ 2 in (step 1307), compressed data A (i, j, k) is created as horizontal line missing data (step 1322), and the data is saved (step 1).
312).

Then, the value of the data in the compressed area is rewritten from 1 to 0 (step 1313). (Step 1
319), if p ≠ 1, A (i + r, j + q) = 1
(However, r = 1, q = 0) is checked (step 1
323), if the condition is satisfied, the value of q is updated by 1 (step 1324), and this operation is repeated until A (i + r, j + q) ≠ 1. Then, A (i + r, j + q) ≠
When it becomes 1, it is checked whether p = q (step 132).
5),

If the condition is satisfied, the value of r is updated by 1 (step 1326) and q = 0 is set (step 132).
7). If p ≠ q, check whether r = 1 (step 13
28) If the condition is satisfied, the number of consecutive bits in the x and y directions with A (i, j) = 1 as a reference is compared to create the longer line missing data (step 1329). This data is saved (step 1312), and the value of the data in the compressed area is rewritten from 1 to 0 (step 131).
3).

If r ≠ 1 in step 1328, compressed data A (i, j, i +) is determined as block missing data.
r-1, j + q-1) is created (step 132).
2). Then, this data is saved (step 131).
2) Rewrite the value of the data in the compressed area from 1 to 0 (step 1313). If all the bit values are 0 in (step 1304), compressed data for one chip is stored in the hard disk (step 1331) and it is checked whether all the data in the wafer has been stored (step 133).
2). If the condition is satisfied, the data for one wafer has been compressed (step 1332).

If the condition is not satisfied in step 1332, the above operation is repeated for another chip.
It should be noted that when saving all data, they are saved in separate storage areas.

[IV] In the following, it will be described how chip defects are displayed and the analysis proceeds. The operator searches the FB data regarding a desired wafer by designating a product type, a lot number, a wafer number, and the like. The retrieved data is restored from the compressed state and displayed on the display device.

The display format is shown in FIGS. 14 to 27. First, the screen configuration of this system will be described with reference to FIG. FIG. 14 is a diagram showing a configuration of a screen of the system displayed on the display device. As shown in FIG. 14, the analysis screen of this system is mainly divided into four.

On the main screen 1401, a portion to be analyzed is displayed. On the sub-screen 1 (1402), the data (product name, lot number, wafer No., size, ...) About the item being analyzed and the tester measurement conditions (power supply voltage, operating temperature, access time, ...). .) Is displayed. On the sub-screen 2 (1403), the category within the wafer (classification performed on chips in the wafer for inspection) and the like are displayed. On the sub screen 3 (1404), the mat structure in the chip and the like are displayed. Also, sub-windows are opened as needed.

Now, the advantage of displaying the test measurement conditions displayed on the sub-screen 1 (1402) will be described. Semiconductor defects can be broadly classified into defects that occur due to problems in the setting of standard values of tester measurement conditions such as power supply voltage and measurement temperature, and defects that occur due to problems in the manufacturing process. In the former case, when a defect occurs within the standard value of each measurement condition, it is important to investigate what kind of condition causes the number of defects to increase or decrease and the cause. Therefore, the test conditions and the like are displayed on the sub screen 1 (1402).

By displaying the conditions, it becomes clear whether the measurement is performed within the standard value or outside the standard value, so that the analysis can be efficiently performed. For example, it is assumed that FB occurs when the measurement is performed according to the standard value.
Therefore, in order to investigate the cause of FB generation, the width of the standard value is narrowed by the value of the power supply voltage, and the difference is compared. If a new FB occurs, it is considered that the margin of the power supply voltage is insufficient.

On the contrary, if a new FB does not occur even if the standard value of the power supply voltage is changed, the value is changed under other measurement conditions to perform the measurement, and if the same result is obtained in all the measurements, This FB is considered to have a problem in the manufacturing process such as foreign matter and poor appearance.

Now, a case where the failure analysis is actually carried out by a concrete example will be described below with reference to FIGS. FIG. 15 is a diagram showing an example of distribution display of FBs on a wafer displayed on a display device. FIG.
FIG. 7 is a diagram showing an example of distribution display of FBs in a chip displayed on a display device. FIG. 17 is a diagram showing an example of distribution display of FBs in the mat displayed on the display device.
FIG. 18 is a diagram showing an example of distribution display of FBs within a shot displayed on the display device.

As shown in FIG. 15, the whole wafer image is shown, and the distribution of FB in each chip is displayed therein. The operator selects the chip display from the menu and designates a desired chip from the sub screen 2 (1501) using a mouse or the like. When the desired chip is specified,
The entire chip image as shown in 6 is displayed. The distribution of FBs in the chip is displayed on the whole chip image. Sub screen 3
(1601) shows the mat structure in the chip. The operator selects the mat display from the menu and designates the desired mat with the mouse or the like from the sub-screen 3 (1601), and the screen shown in FIG. The entire mat image is displayed as shown.

When a shot display is selected from the menu 1503 and a desired chip is selected on the sub screen 1 (1501), a shot including the designated chip is displayed as shown in FIG. Here, a shot is an exposure unit in which an exposure apparatus exposes a plurality of chips at one time. Also, when displaying as described above, as shown in FIG. 3, the orientation flat side (the lower part where the wafer is flat)
Is the X axis, the left side is the Y axis, and the intersection of the X and Y axes is the origin.
The numbers indicating the chip positions on the wafer are 1504 and 1505 in the case of wafer display and 160 in the case of chip display.
By displaying 2 and 1603 respectively, the position of the chip in the displayed wafer is made clear to the person performing the analysis.

From the same viewpoint, in the case of mat display, the mat positions in the chip are displayed on 1701 and 1702 for the convenience of the analyst.

Next, the case where the enlargement function is used when the analyst wants to know the detailed FB distribution in bit units will be described with reference to FIGS. 19 to 20. FIG. 19
FIG. 6 is a diagram showing an example in which an FB distribution in a chip displayed on a display device is enlarged and displayed.

This enlargement display function is a function for enlarging and displaying a part when the operator wants to enlarge a part of the screen such as a wafer display or a chip display. When the operator wants to enlarge a part on a screen such as a wafer display or a chip display, he or she specifies a desired part with a mouse, and an enlarged display screen is newly opened as shown in FIG.

To display at a higher magnification,
It can be freely changed by specifying the enlargement ratio button 1901 at the upper part of the screen with the mouse. On the screen, (x, y) coordinates (1902, 19) based on the design information are displayed.
03) is displayed, the position of the FB can be easily confirmed. When the enlargement ratio is changed, the coordinate display also changes accordingly. This enlargement function is possible from any of the wafer display, shot display, chip display, matte display, and overlay display.

Next, the scale function will be described with reference to FIG. FIG. 20 is a diagram showing an example in which the scale displayed on the display device is displayed.

When the operator designates the scale function, a ruler 2001 as shown in FIG. 20 is displayed on the analysis screen. This ruler can change the direction and position freely in the vertical and horizontal directions, and is effective for confirming the FB distribution range, bit size, mat interval, and the like. Further, this ruler can be displayed on any of a wafer display, a shot display, a chip display, a mat display, an overlay display and an enlarged display. The scale of the ruler matches the scale of each display screen, and the scale of the ruler is changed every time the analysis screen is changed.

[V] Next, the superposition function will be described with reference to FIGS. 21 and 22. First, the superposition algorithm will be described with reference to FIG. Figure 2
FIG. 1 is a conceptual diagram showing a superimposing method.

First, the compressed data on the same wafer stored in the database is retrieved for two chips, and is returned to the state before compression, that is, 0, 1 data on the memory. Then, the following work is performed. As shown in FIG. 21, the corresponding cell values of chips A and B are obtained. Next, when the compressed data of another chip is called from the database and converted into 0, 1 data as C, the sum of the previously calculated values of (A + B) and C is calculated. Thereafter, the compressed data is sequentially called from the database and the same processing is performed. If the finally obtained value is END, the value of each cell of this END indicates the number of chips in which FBs are generated at the same cell position among the superposed chips. By this process, the result of stacking chips in the same wafer can be obtained. When the above result is displayed on the screen, the display color is changed according to the value (number of overlaps) (2101) indicated by each cell to clarify the overlap state.

The chip superposition in the same wafer has been described above, but in the case of superposing wafers,
The data of chips at the same position on different wafers may be sequentially called, and the same processing as that described above may be performed. By performing these processes, screens of wafers, shots, chips, etc. as described below are created.

Now, with reference to FIG. 22, an analysis function called in-wafer shot unit superposition will be described. Figure 2
FIG. 2 is a diagram showing an example in which FB distributions are superimposed and displayed for each shot displayed on the output device.

As described above, the exposure apparatus exposes a plurality of chips at one time. The exposure unit was called a shot. Here, a case where two chips are exposed at one time will be described. When a defect or a foreign substance exists on the photomask used for exposure, FB repeatedly appears at the same position in the shot. When the operator specifies the shot-unit superimposing function while looking at the entire image of the wafer, shot 2 within that wafer
Opens a shot overlay window that displays the FB distributions for each 201. In the window, the chip outline and the distribution status of FBs in each chip are displayed.

When the distribution of FBs is shown, the colors and meshes are displayed separately according to the number j of FBs existing at the same location. As a display method, j / i is calculated with respect to the total number of shots i, and the value is divided into, for example, 3 and the color, mesh, or the like is changed for each range (2202, 2203, 2204).

By doing so, it can be understood that FB is repeatedly generated for each shot at a portion where j / i is large. Therefore, by checking the corresponding portion on the mask, a defect or a foreign substance on the photomask is detected. The probability of discoverability increases, and more appropriate results can be obtained.

Next, with reference to FIG. 23, an analysis function called chip unit superposition will be described. FIG. 23 is a diagram showing an example in which distributions of FBs are superimposed and displayed for each chip displayed on the output device.

If there is an error in the design of the circuit pattern or there is a defect such as insufficient margin, the FB is repeated at the same location in the chip.
Occurs. When the operator specifies the chip-by-chip overlay function while looking at the entire wafer image, the FB distribution state is displayed for each chip 2301 in the wafer. And FB
The same display method as the shot unit superimposition is used to show the distribution of. However, the total number of shots i is the total number of chips here. Here, if the value of j / i is large, it is considered that there is a design defect in the relevant part, and by reviewing the design, it is possible to more appropriately find a defect factor such as an error in the circuit pattern design or a defect such as insufficient margin. You can.

Next, referring to FIG. 24, an analysis function called wafer unit superposition will be described. FIG. 24 is a diagram showing an example in which the FB distributions are superimposed and displayed for each wafer displayed on the output device.

For example, if there is a defect in the film forming apparatus and there is an abnormality in the film quality or the film thickness, a deviation 2401 appears in the in-plane distribution of the FB. Such deviation of FB can be realized by superimposing FB distributions on a plurality of wafers. In the present invention, an operator can perform wafer-by-wafer superimposition by designating the product name, lot number, and wafer number of desired wafers (plurality), using the above-mentioned whole wafer display window. For example, if an abnormality in the film quality or film thickness is found by superimposing FBs, the film forming equipment is inspected. If the film thickness or film quality inspection is performed after film formation, check the inspection equipment itself or the management standard By doing so, the cause of the defect can be found more appropriately.

[VI] Next, a method called grouping will be described with reference to FIG. FIG. 25 is a diagram showing a flow showing a grouping procedure.

The data compression method according to the present invention divides the FB group in order to efficiently perform the data compression, but it is a method for recognizing that each divided FB group is the same FB group. As a result, it becomes clear how much FB occurs due to the influence of one foreign matter when performing a match analysis of the tester data and other measurement data, for example, foreign matter data. This process may be performed before creating the compressed data and storing the compressed data in the database, or when actually transferring the data to the matching analysis or observation device.

First, the stored compressed data is sequentially called. Next, G _max = 1 is set as an initial value (step 2501). Then, it is checked whether the value of the flag is F _A = 0 (step 2502). If F _A = 0,
It is checked whether or not there is data B adjacent to the right side of data A (step 2503).

If there is a data B that contacts, the group N of B
The value of G _B is o is 0 whether investigate (step 250
4). If G _B = 0, the group numbers of _A , G _A and G
The value of G _max is substituted for _B (step 2505). next,
It is checked whether or not there is data C that is in contact with the upper side of A (step 2506). If there is, it is checked whether the value of G _C which is the group number of _C is 0 (step 2507).

If G _C = 0, the value of G _max is substituted for G _C (step 2508). Then, the value of G _max is updated by 1 (step 2509). Finally, change the value of F _A from 0 to 1
(Step 2510). (Step 250
In 6), if there is no data C touching the upper side of A, G _max
The value of is updated by 1 (step 2509).

Then, the value of F _A is converted from 0 to 1 (step 2510). In step 2507, G _C ≠
If it is 0, the value of G _C is substituted into G _A and G _B (step 2)
511). Then, the value of F _A is converted from 0 to 1 (step 2510). Also, in step 2504, G _B
If ≠ 0, the value of G _B is substituted for G _A (step 251)
2).

Next, it is checked whether or not there is data C that is in contact with the upper side of A (step 2513). If there is, it is checked whether G _C is 0 (step 2514). If G _C = 0,
The value of G _B is substituted for G _C (step 2515). Then, the value of F _A is converted from 0 to 1 (step 251).
0). If G _C ≠ 0 in (step 2514), G _B ≦ G
Check _C (step 2516).

If this inequality is satisfied, the value of G _B is substituted for G _C (step 2515). Then, set the value of F _A to 0
To 1 (step 10). (Step 251
If G _B > G _C in 6), the G _C value is substituted into G _A and G _B (step 2517). Then, the value of F _A is converted from 0 to 1 (step 2510). (Step 2503)
If there is no data B touching the right side of A, it is checked whether there is data C touching the upper side of A (step 2518).

If there is a contact data C, it is checked whether the value of G _C is 0 (step 2519). If G _C = 0, the value of G _max is substituted for G _A and G _C (step 252).
0). Then, the value of G _max is updated by 1 (step 250
9), the value of F _A is converted from 0 to 1 (step 251)
0). If G _C ≠ 0 in (step 2519), then G _A becomes G
The value of _C is substituted (step 2521).

Then, the value of F _A is converted from 0 to 1 (step 2510). If there is no data C in contact with the upper side of A in (step 2518), the value of G _max is substituted for G _A (step 2522). Then, the value of G _max is updated by 1 (step 2509), and the value of F _A is converted from 0 to 1 (step 2510). In step 2502, F _A
If ≠ 0, the data is continuously read until the flag values of all the data become 1. If all data flags are 1 (step 2523), the operation is stopped.

[VII] Next, referring to FIGS. 26 and 27, the function of estimating the cause of the defect from the shape distribution of the FB will be described. FIG. 26 shows F displayed on the output device.
It is a figure which shows the example of a display of the distribution shape of B (the 1). Figure 2
FIG. 7 is a diagram showing a display example (No. 2) of the distribution shape of FBs displayed on the output device.

The defect cause database contains information based on expert knowledge and past analysis results. When the analyst first designates the failure cause estimation function, designates a desired FB or FB group, and searches the data database, the items considered to be the cause of the FB are output. For example,
As shown in FIG. 26A, when only one memory cell in the chip is FB, when that cell is designated and the database is searched, a message that foreign matter is attached is displayed on the memory cell. Further, the cause of the defect displayed here is not always one item, and in the case of FIG. 27, a plurality of items may be displayed. In FIG. 27, it is shown that foreign matter adheres to the line missing intersection (A) and the peripheral circuits (B) and (C) are short-circuited or disconnected. This defective item can be displayed with a higher priority than the past analysis results. If the cause of the defect, defective process, etc. are clear from this result, the result is fed back to the relevant department.

[VIII] Next, the function of the observation system using an electron microscope (hereinafter abbreviated as “SEM”) and the like will be described with reference to FIG. FIG. 28 is a diagram showing coordinate reference points in the chip.

Representative points are extracted based on the results of analysis of the FB data and butt analysis of the FB data and the foreign substance inspection data / appearance inspection data. Then, the coordinates of the representative point are calculated, and the coordinate data is sent to the data processing device attached to the SEM or the like. At this time, since the coordinate system in the chip differs depending on each inspection device (tester, foreign substance inspection device, visual inspection device, SEM, laser microscope, etc.), an error may occur if simple data transfer or data matching is performed. Will end up.
That is, in the chip, there is a reference pattern 401 for determining the coordinates in the chip as shown in FIG. 4, and where in the pattern is used as a reference point differs depending on each device. Therefore, the coordinates of the coordinate reference point of each device and the relative error between each device are calculated in advance from the design information, and the information is registered in the database. Then, when the data transfer or the matching analysis with other data is performed, the error between the coordinate systems is corrected and the coordinates are calculated.

For example, in FIG. 1, when the analyst performs analysis by the FB analysis system 105 and then transfers the coordinates of a certain memory cell to the SEM which is the observing device 109 for observation,
Data transfer is performed after the following processing is performed. First, FB
Converts data from logical coordinates to real coordinates. Further SEM
Correct the error between and. That is, as shown in FIG. 28, the real coordinates of the FB in the tester are (x, y) (280
1) and the correction value is (a, b) (2802), SE
The FB coordinate (X, Y) (2803) in the M coordinate system is
It is given by the following formula.

[0146]

## EQU1 ## (X, Y) = (x, y) + (a, b)

Therefore, the value of (x + a, y + b) is transferred. When matching with other data, coordinate conversion may be performed in the same manner. The SEM or the like observes the corresponding position on the wafer or chip based on the obtained coordinate data. Then, it is determined by observation whether there is a foreign substance or a scratch on the representative point and its periphery. As described above, it is an advantage that the LSI design information 107 is used as a system configuration requirement that the correction can be performed uniformly for each device.

During observation, since the semiconductor device has a layered structure, it is necessary to peel off some of the upper layers as necessary. Further, if no abnormality such as foreign matter or scratches can be confirmed as a result of the observation, the layer being observed is peeled off and the lower layer is observed. Note that there is a known method called peeling as a means for peeling off, and the present invention can be performed without any inconvenience by using etching. The observed image is stored in an appropriate storage medium, such as a hard disk or an optical disc, via the data processing device. At the time of saving, an identifier that is uniquely determined at least in the storage medium is added to the observation image data. The calculation of the representative point may be performed by the data processing device.

Further, the observation device is not limited to the SEM, and any device can be used as long as it can obtain an appropriate magnification for observation. S
When foreign matter or impurities are found to be mixed in when observed by EM or the like, the components are analyzed. The analysis itself may be carried out in a device such as SEM or in a separate device. When using another device, the coordinate data can be transmitted via a network or recorded in a portable storage medium and handed over. As the analyzer, an energy dispersive X-ray spectroscope (abbreviated as "EDX" in FIG. 1) and a laser mass spectroscope (abbreviated as "laser mass" in FIG. 1) , An infrared absorption spectroscopy spectroscope (in FIG. 1, abbreviated as “infrared spectroscopy”) and the like.

[IX] Next, referring to FIG. 29, by inputting the function of managing the inspection history of the wafer, the function of instructing the next inspection step and the inspection contents, and the lot number and the wafer number, The function of acquiring the past inspection content of the corresponding target will be described. FIG. 29 is a conceptual diagram of a system for managing an inspection history of a wafer by using an IC card and a computer system, and instructing an inspection process and inspection contents.

First, when performing a foreign matter inspection, an appearance inspection, or the like, a storage medium (for example, an IC card with a display function) that can carry an inspection process, an inspection condition, an inspection content, an inspection result, etc. at the time of the inspection. 292). It is convenient in terms of work if the storage medium is carried along with the inspected lot. In this way, the output device 29 of the computer system 295 is displayed by the display on the IC card.
4 makes it possible to easily acquire the inspection history of lots and wafers. Alternatively, by storing this in the inspection history database 297 and inputting the lot number or wafer number from the keyboard 296 of the computer system 295, the past inspection contents of the corresponding target can be known from the output device 294. In addition, the inspection process of the computer system and the inspection content instruction program can be used to determine the content of the inspection performed in the subsequent process, whether or not to perform the inspection itself, etc., by the data stored in this storage medium. By automation, planning for inspection can be omitted and work efficiency can be improved.

For example, only when foreign substances are detected in the film forming process and more foreign substances are detected than a predetermined reference, it is possible to perform an appearance inspection after the photolithography process immediately after that is completed. By operating in this way, it becomes possible to analyze whether or not the foreign matter adhered has an effect on the pattern formation. Further, since it is only necessary to perform the visual inspection only on the lot or the wafer to which the foreign matter is attached in an abnormally large amount, when the inspection speed of the visual inspection is slower than the inspection speed of the foreign matter inspection, it is possible to judge the lot and the process to be subjected to the visual inspection. It will be possible.

[X] Next, the function called butt analysis of FB data and foreign matter inspection data / appearance inspection data will be described.

First, the operator specifies the function of the FB data and the matching analysis of the foreign substance inspection data / appearance inspection data, and analyzes the lot / wafer product name, wafer size,
By inputting conditions such as lot No., wafer No., measurement date, etc. and searching the database, the desired data is called, and by comparing the position coordinates with foreign particles or scratches and the cell position coordinates with FB, It becomes clear how much FB occurs due to the influence of foreign matter and scratches. As a result, the cause of the defect and the process in which the defect occurs can be narrowed down. Further, when performing detailed analysis, desired coordinates may be transferred to the observation device or the analysis device. In this butt analysis, since the coordinate system differs depending on each inspection device as described above, the coordinate systems are unified and then the coordinate comparison is performed.

[0155]

According to the present invention, it is possible to perform a failure analysis method with higher measurement accuracy in the case of performing FB failure analysis in response to higher integration of semiconductor memory. Further, it is possible to smoothly cope with the characteristics caused by the type of each chip, and it is possible to easily correct the deviation of the measurement selected for the characteristics of the observation device and the analysis device used in the system.

Further, according to the data compression method of the present invention, it is possible to cope with the recent high integration of the semiconductor memory, and no matter what pattern the FB occurs in the memory cell, there is no loss of information and the efficiency is high. The data can be compressed, and even a complicated FB distribution pattern can be easily managed. further,
The data compression method according to the present invention can be restored without losing the original tester data.

Further, according to the present invention, regarding the user interface of the system, a failure analysis method for acquiring various inspection results simultaneously or immediately, and visually confirming the size of the memory cell when displayed on the output device. The failure analysis method, test conditions and inspection results can be displayed at the same time.

Therefore, for example, an operator can easily see the FB distribution in each unit of wafer, chip, shot, and mat and an enlarged image of each inside, and detailed analysis in bit unit becomes possible. Therefore, semiconductor manufacturing equipment,
It has become possible to easily study abnormalities in photomasks and designs.

Further, according to the present invention, when the wafer is exposed,
When the photomask has a defect, the cause of the defect can be effectively investigated. According to the present invention, it becomes possible to immediately acquire the inspection history of the inspection target at the time of failure analysis. Further, according to the result of the inspection, the method of the inspection content and the inspection process to be performed in the future can be automatically acquired. Therefore, the cause of defects can be investigated at an early stage, defects that occur intensively can be prevented, and the product yield can be improved.

[Brief description of drawings]

FIG. 1 is a basic conceptual diagram of a failure analysis system according to the present invention.

FIG. 2 is a conceptual diagram showing a detailed configuration of an FB analysis system.

FIG. 3 is a schematic diagram of chips arranged on a wafer.

FIG. 4 is a diagram showing a configuration in a chip.

FIG. 5 is a diagram showing a schematic flow of physical conversion.

FIG. 6 is a diagram showing various patterns of FBs in a chip.

FIG. 7 is a diagram showing a method of dividing an FB group (diagonalization).

FIG. 8 is a diagram showing a way of holding diagonalization data.

FIG. 9 is a diagram showing a method of dividing an FB group (vectorization) and a way of holding data.

FIG. 10 is a diagram showing a flow of a method of selectively using some compression methods for each FB shape in a chip.

FIG. 11 is a diagram showing a flow of a method for selecting a compression method for each chip.

FIG. 12 is a diagram showing a flow of restoration and display of data for one wafer.

FIG. 13 is a diagram showing a detailed flow when data compression is performed for each FB shape in a chip.

FIG. 14 is a diagram showing a configuration of a system screen displayed on a display device.

FIG. 15 is a diagram showing an example of distribution display of FBs on a wafer displayed on a display device.

FIG. 16 is a diagram showing an example of distribution display of FBs in a chip displayed on a display device.

FIG. 17 is a diagram showing an example of distribution display of FBs in a mat displayed on a display device.

FIG. 18 is a diagram showing an example of FB distribution display within a shot displayed on a display device.

FIG. 19 is a diagram showing an example in which an FB distribution in a chip displayed on a display device is enlarged and displayed.

FIG. 20 is a diagram showing an example in which a scale displayed on a display device is displayed.

FIG. 21 is a conceptual diagram showing a superposition method.

FIG. 22 is a diagram showing an example in which FB distributions are superimposed and displayed for each shot displayed on the display device.

FIG. 23 is a diagram showing an example in which FB distributions are superimposed and displayed for each chip displayed on a display device.

FIG. 24 is a diagram showing an example in which FB distributions are superimposed and displayed for each wafer displayed on the display device.

FIG. 25 is a diagram showing a flow of a grouping procedure.

FIG. 26 is a diagram showing a display example (No. 1) of the distribution shape of FBs displayed on the display device.

FIG. 27 is a diagram showing a display example (No. 2) of the distribution shape of FBs displayed on the display device.

FIG. 28 is a diagram showing coordinate reference points in a chip.

FIG. 29 is a conceptual diagram of a system that manages an inspection history of a wafer using an IC card and a computer system to instruct an inspection process and inspection contents.

[Explanation of symbols]

101-110 ... Configuration block of the present invention 201-212 ... Main configuration block of FB analysis system 401-408 ... Main configuration of chip 501-505 ... Physical conversion processing step 1001-1011 ... Compress for each distribution shape of FB Data compression processing steps 1101 to 1109 in the method of selecting a method ... Data compression processing steps 1201 to 1203 in the method of selecting a compression method for each chip ... Data restoration display processing steps 1301 to 1325 ... Data compression method ( Details) processing steps 1401 to 2001 ... Contents displayed on the display device 2101 ... Number of overlapping chips 2201 to 2401 ... Contents displayed on the display device 2501 to 2523 ... Grouping processing steps 2801 to 2803 ... Coordinate reference points in the chip

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Nakazato 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Production Engineering Research Laboratory, Hitachi, Ltd. Company Hitachi Ltd., Takasaki Plant (72) Inventor Yoshiyuki Miyamoto 111 Nishiyote-cho, Takasaki City, Gunma Hitachi Ltd. Takasaki Plant (72) Inventor Masachika Narushima 111, Nishiyote-cho, Gunma Prefecture Hitachi Ltd. Takasaki Factory (72) Inventor Isao Miyazaki 111 No. Nishiyokote-cho, Takasaki City, Gunma Hitachi Ltd.Takasaki Factory (72) Inventor Yoshiharu 111 No. Nishiyote-cho, Takasaki City, Gunma Hitachi Ltd. Takasaki Factory ( 72) Inventor Masayuki Sato 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Semiconductor company Hitachi, Ltd. Semiconductor design In the originating center (72) Inventor Takayuki Oshima 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside the semiconductor design and development center, Hitachi, Ltd. (72) Inventor Taizo Hashimoto 111 Nishiyote-cho, Takasaki-shi, Gunma Stock Company Hitachi, Ltd. Takasaki factory

Claims (11)

[Claims] 1. A semiconductor defect analysis system, comprising means for collecting semiconductor defect information, means for inspecting semiconductor defect information, and means for performing data analysis of the defect information. A semiconductor failure analysis system having semiconductor design information used for data analysis. 2. A semiconductor defect analysis system comprising: means for collecting semiconductor defect information; means for inspecting semiconductor defect information; means for performing data analysis of the defect information; A semiconductor failure analysis system comprising: means for displaying and design information of the semiconductor used for displaying the failure information. 3. A semiconductor defect analysis system, comprising means for collecting semiconductor defect information, a device for inspecting semiconductor defect information, and means for performing data analysis of the defect information. A semiconductor failure analysis system having information on the inspection device used for data analysis. 4. A method of compressing analysis data used in a semiconductor failure analysis system, including means for collecting semiconductor failure information, means for inspecting semiconductor failure information, and means for storing the failure information. A method for compressing analysis data used in a semiconductor failure analysis system, characterized in that it has a means for compressing the defect information, and at the time of compression, the storage mode is made different depending on the mode in which the defect information occurs. . 5. A semiconductor failure analysis system, means for collecting semiconductor failure information, means for inspecting semiconductor failure information, means for data analysis of the failure information, and the failure information or A semiconductor failure analysis system, comprising: a device for displaying analysis data or inspection conditions, wherein the display device simultaneously displays defect information, analysis data, or inspection conditions in a plurality of windows or individual windows. 6. A semiconductor defect analysis system, means for collecting semiconductor defect information, means for inspecting semiconductor defect information, means for performing data analysis of the defect information, and the defect information or A semiconductor failure analysis system characterized by having a device for displaying analysis data or inspection conditions, and simultaneously displaying defect information or analysis data and inspection conditions on the same screen of the display device. . 7. A semiconductor defect analysis system comprising: means for collecting semiconductor defect information; means for inspecting semiconductor defect information; means for performing data analysis of the defect information; A defect analysis system for a semiconductor, comprising: a device for displaying analysis data, wherein the display device simultaneously displays an object to be inspected and a scale of the object to be inspected. 8. A failure analysis method of a semiconductor failure analysis system, comprising means for collecting semiconductor failure information, means for inspecting semiconductor failure information, and means for performing data analysis of the failure information. A defect analysis method for a semiconductor defect analysis system, which comprises superimposing the inspection results for each exposure unit. 9. A failure analysis method for a semiconductor failure analysis system, comprising means for collecting semiconductor failure information, means for inspecting semiconductor failure information, and means for performing data analysis of the failure information. A defect analysis method for a semiconductor defect analysis system, comprising: a device for displaying defect information or analysis data; and superimposing inspection results for each exposure unit and displaying the result on the display device. 10. A semiconductor defect analysis system, means for collecting semiconductor defect information, means for inspecting semiconductor defect information, means for specifying an object to be inspected, and inspection history of the object to be inspected. A semiconductor defect characterized by having a means for managing the inspection target, an inspection history database of the inspection target, and a device for displaying the inspection history, and displaying the inspection history of the inspection target on the display device. Analysis system. 11. A semiconductor defect analysis system, means for collecting semiconductor defect information, means for inspecting semiconductor defect information, means for specifying an object to be inspected, and inspection history of the object to be inspected. Management means, an inspection history database of the inspected object, a means for instructing the inspection content or the inspection process by the inspection history of the inspected object, and a device for displaying the inspection content or the instruction of the inspection process. Then, the semiconductor failure analysis system, wherein the display device displays the inspection content of the inspection target or the instruction of the inspection process.