JPH06275728A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To prevent a metal for wiring from diffusing into an element region of a semiconductor device to obtain a semiconductor device without deterioration of characteristics. At the same time, the process is simplified and the wiring metal is arranged right above the element region to eliminate unnecessary wiring. In a method of manufacturing a semiconductor device having a wiring part connected to the semiconductor region through an opening formed in an insulating film on the semiconductor region, the semiconductor region 1 of the opening is provided.
09, a step of depositing a polycrystalline semiconductor layer 111 on the polycrystalline semiconductor layer 111, a step of implanting an n-type impurity with a large range into the polycrystalline semiconductor layer 111, and an n-type semiconductor with a small range into the polycrystalline semiconductor layer 111. Ion implantation of impurities, heat treatment after ion implantation of the impurities, and deposition of a metal containing a low melting point metal or a metal silicide on the polycrystalline semiconductor layer after the heat treatment. A method for manufacturing a characteristic semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a connection portion between a semiconductor element region and a wiring connected to the semiconductor element region in the semiconductor device.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have been highly integrated, the area of each part in a chip has been reduced. However, since the wiring part occupies a large proportion of the chip area, the area saving thereof is achieved. Ization is an important issue.

Of these, as for the so-called contact portion of the lead-out portion of the semiconductor element to the wiring, conventionally, an ohmic contact material made of a polycrystalline semiconductor material such as polysilicon is laid directly on the element and then removed from directly above the element. Although a metal or metal silicide electrode containing a low melting point metal such as Al is connected to a polycrystalline semiconductor material at a certain position, a device to connect the metal or metal silicide directly on the element at the same time is being developed. There is.

On the other hand, polycrystalline semiconductor materials are not desirable for use as lead-out wiring because the movement of carriers serving as current carriers does not follow when the operating frequency of the element becomes high, and it is therefore not desirable to use them as metal wiring or metal from the viewpoint of high-speed operation. The structure is such that the silicide electrode is contacted directly above the element.

[0005]

However, the metal used as the low resistance wiring material or the low melting point metal in the metal silicide has a large diffusion into the polycrystalline semiconductor material, and in the above-mentioned conventional example, the metal or the metal directly above the element. When the silicide contact is made, diffusion of the low melting point metal occurs even in the element portion, which causes deterioration of element characteristics.

Therefore, in order to suppress diffusion of the low melting point metal, a barrier metal may be arranged between the metal or metal silicide and the polycrystalline semiconductor material. With this configuration, diffusion of low melting point metal is surely suppressed,
Although the device characteristics are not deteriorated, there is a drawback that the process is complicated and the cost is increased because the process of depositing the barrier metal and the patterning thereof are included.

[Object of the Invention] An object of the present invention is to prevent the diffusion of the metal for wiring into the element region of the semiconductor device to obtain a semiconductor device without deterioration of characteristics, and at the same time, to simplify the process. By arranging the wiring metal immediately above the element region, it is possible to eliminate unnecessary wiring.

[0008]

As a means for solving the above-mentioned problems, the present invention has a wiring portion connected to the semiconductor region through an opening formed in an insulating film on the semiconductor region. In a method of manufacturing a semiconductor device, a step of depositing a polycrystalline semiconductor layer on a semiconductor region of the opening, a step of ion-implanting a large range n-type impurity into the polycrystalline semiconductor layer, and the polycrystalline semiconductor A step of ion-implanting an n-type impurity having a small range into the layer; a step of heat-treating after ion-implanting the impurity; and, after the heat-treatment, a metal containing a low melting point metal or a metal silicide is formed on the polycrystalline semiconductor layer. The present invention provides a method for manufacturing a semiconductor device, which comprises a step of depositing.

Further, the total concentration of the n-type impurities contained in the polycrystalline semiconductor layer is made larger than 5E20 atom / cm ³ at a depth of 1000 A from the surface of the polycrystalline semiconductor layer by the ion implantation step of the impurities. Is characterized by.

[0010]

According to the present invention, a step of ion-implanting a large-range n-type impurity into a polycrystalline semiconductor layer such as polycrystalline silicon, and a step of ion-implanting a small-range n-type impurity, By carrying out, it is possible to particularly increase the impurity concentration near the surface of the polycrystalline semiconductor layer.

Therefore, by heat-treating a polycrystalline semiconductor layer such as polycrystalline silicon having such an impurity concentration distribution, a crystal having a large crystal grain size can be formed especially near the surface.

In general, diffusion of a low melting point metal in polycrystalline silicon is mostly carried out through crystal grain boundaries. Therefore, when the crystal grain size becomes large, there are few paths through which the metal diffuses, and the amount of diffusion can be kept small.

Therefore, in the present invention, the grain size of the polycrystalline silicon is made larger than in the conventional case, so that the diffusion of the wiring metal formed in the upper layer can be suppressed.

In the case of silicon, in the case of n-type, there is a phenomenon that crystallization by heat treatment is promoted at an impurity concentration of 5E20 cm ^-3 and a polycrystalline silicon having a large grain size is obtained (see "1988. Materials Re
search Society symposium
Proceedings p143-148 ").

Therefore, in the present invention, the total concentration of the n-type impurities contained in the polycrystalline semiconductor layer is 5E20 atom / cm ³ at a depth of 1000 A from the surface of the polycrystalline semiconductor layer by the impurity ion implantation step. By making it larger, it is possible to surely increase the particle size.

[0016] Incidentally, this phenomenon is to begin to saturate at a concentration of at least 1E21 cm ^-3, to more reliably realize the present invention it is desirable to add the 1E21 cm ^-3 or more impurities.

The operation of the present invention will be described below with reference to the drawings.

FIG. 5 is a diagram schematically showing a vertical structure of a contact portion of a semiconductor device. In this example, AlSi is used as one of the metal or metal silicide electrodes 205, and polycrystalline silicon (polysilicon) is used as the polycrystalline semiconductor layer 203.

FIG. 6 shows that, in such a contact portion, Al as a wiring metal is replaced by polysilicon 2 underneath.
03 is a diagram showing a result of measurement of the diffusion in the semiconductor region 201 and the semiconductor region 201.

FIG. 6A shows a change in Al concentration from the surface of the polycrystalline silicon 203 in the contact portion manufactured by the conventional manufacturing method to the semiconductor region 201.
Al maintains a concentration of 1E18 cm ⁻³ or more in the polycrystalline silicon 203, and the polycrystalline silicon 203 and the semiconductor region 201
Is increasing at the interface. Also in the semiconductor region 201
It can be seen that l is widely diffused.

On the other hand, FIG. 6 (b) is a diagram showing the Al concentration distribution of the contact portion manufactured by the manufacturing method of the present invention. As shown in FIG. It is blocked, and the concentration in the polycrystalline silicon 203 decreases toward the semiconductor region 201. Further, in the semiconductor region 201, the Al concentration is suppressed to 1E17 cm ⁻³ or less.

[Embodiment] As the low melting point metal contained in the metal or metal silicide used in the present invention,
In general, metals belonging to 1B to 3B groups and 2A groups, and representative ones are Al, Mg, Cu, Ag, Au and Z.
n and Cd are examples.

Regarding implantation of n-type impurities into polycrystalline silicon or polycrystalline silicon germanium, high-energy P is used as an implantation impurity with a large range, low-energy P is used as an implantation impurity with a small range, and As,
Examples are Sb and Bi.

[0024]

[Embodiment 1] FIGS. 1 to 4 show the structure and manufacturing process of an embodiment according to the present invention.

First, while masking a desired shape on a P-type substrate, As ⁺ ions are implanted by a normal ion implantation method under the conditions of a dose amount of 1E15 cm ^-2 and an acceleration voltage of 60 keV, and thereafter, in an N ₂ atmosphere at 1000 ° C. By annealing under the conditions, As ⁺ ions were diffused to form the N-type blocking layer 101.

Subsequently, while masking B ⁺ ions into a desired shape, implantation is performed under the conditions of a dose amount of 2E13 cm ^-2 and an accelerating voltage of 60 keV, and then 1 in an N ₂ atmosphere.
Annealing was performed at 000 ° C. to diffuse B ⁺ ions and form a P-type blocking layer 102.

Epitaxial growth was carried out on this substrate to form an epitaxial layer 103 having a thickness of 5 μm.

Thereafter, while masking the desired shape, B ⁺ ions are dosed at a dose of 6 by a normal ion implantation method.
Implantation was carried out at E12 cm ⁻² and an acceleration voltage of 100 keV, and then B ⁺ ions were diffused by annealing in an N ₂ atmosphere at 1000 ° C. to form a P well 104.

Then, while masking to a desired shape, P ⁺ ions are implanted by an ordinary ion implantation method under the conditions of a dose amount of 7E15 cm ^-2 and an acceleration voltage of 70 keV, and then in an N ₂ atmosphere at 1000 ° C. By annealing, the contact region 105 of the N-type blocking layer 101 was formed.

Next, a silicon nitride film (106) of 1500 A was deposited by a normal low pressure CVD method and patterned into a desired shape.

Then, O ₂ = 4 l / min, H ₂ = 2
1000 in an atmosphere of 1 / min, N ₂ = 5 1 / min
Field oxide film 1 by oxidation at 5 ℃ for 5 hours
After forming 07, the silicon nitride film 106 was removed.

Then, while masking to a desired shape, a dose amount of 6E12 is obtained by an ordinary ion implantation method.
cm ⁻² , implanting B ⁺ ions at an acceleration voltage of 80 keV,
Then, by annealing at 1000 ° C. in an N ₂ atmosphere, B ⁺ ions are diffused to form a base region 108.

Further, while masking the desired shape, As ⁺ ions are implanted at a dose amount of 1E15 cm ^-2 and an acceleration voltage of 40 keV, and subsequently, the diffusion of As ⁺ ions is performed by annealing at 1000 ° C. in an N ₂ atmosphere. Then, the emitter region 109 is formed.

Then, Si is formed by a normal atmospheric pressure CVD method.
3000 A of O ₂ 110 was deposited to form an interlayer insulating film, and this was etched into a desired shape by a normal photolithography process to form an opening.

Subsequently, a polysilicon layer 111 of 4400 A was deposited by a normal low pressure CVD method.

Next, as the most characteristic step of the present invention,
As a step of implanting impurities into the polysilicon layer 111 with a large range, a dose amount of 7.5E15 cm ^-2 and an acceleration voltage of 8
P ⁺ ions are implanted at ⁰ keV, and as the impurity implantation step with a smaller range, As ⁺ ions are implanted at a dose amount of 5E15 cm ⁻² and an acceleration voltage of 120 keV.

This ion implantation condition is that, when the dose amount of P ⁺ ions is set to about 7.5E15 cm ⁻² and the resistance of the polysilicon layer is sufficiently lowered, As ⁺ ions are as shown in FIG. By injecting in the shaded area, the desired purpose is achieved.

After that, by annealing in a N ₂ atmosphere at 950 ° C., P ⁺ ions and As ⁺ ions were diffused to make the polysilicon layer N-type.

Subsequently, the polysilicon layer 111 was etched into a desired shape by a normal photolithography process.

Thereafter, Si is formed by a normal atmospheric pressure CVD method.
An O ₂ film was deposited at 6000 A to form an inter-layer insulating film 112, which was then etched into a desired shape by a normal photolithography process to form an opening.

After that, AlSi1 is formed by a normal sputtering method.
13 was deposited at 10000 A, followed by etching into a desired shape by a normal photolithography process, and further heat treatment at 450 ° C. for 30 minutes in an N ₂ atmosphere to form AlSi1.
13 and polysilicon 111 were alloyed. Thus, the wiring electrode 113 was formed, and the semiconductor device according to the present invention was completed.

[Effects of Embodiment 1] The semiconductor device (semiconductor device A) formed as described above and A of the polysilicon portion.
Semiconductor device created without s implantation (semiconductor device B)
When semiconductor device B is compared, Vbe-Ic, I
Although the leakage current in the low voltage region was very large when the b characteristic was observed (FIG. 8B), it was almost suppressed in the semiconductor device A, and Ic and Ib were V in the region of Vbe = 0 to 0.5V.
The relationship that depends exponentially on be was clearly seen (Fig. 8 (a)).

[Embodiment 2] FIG. 9 shows the structure of a second embodiment according to the present invention. Regarding the numbers of the respective parts, the same parts as those in the first embodiment are given the same numbers. Hereinafter, using FIG. 1 to FIG.
The manufacturing process of this example will be described.

First, while masking a P-type substrate into a desired shape, As ⁺ ions are implanted by a usual ion implantation method under the conditions of a dose amount of 1E15 cm ^-2 and an acceleration voltage of 60 keV, and thereafter, in an N ₂ atmosphere at 1000 ° C. By annealing under the conditions, As ⁺ ions were diffused to form the N-type blocking layer 101.

Subsequently, while masking B ⁺ ions into a desired shape, implantation is performed under the conditions of a dose amount of 2E13 cm ^-2 and an accelerating voltage of 60 keV, and then 1 in an N ₂ atmosphere.
Annealing was performed at 000 ° C. to diffuse B ⁺ ions and form a P-type blocking layer 102.

Epitaxial growth was carried out on this substrate to form an epitaxial layer 103 having a thickness of 5 μm.

After that, while masking the desired shape, B ⁺ ions are dosed at a dose of 6 by an ordinary ion implantation method.
Implantation was carried out at E12 cm ⁻² and an acceleration voltage of 100 keV, and then B ⁺ ions were diffused by annealing in an N ₂ atmosphere at 1000 ° C. to form a P well 104.

Then, while masking to a desired shape, P ⁺ ions are implanted by a normal ion implantation method under the conditions of a dose amount of 7E15 cm ^-2 and an acceleration voltage of 70 keV, and thereafter, in an N ₂ atmosphere at 1000 ° C. By annealing, the contact region 105 of the N-type blocking layer 101 was formed.

Then, a silicon nitride film (106) having a thickness of 1500 A was deposited by an ordinary low pressure CVD method and patterned into a desired shape.

Then, O ₂ = 4 l / min, H ₂ = 2
1000 in an atmosphere of 1 / min, N ₂ = 5 1 / min
Field oxide film 1 by oxidation at 5 ℃ for 5 hours
After forming 07, the silicon nitride film 106 was removed.

Then, while masking to a desired shape, a dose amount of 6E12 is obtained by an ordinary ion implantation method.
cm ⁻² , implanting B ⁺ ions at an acceleration voltage of 80 keV,
Then, by annealing at 1000 ° C. in an N ₂ atmosphere, B ⁺ ions are diffused to form a base region 108.

Further, while masking the desired shape, As ⁺ ions are implanted at a dose amount of 1E15 cm ^-2 and an acceleration voltage of 40 keV, and then the As ⁺ ions are diffused by annealing at 1000 ° C. in a N ₂ atmosphere. Then, the emitter region 109 is formed.

Then, Si is formed by a normal atmospheric pressure CVD method.
3000 A of O ₂ 110 was deposited to form an interlayer insulating film, and this was etched into a desired shape by a normal photolithography process to form an opening.

Subsequently, a polysilicon layer 111 of 4400 A was deposited by a normal low pressure CVD method.

Next, as the most characteristic step of the present invention,
As a step of implanting impurities into the polysilicon layer 111 with a large range, a dose amount of 7.5E15 cm ^-2 and an acceleration voltage of 8
P ⁺ ions are implanted at ⁰ keV, and Sb ⁺ ions are implanted at a dose amount of 5E15 cm ^-2 and an acceleration voltage of 180 keV as an impurity implantation step with a smaller range.

This ion implantation condition is that when the dose amount of P ⁺ ions is set to about 7.5E15 cm ⁻² and the resistance of the polysilicon layer is sufficiently low, the Sb ⁺ ions are as shown in FIG. By injecting in the shaded area, the desired purpose is achieved.

After that, by annealing in a N ₂ atmosphere at 950 ° C., P ⁺ ions and Sb ⁺ ions were diffused to make the polysilicon layer N-type.

Subsequently, the polysilicon layer 111 was etched into a desired shape by a normal photolithography process.

Thereafter, Si is formed by a normal atmospheric pressure CVD method.
An O ₂ film was deposited at 6000 A to form an inter-layer insulating film 112, which was then etched into a desired shape by a normal photolithography process to form an opening.

After that, AlSi is formed by an ordinary sputtering method.
AlSi is deposited by depositing 113A of 10000A, followed by etching into a desired shape by a normal photolithography process, and further performing heat treatment at 450 ° C. for 30 minutes in an N ₂ atmosphere.
113 and polysilicon 111 were alloyed. Thus, the wiring electrode 113 was formed, and the semiconductor device according to the present invention was completed.

[Effect of Embodiment 2] The semiconductor device (semiconductor device A) formed as described above and the S of the polysilicon portion are formed.
Semiconductor device created without b implantation (semiconductor device B)
When semiconductor device B is compared, Vbe-Ic, I
The leakage current in the low voltage region was very large when the b characteristics were observed, but it was almost suppressed in the semiconductor device A, and Vbe
In the region of = 0 to 0.5 V, the relationship that Ic and Ib depend exponentially on Vbe was clearly seen. [Embodiment 3] FIGS. 11 and 12 show the structure of a third embodiment of the present invention. FIG. 11 is a plan view and FIG.
(A) and (b) are AA 'and BB' of FIG. 11, respectively.
It is a typical sectional view of a part.

In this embodiment, a CCD is formed on a P-type silicon substrate by a normal CCD process.

In FIG. 11, only the photodiode portion 31 and the vertical CCD (hereinafter referred to as VCCD) portion 32 are shown.

In FIG. 12, the N-type region 302 forms a PN junction with the P-type substrate 301 and becomes a photodiode for detecting an optical signal. Further, a VCCD is formed by the N-type region 303 and the polysilicon gate electrodes 305 and 306, and the N-type region 303 serves as a potential well for storing and transferring charges.

Here, the polysilicon gates 305 and 306 are provided.
The method of the present invention is used for the doping. That is, the polysilicon layer 305 is formed by the normal LP-CVD method.
After 00A deposited dose 7.5E15cm ^-2 by conventional ion implantation method, implanted P ⁺ ions at an acceleration voltage 80 keV, further dose 5E15 cm ^-2, implanted As ⁺ ions at an acceleration voltage 120 keV.

Under these ion implantation conditions, when implanting P ⁺ ions at a dose of about 7.5E15 cm ^-2 , As ⁺ ions are implanted in the region shown in FIG. 7 as in the case of the first embodiment. By doing so, the desired purpose is achieved.

Thereafter, by annealing at 950 ° C. in an N ₂ atmosphere, P ⁺ ions and As ⁺ ions are diffused to make the polysilicon layer N-type.

After that, the polysilicon layer 305 was etched into a desired shape by a normal photolithography process, and then 2000 A of SiO ₂ film was deposited by a normal atmospheric pressure CVD method to dispose an interlayer insulating film.

After that, the polysilicon layer 306 was also deposited under the same conditions as the polysilicon layer 305, ion-implanted, annealed under the same conditions, and then etched into a desired shape by a normal photolithography process to form an electrode shape. Then, after depositing 6000 A of SiO ₂ by a normal atmospheric pressure CVD method,
The SiO ₂ film was selectively opened by a normal photolithography process to form a contact region with Al.

After that, AlSi of 10000 A is deposited by a normal sputtering method, followed by etching in a desired shape by a normal photolithography process, and further, in an N ₂ atmosphere at 45 °.
AlSi and polysilicon were alloyed by heat treatment at 0 ° C. for 30 minutes. Thereby, the wiring electrode 307
Then, the semiconductor device according to the present invention was completed.

[Effects of Embodiment 3] The semiconductor device formed as described above has a very short length in which polysilicon is used as a wiring and most of the portion is connected by an Al wiring, so that a very high speed operation can be achieved. This is possible, and since there is no diffusion of Al into the lower portion of the polysilicon gate, there is no variation in charge transfer characteristics. Further, since the contact between polysilicon and Al is formed directly above the VCCD without interposing an Al diffusion preventing layer or the like, the manufacturing process is simplified.

[0072]

As described above, according to the present invention,
N has a large range in a polycrystalline semiconductor layer such as polycrystalline silicon.
By performing a step of ion-implanting a p-type impurity and a step of ion-implanting an n-type impurity having a small range, the impurity concentration in the vicinity of the surface of the polycrystalline semiconductor layer is particularly increased, and then a heat treatment is performed. A crystal having a large crystal grain size can be formed especially near the surface.

As described above, in the present invention, the grain size of the polycrystalline silicon is made larger than before, so that the diffusion path of the wiring metal formed in the upper layer is reduced and the diffusion of the wiring metal to the semiconductor element region is prevented. Therefore, it is possible to prevent deterioration of the element characteristics.

Further, since the step of forming the barrier metal as in the prior art is eliminated, the steps can be simplified and the cost can be reduced.

Further, unlike the conventional case, there is no need to dispose the contact portion at a position far away from the element region due to fear of metal diffusion, and since the contact portion can be disposed immediately above the element, it is necessary to draw extra wiring. Is eliminated, high-speed operation is possible and stable characteristics are obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure and a manufacturing process of a first embodiment according to the present invention.

FIG. 2 is a diagram showing a structure and a manufacturing process of a first embodiment according to the present invention.

FIG. 3 is a diagram showing a structure and a manufacturing process of a first embodiment according to the present invention.

FIG. 4 is a diagram showing a structure and a manufacturing process of a first embodiment according to the present invention.

FIG. 5 is a schematic view showing a polysilicon / Al contact portion to which the present invention is applied.

6A and 6B are diagrams showing how polysilicon in a contact portion and Al in a semiconductor region are diffused. FIG. 6A shows a conventional example and FIG. 6B shows the present invention.

FIG. 7 is a diagram showing ion implantation conditions set to achieve a predetermined impurity concentration when implementing the present invention.

FIG. 8 is a diagram showing the effect of the present invention, showing Vbe-Ic, Ib characteristics of a bipolar transistor formed by applying the present invention.

FIG. 9 is a schematic diagram showing the structure of a semiconductor device according to a second embodiment of the invention.

FIG. 10 is a diagram showing ion implantation conditions set to achieve a predetermined impurity concentration when carrying out the present invention.

FIG. 11 is a top view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a schematic sectional view showing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 101 N-type blocking region 102 P-type blocking region 103 Epitaxial growth layer 104 P-well 105 Collector contact region 107 Field oxide film 108 Base region 109 Emitter region 110, 112 Interlayer insulating film 111 Polysilicon electrode 113 Al electrode 31 Photodiode 32 Vertical CCD 301 P Type Silicon substrate 302 PN junction photodiode N type region 303 Vertical CCD potential well 304 Insulating film (gate insulating film, interlayer insulating film) 305, 306 Polysilicon gate 307 Al electrode

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a wiring portion connected to the semiconductor region through an opening formed in an insulating film on the semiconductor region, comprising: a polycrystalline semiconductor layer on the semiconductor region of the opening. A step of ion-implanting a large range n-type impurity into the polycrystalline semiconductor layer, a step of ion-implanting a small range n-type impurity into the polycrystalline semiconductor layer, And a step of depositing a metal containing a low melting point metal or a metal silicide on the polycrystalline semiconductor layer after the heat treatment, the method of manufacturing a semiconductor device. 2. The total concentration of n-type impurities contained in the polycrystalline semiconductor layer is 5E2 at a depth of 1000 A from the surface of the polycrystalline semiconductor layer by the ion implantation step of impurities.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is greater than 0 atom / cm ³ . 3. The method for manufacturing a semiconductor device according to claim 1, wherein the polycrystalline semiconductor is polycrystalline silicon or polycrystalline silicon germanium.