JPH06295927A - Manufacture of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent the generation of loose joint of the first layer transfer electrode of a transfer electrode having a multilayer structure. CONSTITUTION:A silicon oxide film 13, formed by a thermal oxidation method, and a polycrystalline silicon film 14 and a silicon oxide film 15, formed by a CVD method, are formed in order on a silicon substrate 10 and these films 14 and 15 are patterned using a resist mask to form transfer electrodes 17. After the mask is removed, the film 13 is etched to expose the substrate 10. The surface of the exposed substrate 10 is thermally oxidized to form a thin silicon oxide film 18 and a silicon oxide film 19 and a polycrystalline silicon film 20 are formed in order on this film 18 by a CVD method. The film 20 is patterned to form transfer electrodes 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a solid-state image pickup device having a multi-layered transfer electrode.

[0002]

2. Description of the Related Art In a frame transfer type CCD solid-state image pickup device, an image pickup portion which receives light from an object accumulates information charges generated in response to the applied light, and at the same time, accumulates information charges accumulated for a predetermined period. Is transferred to the storage unit and output. Therefore, transfer electrodes for transferring and driving information charges are also provided in the light receiving region.
The side edges of the transfer electrodes are overlapped with each other so that the continuity of the potential action of the transfer path is ensured and the reduction of the charge transfer efficiency is prevented.

FIG. 5 shows a frame transfer type CCD.
FIG. 6 is a plan view showing an image pickup section of the solid-state image pickup element, and FIG.
It is a X-ray sectional view. This drawing shows a vertical overflow drain structure in which excessive charges are absorbed on the substrate side. A P-type diffusion layer 2 serving as an element region is formed on one surface of the N-type silicon substrate 1. In the diffusion layer 2, a plurality of isolation layers including a high-concentration P-type region and a thick oxide film (LOCOS) are formed. Regions 3 are formed parallel to each other. In the channel region 4 sandwiched between these isolation regions 3, a buried channel layer 5 is provided by diffusing N-type impurities in the surface portion. The transfer electrodes 7 of the first layer are arranged in parallel with each other so as to intersect the channel region 4 with the oxide film 6 interposed therebetween, and the transfer electrodes 8 of the second layer are separated from each other by a gap between the transfer electrodes 7 of the first layer. Arranged to cover. A fixed potential is applied to each of the transfer electrodes 7 and 8 during the accumulation period, so that a light receiving pixel with four transfer electrodes 7 and 8 as one unit is set. Then, after a lapse of a predetermined light receiving period, four-phase clock pulses are applied to the respective transfer electrodes 7 and 8, and the information charges accumulated in the respective light receiving pixels are transferred to the accumulating portion side along the channel region 4. To be done. When excessive information charges are generated in the channel region 4, the excess charges exceed the potential barrier between the silicon substrate 1 and the diffusion layer 2 and are absorbed by the silicon substrate 1 side. .

[0004]

In the light receiving portion of the CCD solid-state image pickup device as described above, since information charges are obtained by the photoelectric effect of the light incident on the channel region 4, the film thickness of the transfer electrodes 7 and 8 is increased. Measures have been considered to reduce the thickness and increase the incidence efficiency of light. In particular, if each part is miniaturized in response to higher resolution, the area of the light receiving pixel becomes smaller, and the improvement of the light receiving sensitivity due to the improvement of the incident efficiency becomes a problem.

However, when the film thickness of the transfer electrodes 7 and 8 becomes thin, the first layer is formed when the interlayer insulating film for insulating between the first layer transfer electrode 7 and the second layer transfer electrode 8 is formed. There is a problem that the side portion of the transfer electrode 7 is easily lifted. That is, since the interlayer insulating film is formed by thermal oxidation of the surface of the transfer electrode 7 made of polycrystalline silicon, an oxide film between the silicon substrate 1 and the transfer electrode 7 is formed during the thermal oxidation process. 7 is grown from the side surface side, and the transfer electrode 7
When the film thickness is thin, the side portion of the transfer electrode 7 floats. When the side portion of the transfer electrode 7 is lifted up, etching may remain in the lifted portion in a later etching step, which may cause current leakage. In addition, the effective gate length of the transfer electrode 7 becomes short, and desired characteristics cannot be obtained, and projections are formed on the transfer electrodes 7 and 8 at the raised portion, and the electric field is concentrated on the projection portion to cause transfer failure. Become.

Therefore, an object of the present invention is to improve the incidence efficiency of light to the image pickup section while preventing the deterioration of reliability and characteristics.

[0007]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it is provided on a semiconductor substrate provided with a channel region serving as a charge transfer path. In the method for manufacturing a solid-state imaging device, in which a plurality of transfer electrodes intersecting the channel region are arranged in multiple layers, a first conductive film and a first insulating film are sequentially formed on the semiconductor substrate via a gate insulating film. And the first step
A resist mask having a shape extending in a direction intersecting with the channel region of the semiconductor substrate is formed on the insulating film, and the first conductive film and the first insulating film except the region covered with the resist mask. A step of forming a first transfer electrode by removing the film, and after removing the resist mask,
A step of removing the gate insulating film exposed in the region where the first conductive film and the first insulating film are removed; and a second insulating film on the semiconductor substrate, covering the first transfer electrode. And a step of sequentially forming the second conductive film, and a step of forming the second transfer electrode by removing the second conductive film except at least a gap portion of the first transfer electrode,
To prepare.

[0008]

According to the present invention, the oxide film between the first transfer electrode and the semiconductor substrate is formed by thinly oxidizing the surface of the first transfer electrode and then forming the second insulating film by the CVD method or the like. Growth is suppressed, and lifting of the side portion of the first transfer electrode is eliminated.

[0009]

1 to 4 are cross-sectional views for each step showing a method of manufacturing a solid-state image pickup device according to the present invention. Note that these figures show the same parts as in FIG. First, as shown in FIG. 1, P-type impurities such as boron ions are implanted into one surface of an N-type silicon substrate 10 to form a diffusion layer 11, and a high concentration of P as a separation region is formed in the diffusion layer 11. A plurality of mold regions (not shown) are formed in parallel. A buried channel layer 12 is formed by implanting N-type impurities such as phosphorus ions into the channel region sandwiched between these isolation regions. The above implantation process is performed using a resist mask having a desired shape obtained by a well-known photolithography technique. Then, the silicon oxide film 13 serving as a gate insulating film is formed on the silicon substrate 10 on which the isolation region and the channel region are formed.
To a thickness of 100 nm by thermal oxidation. Further, a polycrystalline silicon film 14 serving as a transfer electrode is formed in a thickness of 400 nm and a silicon oxide film 15 serving as an interlayer insulating film is formed in a thickness of 200 nm in this order by the CVD method.

Next, as shown in FIG. 2, a resist mask 16 patterned into a predetermined shape is formed on the silicon oxide film 15, and the transfer mask 17 of the first layer is formed by etching according to the resist mask 16. Form. The transfer electrodes 17 extend in a direction intersecting the channel region provided in the diffusion layer 11 and are formed so as to be parallel to each other with a certain distance. Furthermore, after removing the resist mask 16, the silicon oxide film 13 is etched by the RIE method to remove the silicon substrate 10.
Expose the surface of. During this etching, the silicon oxide film 15 left on the transfer electrode 17 is removed.
It becomes a protective film of. Thus, if the silicon oxide film 13 is removed to expose the surface of the silicon substrate 10 after the resist mask 16 is removed, impurities generated by the removal of the resist mask 16 are removed.
Can be prevented from adhering to the surface.

Then, the side surface of the transfer electrode 17 and the surface of the silicon substrate 10 exposed in the gap portion of the transfer electrode 17 are thinly thermally oxidized to newly form a silicon oxide film 18 serving as a gate insulating film to a film thickness of 10 nm. . Therefore, as shown in FIG. 3, another silicon oxide film 19 is formed by CVD to have a film thickness of 150 nm so as to cover the silicon oxide film 18. This silicon oxide film 19 is formed by TEOS (Tetra
A low pressure CVD method using ethyl orthosilicate) is preferable. TEOS is an alcoholic liquid at room temperature, which is decomposed by heating to grow silicon oxide according to the reaction formula Si (OC ₂ H ₅ ) ₄ → SiO ₂ + 4C ₂ H ₄ + 2H ₂ O.
The silicon oxide film grown using S has good step coverage and is suitable for an interlayer insulating film.

After forming the silicon oxide film 19, as shown in FIG. 4, a polycrystalline silicon film 20 serving as a transfer electrode is formed on the silicon oxide film 19 to have a film thickness of 400 nm by the CVD method. Then, the portion of the polycrystalline silicon film 20 that overlaps the transfer electrode 17 is removed by a known etching process, and the second-layer transfer electrode 2 that covers the gap portion of the transfer electrode 17 is removed.
1 is formed. The transfer electrode 21 extends in the direction intersecting the channel region, like the transfer electrode 17 of the first layer,
The side portions are arranged so as to overlap the adjacent transfer electrodes 17. Further, on these transfer electrodes 21, wirings made of aluminum or the like are provided on the transfer electrodes 17, 21 via an insulating film.
Is formed so as to be connected to the end portions of the electrodes, and when the information charges are accumulated and transferred, the transfer electrodes 17 and 21 are transferred from the wirings.
A predetermined potential is supplied to.

Since the second-layer transfer electrode 21 is arranged on the silicon substrate 10 with the silicon oxide film 18 formed by thermal oxidation interposed therebetween, the second-layer transfer electrode 2 is formed.
The interface order under 1 is close to the interface order under the transfer electrode 17 of the first layer. That is, since the silicon oxide films 13 and 18 in contact with the silicon substrate 10 under the transfer electrodes 17 and 21 are both formed by thermal oxidation, the interface order of the silicon / silicon oxide interfaces is different in each part. It becomes almost equal. Therefore, as compared with the case where only the silicon oxide film formed by the CVD method is used as the gate insulating film, the interface state of the channel region becomes more uniform and the deterioration of transfer efficiency can be prevented.

In the above embodiments, the vertical overflow drain structure in which the P type diffusion layer 11 is formed on the N type silicon substrate 10 has been exemplified. However, a P type silicon substrate is used, and the vertical overflow drain structure is formed in the isolation region. A horizontal overflow drain structure provided with an overflow drain can be similarly implemented.

[0015]

According to the present invention, since the floating of the transfer electrode of the first layer can be prevented, etching residue is less likely to occur when the transfer electrode of the second layer is formed, current leakage can be prevented, and transfer can be prevented. It is possible to prevent variations in the effective gate length of the electrodes and obtain desired characteristics for each electrode.
Further, since the interface order under the transfer electrodes of the first layer and the interface order under the transfer electrodes of the second layer can be set to be substantially equal, the same characteristics can be obtained for each transfer electrode, and the deterioration of transfer efficiency can be prevented. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first manufacturing process of a solid-state imaging device of the present invention.

FIG. 2 is a cross-sectional view showing a second manufacturing process of the solid-state imaging device of the present invention.

FIG. 3 is a cross-sectional view showing a third manufacturing process of the solid-state imaging device of the present invention.

FIG. 4 is a cross-sectional view showing a fourth manufacturing process of the solid-state imaging device of the present invention.

FIG. 5 is a plan view showing an image pickup section of a conventional solid-state image pickup element.

6 is a cross-sectional view taken along line XX of FIG.

[Explanation of symbols]

 1, 10 Silicon substrate 2, 11 Diffusion layer 3 Separation region 4 Channel region 5, 12 Buried channel layer 6, 13, 15, 18, 19 Silicon oxide film 7, 8, 17, 21 Transfer electrode 14, 20 Polycrystalline silicon film 16 resist mask

Claims (2)

[Claims] 1. A method of manufacturing a solid-state imaging device, wherein a plurality of transfer electrodes intersecting with the channel region are arranged in multiple layers on a semiconductor substrate provided with a channel region serving as a charge transfer path. A step of sequentially forming a first conductive film and a first insulating film via a gate insulating film, and a resist having a shape extending on the first insulating film in a direction intersecting the channel region of the semiconductor substrate. Forming a mask and removing the first conductive film and the first insulating film except the region covered by the resist mask; forming a first transfer electrode; and removing the resist mask. After that, a step of removing the gate insulating film exposed in the region where the first conductive film and the first insulating film are removed, and a second step on the semiconductor substrate covering the first transfer electrode. Insulation film and And a step of forming a second transfer electrode by removing the second conductive film except at least a gap portion of the first transfer electrode. A method of manufacturing a characteristic solid-state imaging device. 2. The second insulating film is obtained by stacking an insulating material after oxidizing the surface of the semiconductor substrate exposed in the gap portion of the first transfer electrode.
A method for manufacturing the solid-state imaging device according to claim 1.