JPH06292169A - Video signal reproducing device - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to reduce the error in motion determination and prevent deterioration of an interpolated image by interpolating using pixels with high correlation. When interpolating a pixel block that is determined to be unreproducible by a propriety determining unit 2 that determines whether or not each pixel block can be reproduced, the time of pixel signals in a plurality of pixel blocks adjacent to the pixel block to be interpolated The motion determination circuit 9 determines the dynamic change and outputs one motion determination result to obtain a motion determination result in which the determination error is reduced, and after the determination result is obtained, the motion determination output is used. To switch between the first interpolation circuit (2, 3, 5) and the second interpolation circuit (2, 6, 8), and when the pixel block has a high correlation with the same screen, the pixel information of the same screen is used. ,
When the correlation with another screen is high, the pixel information of the other screen is used to interpolate, thereby preventing the inconvenience of interpolating using pixels having a small correlation with the pixel block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal reproducing apparatus, and more particularly, it is suitable for use in an apparatus for interpolating a so-called block coded image signal.

[0002]

2. Description of the Related Art Conventionally, as this type of image signal reproducing apparatus, an interpolating apparatus having a configuration as shown in FIG. 5 has been known. The configuration of the conventional image signal reproducing apparatus will be described below with reference to FIG.

In FIG. 5, a decoded signal is input to an error correction circuit (ECC circuit) 302 from an input terminal 301, a code error is corrected, and a frame memory 303 is input.
Entered in. At this time, the image data that could not be corrected by the ECC circuit 302 is not written in the frame memory 303 and becomes empty data, and an error flag indicating the address of the empty data is stored in the flag memory 304.
Entered in.

Reference numeral 305 denotes a motion judging circuit, which is the ECC.
After taking the difference between the output of the circuit 302 and the output of the frame memory 303 and integrating the difference data for each pixel block, the integrated data is compared with a predetermined value. As a result of the comparison, the motion determination circuit 305 determines that the pixel block has no motion and outputs a low level “0” when the integrated data is smaller than a predetermined value.

Further, when the result of the above-mentioned comparison shows that the above-mentioned integrated data is larger than a predetermined value, the pixel block is judged to be in motion, and a high level "1" is outputted. The output of these motion determination circuits 305 is hereinafter referred to as motion data.

The motion data is converted into the first delay circuit 306.
Entered in. Then, a third delay circuit 307 described later
The delay time of the first delay circuit 306 is adjusted such that the output data of the first delay circuit 306 and the motion data output from the first delay circuit 306 match the timing.

The output of the first delay circuit 306 is input to the a terminal of the first switch SW1 and the second delay circuit 30
When the output of 8 is input to the b terminal of the first switch SW1, a feedback loop is formed between the first switch SW1 and the second delay circuit 308 via the second delay circuit 308. ing.

The first switch SW1 is connected to the a terminal when the output of the fifth delay circuit 309 is "0", and b when the output of the fifth delay circuit 309 is "1".
It is designed to be connected to terminals. Second delay circuit 3
The delay time of the second delay circuit 308 is set so that the motion data output from 08 is in timing with the image data output from the fourth delay circuit 310 described later.

On the other hand, the image data output from the ECC circuit 302 is input to the third delay circuit 307 so that the data of the upper pixel block on the screen is output with respect to the output of the ECC circuit 302. The delay time of the delay circuit 307 is set.

Further, the image data output from the third delay circuit 307 is input to the fourth delay circuit 310, and the data of the upper pixel block on the screen is output with respect to the output of the third delay circuit 307. Thus, the delay time of the fourth delay circuit 310 is set.

Further, at the same timing, the flag memory outputs the error flag of the same pixel block as the output data of the ECC circuit 302, and the fifth delay circuit 309 outputs the error flag of the same pixel block as the output data of the third delay circuit 307. The error flag is output, and the sixth delay circuit 311 outputs the error flag of the same pixel block as the output data of the fourth delay circuit 310.

The image data output from the third delay circuit 307 is input to the fourth delay circuit 310 and also to the c terminal of the second switch SW2. In addition, the average value of the pixel data obtained by the average value calculation circuit 312 from the output of the ECC circuit 302 and the output of the fourth delay circuit 310 is input to the d terminal of the second switch SW2.

Therefore, the data input to the d terminal of the second switch SW2 is the average value of the image data in the pixel blocks above and below the image data input to the c terminal of the second switch SW2. . Also, the second switch SW2 is connected to the c terminal when the output of the logic operation circuit described later is "0", and is connected to the d terminal when the output of the logic operation circuit is "1". It has become.

A logical operation circuit 313 includes a flag memory 304, a fifth delay circuit 309, a sixth delay circuit 3 and 3.
The output of the logical operation circuit 313 is determined by the combination of the flag data output from each of the 11 and the motion determination result output from the first delay circuit 306, and is input to the second switch SW2.

The second switch SW2 selects one of the output data of the third delay circuit 307 and the average value calculation circuit 312 according to the output of the logic operation circuit 313 and outputs it to the output terminal.

If there is an error in the image data output from the third delay circuit 307, the fifth delay circuit 309
The flag data output by is 1 and is input to the logical operation circuit 313 and also to the first switch SW1, and the input of the first switch SW1 is connected to the b terminal. At this time, when there is no error in the pixel blocks above and below the pixel block output by the third delay circuit 307, the flag memory 304 and the sixth delay circuit 3
The flag data output by each of 11 is "0".

Since the motion data at this time cannot be output as a signal because the output data of the third delay circuit 307 has an error, the motion data of the upper pixel block with respect to the data output by the third delay circuit 307. Is used to detect motion. That is, when there is a motion in the upper pixel block with respect to the pixel block output by the third delay circuit 307, the motion data output by the second delay circuit 308 becomes “1” and the logical operation circuit 313. Output becomes "1" and is input to the second switch SW2.

When the output of the logical operation circuit 313 becomes "1", the second switch SW2 is connected to the d terminal and the output of the average value operation circuit 312, that is, the result of the intra-field interpolation is output terminal 314. Output to the outside. On the other hand, when there is no motion in the upper pixel block with respect to the pixel block output by the third delay circuit 307, the motion data output by the second delay circuit 308 becomes “0”,
The output of the logical operation circuit 313 becomes "0" and is input to the second switch SW2.

When the output of the logical operation circuit 313 becomes "0", the second switch SW2 is connected to the c terminal, and the output of the third delay circuit 307, that is, the input terminal 3
The result of inter-frame interpolation, which is the data one frame before the pixel data input from 01, is output from the output terminal 314 to the outside.

[0020]

However, in the above-mentioned conventional example, since the motion determination is performed only in the upper one block of the blocks to be interpolated, it is easy to make an erroneous motion determination, and the pixel block to be interpolated is erroneously determined. There is a problem that interpolation is performed using pixels having a small correlation, and the quality of the interpolated image deteriorates.

In view of the above problems, it is an object of the present invention to reduce errors in motion determination and to enable interpolation using highly correlated pixels.

[0022]

An image signal reproducing apparatus of the present invention is an image signal reproducing apparatus which obtains an image signal by blocking the encoded image signal for each predetermined number of pixels and decoding the encoded data in block units. A selecting means for selecting the interpolation data generated by a predetermined method, an interpolation means for interpolating the data of the undecodable block by the interpolation data selected by the selecting means, and the same screen as the undecodable block. Motion estimation means for estimating the motion of the undecodable block based on the motion of the surrounding blocks, and error pattern detection means for detecting an error in the surrounding blocks and controlling the interpolation means based on the error condition. The selecting means selects the interpolation data based on the estimation result of the motion estimating means.

Another characteristic of the present invention is that
An image signal reproducing device that obtains an image signal by decoding the encoded data in blocks of a predetermined number of pixels in units of blocks, which cannot be decoded using interpolation data generated by a predetermined method. An interpolation means for interpolating the data of the block is provided, and the interpolation data is selectively used based on the movement of the surrounding block on the same screen as the undecodable block.

[0024]

Since the present invention has the above technical means, when interpolating a pixel block determined to be unreproducible, for example,
One motion determination result is output from the temporal change of pixel signals in a plurality of pixel blocks adjacent to the pixel block to be interpolated to obtain a motion determination result with reduced determination error, and the determination result is obtained. After that, if the pixel block has a high correlation with the same screen, the pixel information of the same screen is used, and if the pixel block has a high correlation with another screen, the pixel information of the other screen is used for interpolation. This makes it possible to prevent the inconvenience of performing interpolation using pixels having a small correlation with the pixel block.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the image signal reproducing apparatus of the present invention will be described below with reference to FIG. First, a signal decoded by a decoding circuit (not shown) is input from an input terminal 1 to an error correction circuit (ECC circuit) 2, where a code error is corrected and then input to a frame memory 3.

At this time, the image data that cannot be corrected by the ECC circuit 2 is not written in the frame memory 3 but becomes empty data, and an error flag indicating the address of the empty data is input to the flag memory 4. 5 is 4H
A first delay circuit for delaying, and the first delay circuit 5
The delay time of the first delay circuit is set such that the output of the first delay circuit is data just one frame before the output of the third delay circuit 6 delayed by 4H, which will be described later.

The output of the first delay circuit 5 is input to the second delay circuit 7 which performs 4H delay. As for the delay time of the second delay circuit 7, the output of the second delay circuit 7 will be described later.
It is set to be exactly one frame before the output of the fourth delay circuit 8 which performs H delay. And first to fourth
The outputs of the delay circuits are input to the motion determination circuit 9, respectively.

The motion determination circuit 9 takes the difference between the output of the ECC circuit 2 and the output of the frame memory 3 and the difference between the output of the second delay circuit 7 and the output of the fourth delay circuit 8, respectively, After integrating all the absolute values of the difference data, the integrated data is compared with a predetermined value.

As a result of the comparison, the motion judging circuit 9 judges that there is no motion and outputs a low level "0" when the integrated data is smaller than a predetermined value. Further, when the integrated data is larger than a predetermined value, it is determined that there is motion and a high level “1” is output.
Hereinafter, the output of these motion determination circuits 9 will be referred to as motion data.

Next, 10 is an interpolation calculation circuit, and this interpolation calculation circuit 10 outputs intra-field interpolation data from the outputs of the ECC circuit 2 and the fourth delay circuit 8. The output of the interpolation calculation circuit 10 is input to the b terminal of the first switch SW1.

The switching operation of the first switch SW1 is as follows.
It is controlled by the output of the motion determination circuit 9, and when the motion determination circuit output is "0", it is connected to the a terminal, and when it is "1", it is connected to the b terminal. As a result, the interpolation calculation circuit 10 calculates from the output of the fifth delay circuit 12 (interframe interpolation data) which is the pixel data of one frame before, the output of the ECC circuit 2 and the output of the third delay circuit 6. The selected interpolated value (interpolated data in the field) is selected.

The output of the first switch SW1 is input to the c terminal of the second switch SW2, and the output of the first switch SW1 which is the interpolation data and the unprocessed first output are input by the second switch SW2. 3 and the output data of the delay circuit 6 are selected.

The output of the flag memory 4 is supplied to the fifth delay circuit 12. In addition, the fifth delay circuit 12
The delay time is set so as to output the error flag of the pixel block output from the third delay circuit 6.

The output of the sixth delay circuit 13 is supplied to the logical operation circuit 14. The sixth delay circuit 13 has a fourth
The delay time is set so as to output the error flag of the pixel block output from the delay circuit 8.

The outputs of the flag memory 4, the fifth delay circuit 12 and the sixth delay circuit 13 are supplied to the logical operation circuit 14, respectively. The logical operation circuit 14 performs a predetermined logical operation from the above-mentioned input data and outputs a signal for controlling the second switch SW2.

The output of the first switch SW1 is supplied to the c terminal of the second switch SW2, and the output of the third delay circuit 6 is supplied to the d terminal. The second switch SW2 is interpolated data by being connected to the d terminal when the output of the logical operation circuit 14 is "0" and connected to the c terminal when the output of the logical operation circuit 14 is "1". The output of the first switch SW1 and the output of the third delay circuit 6 which is unprocessed pixel data are selected and output to the outside through the output terminal 15.

The logical operation circuit 14 is configured, for example, as shown in FIG. 2, and outputs only when the input from the input terminals g and i is "0" and the input from the input terminal h is "1". Becomes "1".

Next, FIG. 4 shows a structural example of the motion judging circuit 9 used in the image signal reproducing apparatus of the present invention. In FIG.
Reference numeral 501 is a first subtraction circuit that subtracts the input signal of the input terminal h and input signal of the input terminal j, and 502 is a second subtraction circuit that subtracts the input signal of the input terminal i and the input signal of the input terminal k. A circuit, 503 is a first absolute value calculation circuit for calculating the absolute value of the output signal of the first subtraction circuit 501, 504.
Is a second absolute value calculation circuit for calculating the absolute value of the output signal of the second subtraction circuit 502, and 505 is the output of the first absolute value calculation circuit 503 and the output of the second absolute value calculation circuit 504. Is a first adder circuit that performs the addition operation of.

Reference numeral 506 is a second adder circuit for performing addition operation of the first adder circuit 505 and the output of a delay circuit 507, which will be described later, 507 is a delay circuit for delaying the output of the second adder circuit 506, and 510 is a delay circuit. A read only memory (ROM) 511 in which data to be compared with the output of the circuit 507 is stored in advance is a third subtraction circuit 512 for calculating the difference between the output of the line delay circuit 507 and the output of the ROM 510. Is a positive / negative determination circuit for determining the positive / negative of the output result of the third subtraction circuit 511, and 513 is an output terminal. The input terminals h, i, j, k correspond to the input terminals (not shown) provided in the motion determination circuit 9 in FIG.

Next, the operation of the motion determination circuit shown in FIG. 5 will be described. The image signal input from the input terminal h and the image signal input from the input terminal j have a time difference of exactly one frame. When attention is paid to a certain pixel, the absolute value of the difference between the frames becomes small when the amount of movement on the screen is small, so the output of the first absolute value calculation circuit 503 becomes small.

Further, when there is a lot of movement on the screen, the absolute value of the difference between the frames becomes large, so that the output of the first absolute value calculation circuit 503 becomes large. Similarly, the image signal input from the input terminal i and the image signal input from the input terminal k have a time difference of exactly one frame, and when the motion is small, the second absolute value calculation circuit 504 is operated.
The output of the second absolute value calculation circuit 504 becomes large when there is a lot of movement on the screen.

The output of the first absolute value calculation circuit 503 and the second
Output of the absolute value calculation circuit 504 of the first addition circuit 5
It is added by 05. Hereinafter, the first addition circuit 505
Is called the difference absolute value.

Second adder circuit 506 and delay circuit 507
Adds the absolute difference value described above for one pixel block. The delay circuit 507 is controlled by a control circuit (not shown) so as to add the above-described absolute difference value over one block for each pixel block. Hereinafter, the delay circuit 50
The output of 7 is called the sum of absolute differences.

The third subtraction circuit 511 subtracts the sum of absolute differences and the ROM 510, and the positive / negative determination circuit 51 is executed.
By determining whether the output of the third subtraction circuit is positive or negative at 2,
The comparison value previously stored in M510 and the sum of absolute differences are compared. The positive / negative determination circuit 512 outputs "1" as the motion is present when the difference absolute value sum is larger than the comparison value, and outputs "0" as no motion when the difference absolute value sum is smaller than the comparison value. To do. This determination result is calculated for each pixel block. The comparison value stored in advance in the ROM 510 is set to, for example, a half value of the total value of all the pixels forming the pixel block.

Next, the operation of the image signal of this embodiment will be described with reference to FIG. FIG. 3 shows a pixel block on the screen. Now, the pixel data of the block of Bi, j + 1 is ECC
If it is output from the circuit 2, the third delay circuit 6
Outputs Bi, j pixel data from the
From the delay circuit 6 of 1, the pixel data of Bi, j one frame before is obtained. The fourth delay circuit 8 outputs Bi, j-1 pixel data, and the second delay circuit 7 outputs Bi, j-1 pixel data one frame before. .

The flag memory 4 outputs a Bi, j + 1 error flag, the fifth delay circuit 12 outputs a Bi, j error flag, and the sixth delay circuit 13 outputs a Bi, j-1 error flag. Error flags are output respectively.

The motion determination circuit 9 includes blocks Bi, j + 1 and 1
The difference between Bi, j + 1 before the frame and the difference between Bi, j-1 one block before and Bi, j-1 one frame before is calculated, and these differences are integrated for two blocks Is compared with a predetermined comparison value. When the integrated data is smaller than the predetermined value, it is determined that there is no motion and low level "0" is output. When the integrated data is larger than the predetermined value, it is determined that there is motion and a high level "1" is output.

At this time, the blocks Bi, j-1 and Bi, j + 1
When both and are reproducible and the block Bi, j is not reproducible, the output of the logical operation circuit 14 becomes 1, the second switch SW2 is connected to the c terminal, and the block Bi, j is interpolated. Become.

The interpolation of the block Bi, j differs depending on the motion data output of the motion judging circuit 9. When the motion determination circuit 9 outputs "0", the first switch SW1 is connected to the a terminal, and the block Bi, j is interpolated between frames.
When the motion determination circuit 9 outputs "1", the first switch SW1 is connected to the b terminal and the block Bi, j is interpolated in the field. Since the image signal reproducing apparatus of this embodiment is configured as described above, it is possible to perform accurate interpolation.

[0050]

As described above, according to the present invention, erroneous motion determination is less likely to occur during motion determination, and interpolation is performed using pixels having a small correlation with the interpolated pixel block. Since it does not occur, it is possible to reduce the image quality deterioration of the interpolated image.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an image signal reproducing apparatus of the present invention.

FIG. 2 is a diagram showing an example of a logical operation circuit used in the present invention.

FIG. 3 is a diagram for explaining the operation of the image signal reproducing device of the present invention.

FIG. 4 is a diagram illustrating an example of a motion determination circuit.

FIG. 5 is a block diagram of an image signal reproducing apparatus showing a conventional example.

[Explanation of symbols]

 2 error correction circuit (ECC circuit) 3 frame memory 4 flag memory 5, 6, 7, 8 pixel data delay circuit 9 motion determination circuit 10 interpolation calculation circuit 12 and 13 error flag delay circuit 14 logical calculation circuit SW1 first Switch SW2 Second switch

Claims (2)

[Claims] 1. An image signal reproducing apparatus which obtains an image signal by block-coding an image signal for each predetermined number of pixels and decoding encoded data in block units, wherein interpolation data generated by a predetermined method is selected. Selecting means, an interpolation means for interpolating the data of the non-decodable block by the interpolation data selected by the selecting means, and the non-decodable based on the motion of the surrounding block of the same screen as the non-decodable block. The motion estimation means for estimating the motion of the block; and the error pattern detection means for detecting the error of the surrounding block and controlling the interpolation means based on the error condition, wherein the selecting means comprises the motion estimating means. The image signal reproducing apparatus, wherein the interpolation data is selected based on the estimation result of 1. 2. An image signal reproducing apparatus which obtains an image signal by decoding an image signal into blocks for each predetermined number of pixels and decoding the encoded data in block units, wherein interpolation data generated by a predetermined method is used. And an interpolation means for interpolating the data of the non-decodable block, and the interpolated data is selectively used based on the movement of a surrounding block on the same screen as the non-decodable block. .