JPH06302768A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable wafer testing without probing all bonding pads of a high-density multi-pin LSI wafer with metal probe needles. Configuration: Input / output bonding pads 31, 34 for electrically connecting the semiconductor integrated circuit to the outside, and input / output circuit parts 41, 44 connected to the input / output bonding pads
And a selection switching circuit 10 connected between the input / output logic circuit section and the internal logic circuit section 20. The switching operation of the selection switching circuit is controlled by the wafer test switching input signals T1 and T2.
By controlling the input / output circuit section connected to one input / output bonding pad to the internal logic circuit section connected to the input / output circuit section connected to another input / output bonding pad. The one input / output bonding pad 31 enables a probe test of a plurality of circuit parts in an internal logic circuit part in a wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of performing a probe test on a high density multi-pin semiconductor integrated circuit wafer.

[0002]

2. Description of the Related Art FIG. 4 is a diagram schematically showing an input / output unit of a conventional semiconductor integrated circuit device (hereinafter referred to as an LSI).
1, 12, 13 are input bonding pads, 14, 1
Reference numerals 5 and 16 are input buffers, 21, 22 and 23 are output bonding pads, and 24, 25 and 26 are output buffers. The input signals IN1, IN2, IN3 supplied to the input bonding pads 11, 12, 13 pass through the input buffers 14, 15, 16 respectively, and the input signals in1, in
2, in3, and transmitted to the internal logic circuit section 2. On the other hand, output signals out1 and out from the internal logic circuit unit 2
2 and out3 are output buffers 24, 25 and 26, respectively.
To output signals OUT1, OUT2, OUT3,
It is transmitted to the output bonding pads 21, 22, 23.

[0003]

Since the conventional LS1 is constructed as shown in FIG. 4, it is necessary to probe all the bonding pads 11 to 13 and 21 to 23 with a metal probe needle during a wafer probe test. . Therefore, in a high-density multi-pin LSI, the arrangement pitch of the bonding pads becomes extremely small, and it is necessary to make the metal probe needle thin correspondingly, which causes a problem in durability of the metal probe needle. There is also a problem that probing itself becomes impossible as the number of high-density and more pins increases.

[0004]

SUMMARY OF THE INVENTION The present invention solves the problems relating to the conventional probe test of a high-density multi-pin LSI wafer, and facilitates a high-density multi-pin LSI wafer probe test. An object is to obtain a semiconductor integrated circuit device that can be manufactured. The semiconductor integrated circuit according to the present invention basically connects one input / output bonding pad to another input / output bonding pad between the input / output unit connected to the input / output bonding pad and the internal logic circuit unit. A selection switching circuit that can access the selected internal logic circuit portion is provided, and the operation of the selection switching circuit is controlled by a wafer test switching input signal to be supplied to another input / output bonding pad by the one input / output bonding pad. The input signal and the output signal can be respectively input or monitored.

[0005]

According to the present invention, an input signal of another input bonding pad can be input from one bonding pad, and an output signal appearing at another output bonding pad can be monitored. No need to probe all bonding pads with a metal probe needle. Therefore, the probe test of the wafer can be easily performed even when the arrangement pitch of the bonding pads is extremely small in the high density multi-pin LSI.

[0006]

FIG. 1 is a diagram showing the structure of an input / output section related to the present invention of a first embodiment of a semiconductor integrated circuit device of the present invention.
Reference numerals 31, 32, 33, and 34 denote bonding pads, and the input bonding pad 31 is connected to each data input D of the data latches 4 and 5 via the input buffer 41 and is supplied with the wafer test switching input signal T1. Is connected to the trigger input E of the data latch 4 via the input buffer 42, and is connected to the trigger input E of the data latch 5 via the input buffer 42 and the inverter 6. Reference numeral 35 is a pull-up resistor.

The bonding pad 33 to which the wafer test switching input signal T2 is supplied is supplied to one gate terminal of each of the transmission gates 8 and 9 via the input buffer 43, and the input buffer 43 and the inverter 3 are also provided.
It is connected via 6 to the other gate terminal of each of transmission gates 8 and 9. The transmission gates 8 and 9 and the inverter 36 constitute the switching circuit 10,
The switching circuit 10 and the data latches 4 and 5 form a selection switching circuit. The input bonding pad 34 is connected to the transmission line of the transmission gate 9 via the input buffer 44. The transmission gates 8 and 9 are, for example, FEs of opposite conductivity type as shown in the figure.
A parallel connection of T is used. 37 and 38 are pull-up resistors.

The Q output of the data latch 4 is connected to a predetermined circuit portion of the internal logic circuit portion 20 of the integrated circuit device, and the Q output of the data latch 5 passes through the transmission gate 8 and the other circuit portion of the internal logic circuit portion 20. The transmission gate 9 is also connected to the other circuit portion of the internal logic circuit section 20.

Next, the operation of the semiconductor integrated circuit device of FIG. 1 will be described. In FIG. 1, when the wafer test switching input signal T2 supplied to the bonding pad 33 is set to the ground level (hereinafter, referred to as L level), the transmission gate 8 is turned on and the transmission gate 9 is turned on.
Turns off. Here, when the wafer test switching input signal T1 supplied to the bonding pad 32 is set to the power supply level (hereinafter referred to as H level), the data latch 4
Becomes the data through state, and the input bonding pad 3
The input signal IN1 supplied to 1 is transmitted to the internal logic circuit section 20 as the signal in1 via the input buffer 41 and the data latch 4.

On the other hand, since the inverted input of the signal T1 is supplied to the trigger input E of the data latch 5 by the inverter 6, the data latch 5 is in the latch state and in2 is irrespective of the change of the input signal IN1. Holds a constant value. Next, when the wafer test switching input signal T1 is set to the L level, the data latch 4 enters the latch state, and in1 is maintained at a constant value regardless of the change of the input signal IN1.
On the other hand, the data latch 5 enters the data through state, and the input signal IN1 supplied to the bonding pad 31 is supplied to the other part of the internal logic circuit section 20 as the signal in2 via the data latch 5 and the transmission gate 8. It Therefore, by switching the wafer test switching input signal between H and L, the input signals supplied to the input bonding pad 31 can be separately transmitted as in1 and in2 to predetermined circuit portions of the internal logic circuit section 20. . As a result, the above-mentioned predetermined circuit portion probe test of the wafer can be performed using one input bonding pad 31.

Next, when the wafer test switching input signal T2 supplied to the bonding pad 33 is set to H level,
The transmission gate 8 turns off and the transmission gate 9 turns on. As a result, the input signal IN2 supplied to the input bonding pad 34 irrespective of the output of the data latch 5 passes through the input buffer 44 and the transmission gate 9 and then the signal in2.
Is transmitted to the internal logic circuit 20. At this time, if the wafer test switching signal T1 supplied to the bonding pad 32 is set to the H level like T2, the input signal IN1 supplied to the bonding pad 31 will be input to the input buffer 4.
Similarly, since the signal in1 is supplied to the internal logic circuit section 20 via the data latch 4, the wafer can be brought into an actual operating state by IN1 and IN2. As described above, in the embodiment of FIG. 1, by probing one bonding pad 31 with the metal probe needle, the circuit portion in the internal logic circuit unit 20 connected to another bonding pad in the actual specification state is removed. Can also be tested.

FIG. 2 shows the structure of the input / output unit according to the second embodiment of the present invention. In the embodiment of FIG. 2, the input bonding pad 51 is connected to the data input D of the data latch 54 via the input buffer 61, and the output Q of the data latch 54 is connected to the internal logic circuit 30 of the wafer. The bonding pad 52 is connected to the trigger input E of the data latch 54 and the control input of the gate type tri-state output buffer 62 via the input buffer 63. The selection switching circuit 28 is constituted by the output buffer 62 and the data latch 54.
Make up. The internal signal out1 of the internal logic circuit section 30 is transmitted to the output bonding pad 53 as the external output signal OUT1 via the output buffer 64. The internal output signal out1 is also supplied to the input of the tri-state output buffer 62, and the output of the tri-state output buffer 62 is connected to the input bonding pad 51.
Reference numeral 65 is a pull-up resistor.

The operation of the semiconductor integrated circuit device of FIG. 2 will be described. When the wafer test switching input signal T1 supplied to the bonding pad 52 is set to L level, the tri-state output buffer 62 is turned on, and the internal logic circuit section 3 is turned on.
The output signal out1 of 0 is transmitted to the input bonding pad 51 as OUT1. At this time, the data wrap 54 is in the latched state, and the internal input signal in3 of the internal logic circuit section 30 is maintained at a constant value regardless of the output of the input buffer 61.

When the wafer test switching input signal T1 is set to the H level, the data latch 54 enters the data through state and the tristate output buffer 62 is turned off. Therefore, the input signal IN3 supplied to the input bonding pad 51 is supplied to the internal logic circuit section 30 as in3 via the input buffer 61 and the data latch 54. Further, regardless of the level of the wafer test switching input signal T1, the output signal out1 of the other circuit portion of the internal logic circuit section 30 is transmitted to the output bonding pad 53 as OUT1 via the output buffer 64. Therefore, FIG.
In this embodiment, one input bonding pad 51 is selected by switching the level of the wafer test switching input signal T1.
Input signal IN3 by probing with a metal probe needle.
Can be transmitted as in3 to a specific circuit portion of the internal logic circuit portion 30, and the internal output signal out1 of another circuit portion can be monitored.

FIG. 3 shows the structure of the input / output unit of the third embodiment of the present invention. In FIG. 3, 71 and 72 are output bonding pads, 73 is a bonding pad to which the wafer test switching input signal T1 is supplied, 81 and 82 are output buffers,
Reference numeral 83 is an input buffer, 84 is an inverter, 85 is a pull-up resistor, 8 and 9 are transmission gates, and 40 is an internal logic circuit section. Transmission gate 8,
9 and the inverter 84 form the switching selection circuit 50.

The operation of FIG. 3 will be described. When the wafer test switching input signal T1 is at the level, the transmission gate 8 is turned on and the transmission gate 9 is turned off. At this time, the internal output signal out3 of a specific circuit portion in the internal logic circuit portion 40 is transmitted to the output bonding pad 71 via the transmission gate 8 and the output buffer 81 and is monitored. When the wafer test switching input signal T1 is at the H level, the transmission gate 9 is turned on, the transmission gate 8 is turned off, and the internal output signal out2 of the other circuit portion of the internal logic circuit portion 40 is transmitted to the transmission gate 9 and the output buffer 81. Then, it is transmitted to the output bonding pad 71 and monitored. Further, the internal output signal out3 of the other circuit portion is transmitted to the output bonding pad 72 via the output buffer 82 regardless of the level of the wafer test switching input signal T1 supplied to the bonding pad 73. Therefore, in the embodiment of FIG. 3 as well, by switching the level of the switching input signal T1 for wafer test, one output bonding pad 71 is probed with a metal probe needle to generate two internal output signals o.
ut2 and out3 can be monitored.

[0017]

As described above, in the present invention, the selection switching circuit controlled by the wafer test switching input signal is provided between the input / output circuit section connected to the input / output bonding pad and the internal logic circuit section. Therefore, it is not necessary to probe all the bonding pads with metal probe needles during the wafer test by probing, and it is possible to test the wafer easily and with high reliability even when the arrangement pitch of the bonding pads is extremely small in the high density multi-pin LSI. Since the number of probing of the metal probe needle is reduced, even if a thin metal probe needle compatible with high density multi-pin is used, there is little wear and there is no problem in durability. Absent.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an input / output unit of a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a diagram showing a configuration of an input / output unit of a second embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 3 is a diagram showing a configuration of an input / output unit of a third embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 4 is a diagram showing a configuration of an input / output unit of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 4 data latch 5 data latch 6 inverter 10 switching circuit 20 internal logic circuit section 28 selection switching circuit 30 internal logic circuit section 31 input bonding pad 32 bonding pad 33 bonding pad 34 input bonding pad 40 internal logic circuit section 41 input buffer 42 input buffer 43 Input Buffer 44 Input Buffer 50 Selection Switching Circuit 51 Input Bonding Pad 52 Bonding Pad 53 Output Bonding Pad 54 Data Latch 61 Input Buffer 62 Tri-State Output Buffer 63 Input Buffer 64 Output Buffer 71 Bonding Pad 72 Bonding Pad 73 Bonding Pad 81 Output Buffer 82 output buffer 83 input buffer

Claims (3)

[Claims] 1. A plurality of input bonding pads for electrically connecting the semiconductor integrated circuit to the outside, an input circuit unit connected to the input bonding pads, the input circuit unit and the inside of the semiconductor integrated circuit. A wafer test, which comprises a selection switching circuit including two or more data latches connected to a logic circuit section and at least one switching circuit, and is supplied to the switching circuit from outside the semiconductor integrated circuit. The switching circuit is controlled by the switching input signal so that an input circuit unit connected to a specific one input bonding pad among the plurality of input bonding pads becomes an input circuit unit connected to another input bonding pad. A semiconductor integrated circuit device characterized in that it is connected to an internal logic circuit part connected thereto so that an input signal can be supplied thereto. 2. An input bonding pad and an output bonding pad for electrically connecting the semiconductor integrated circuit to the outside, an input circuit section connected to the input bonding pad, and an output connected to the output bonding pad. A circuit section, a data latch connected between the input circuit section and an internal logic circuit section of the semiconductor integrated circuit, and another internal logic circuit section of the semiconductor integrated circuit connected to the output circuit section and the input A gate-type output circuit section connected between the bonding pad and the gate pad, the gate-type output circuit section and the data latch constitute a selection switching circuit, and the gate-type output circuit section and the gate-type output circuit section from the outside of the semiconductor integrated circuit. The selection switching circuit is controlled by the wafer test switching input signal supplied to the data latch and the other internal logic circuit portion is gated. A semiconductor integrated circuit device, characterized in that it is connected to the input bonding pad via an output circuit section so that the output signal of the other internal logic circuit section can be monitored by the input bonding pad. 3. A plurality of output bonding pads for electrically connecting the semiconductor integrated circuit to the outside, an output circuit unit connected to the output bonding pads, the output circuit unit and the inside of the semiconductor integrated circuit. A selection switching circuit connected to a logic circuit section, and controlling the selection switching circuit by a wafer test switching input signal supplied from the outside of the semiconductor integrated circuit to the selection switching circuit. The output circuit section connected to a specific one of the output bonding pads of the above is connected to the internal logic circuit section connected to the output circuit section connected to the other output bonding pad, and this internal logic is connected. A semiconductor integrated circuit device characterized in that an output signal of a circuit portion can be monitored by the above-mentioned specific one output bonding pad.