JPH06314770A - Semiconductor resistor and forming method thereof - Google Patents
Semiconductor resistor and forming method thereofInfo
- Publication number
- JPH06314770A JPH06314770A JP12795893A JP12795893A JPH06314770A JP H06314770 A JPH06314770 A JP H06314770A JP 12795893 A JP12795893 A JP 12795893A JP 12795893 A JP12795893 A JP 12795893A JP H06314770 A JPH06314770 A JP H06314770A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- semiconductor
- silicon nitride
- oxygen
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000005204 segregation Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052796 boron Inorganic materials 0.000 abstract description 17
- 239000000463 material Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 101000635799 Homo sapiens Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Proteins 0.000 abstract 2
- 102100030852 Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Human genes 0.000 abstract 2
- 230000001788 irregular Effects 0.000 abstract 1
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体抵抗に関し、特に
多結晶シリコン抵抗（すなわちポリシリコン）を生成す
る場合に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor resistor, and is particularly suitable for application in producing a polycrystalline silicon resistor (that is, polysilicon).
【０００２】[0002]
【従来の技術】従来、ポリシリコン抵抗は図４の処理工
程によつて形成されている。シリコン基板上への各素子
の作り込み工程が終了した後、フイールド領域に形成さ
れた酸化膜１の上にポリシリコン２を化学気相成長（以
下ＣＶＤ：ChemicalVapor Deposition ）によつて堆積
させる（図４（Ａ））。堆積されたポリシリコン２にボ
ロン（ＢＦ2 + ) をイオン注入し（図４（Ｂ））、続い
てレジスト３をポリシリコン２上に塗布して抵抗パター
ンを露光する。2. Description of the Related Art Conventionally, a polysilicon resistor is formed by the processing steps shown in FIG. After the process of forming each element on the silicon substrate is completed, polysilicon 2 is deposited on the oxide film 1 formed in the field region by chemical vapor deposition (hereinafter, CVD: Chemical Vapor Deposition) (see FIG. 4 (A)). Boron (BF 2 + ) is ion-implanted into the deposited polysilicon 2 (FIG. 4B), and subsequently, a resist 3 is applied on the polysilicon 2 to expose the resistance pattern.
【０００３】この後、反応性イオンエツチング（ＲＩ
Ｅ：Reactive Ion Etching）によつてポリシリコン２を
パターニングし、ポリシリコン抵抗パターンを形成する
（図４（Ｃ））。続いてポリシリコン抵抗パターンの上
側に酸化膜４をＣＶＤによつて堆積し、ポリシリコン抵
抗パターンの表面を全面を酸化膜（ＳｉＯ2 ）によつて
包み込む（図４（Ｄ））。After this, reactive ion etching (RI
The polysilicon 2 is patterned by E: Reactive Ion Etching) to form a polysilicon resistance pattern (FIG. 4C). Subsequently, an oxide film 4 is deposited on the upper side of the polysilicon resistance pattern by CVD, and the entire surface of the polysilicon resistance pattern is covered with an oxide film (SiO 2 ) (FIG. 4 (D)).
【０００４】次にポリシリコン抵抗パターン中に注入さ
れているボロン（Ｂ）をアニール処理によつて拡散し、
ボロンを均一に拡散する（図４（Ｄ））。この後、酸化
膜４にコンタクトホールを穿設し、開口部にアルミニウ
ムを蒸着して配線５を形成する。表面を保護膜によつて
覆うことによつてポリシリコン抵抗の形成が終了する。Next, the boron (B) implanted in the polysilicon resistance pattern is diffused by an annealing treatment,
Boron is uniformly diffused (FIG. 4 (D)). After that, a contact hole is formed in the oxide film 4, and aluminum is deposited in the opening to form the wiring 5. The formation of the polysilicon resistor is completed by covering the surface with the protective film.
【０００５】[0005]
【発明が解決しようとする課題】ところがこのような構
造によつてポリシリコン抵抗を生成しようとすると、ア
ニール処理の際に大気中の酸素が酸化膜を通してポリシ
リコン２に混入することがある。この酸素の混入がある
と、酸化膜１及び４とポリシリコン２の界面において偏
析現象が生じ、ポリシリコン２中のボロンが酸化膜中に
吸い出され、ポリシリコン２の界面付近のボロン濃度が
落ち込むことがあつた（図５（Ｂ））。これは抵抗値の
バラツキの原因となつている。However, when attempting to generate a polysilicon resistance by such a structure, oxygen in the atmosphere may be mixed into the polysilicon 2 through the oxide film during the annealing process. When this oxygen is mixed, segregation occurs at the interface between the oxide films 1 and 4 and the polysilicon 2, boron in the polysilicon 2 is sucked out into the oxide film, and the boron concentration near the interface of the polysilicon 2 is increased. I was depressed (Fig. 5 (B)). This causes variation in resistance value.
【０００６】そこで抵抗パターンの形成後、ＣＶＤによ
つてシリコン窒化膜（ＳｉＮ）７をポリシリコン２の上
に堆積させることによりポリシリコン２の上面及び側面
を覆つてから酸化膜４を堆積し、アニール処理する方法
が提案されている（図６）。この方法を用いると、アニ
ール時に大気中から侵入する酸素はシリコン窒化膜７に
よつて遮断されるため少なくともポリシリコン２の上面
では偏析現象を抑えることができる（図７（Ｂ））。し
かしポリシリコン２の底面は酸化膜１と接しているため
偏析現象を避け得ず、ポリシリコン２の底部におけるボ
ロン濃度の低下によつて抵抗値が変動するおそれを回避
し得なかつた。Therefore, after forming the resistance pattern, a silicon nitride film (SiN) 7 is deposited on the polysilicon 2 by CVD to cover the upper surface and the side surface of the polysilicon 2 and then the oxide film 4 is deposited. A method of annealing is proposed (FIG. 6). Using this method, oxygen penetrating from the atmosphere during annealing is blocked by the silicon nitride film 7, so that the segregation phenomenon can be suppressed at least on the upper surface of the polysilicon 2 (FIG. 7B). However, since the bottom surface of the polysilicon 2 is in contact with the oxide film 1, the segregation phenomenon cannot be avoided, and the resistance value may not fluctuate due to the decrease in the boron concentration at the bottom of the polysilicon 2.
【０００７】本発明は以上の点を考慮してなされたもの
で、ポリシリコン抵抗中の不純物濃度分布が均一であ
り、従来に比して抵抗値の精度が高い半導体抵抗を提案
しようとするものである。The present invention has been made in consideration of the above points, and an object of the present invention is to propose a semiconductor resistor in which the impurity concentration distribution in the polysilicon resistor is uniform and the resistance value of which is higher than that of the conventional one. Is.
【０００８】[0008]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、ポリシリコン２に不純物Ｂを導入
することによつて形成される半導体抵抗において、ポリ
シリコン２の全面が、酸素を透過せず、かつポリシリコ
ン２に対して偏析係数が１でなる物質の絶縁膜１１及び
１２によつて包まれてなるようにする。また本発明にお
いては、ポリシリコン２に不純物Ｂを導入した後、ポリ
シリコン２の全面を全てシリコン窒化膜（ＳｉＮ）によ
つて包み込み、その後、アニール工程によつて不純物Ｂ
を拡散させることにより半導体抵抗を生成するようにす
る。In order to solve such a problem, in the present invention, in the semiconductor resistor formed by introducing the impurity B into the polysilicon 2, the entire surface of the polysilicon 2 is permeable to oxygen. Not to be used, and it is wrapped with the insulating films 11 and 12 of a material having a segregation coefficient of 1 with respect to the polysilicon 2. Further, in the present invention, after the impurity B is introduced into the polysilicon 2, the entire surface of the polysilicon 2 is covered with the silicon nitride film (SiN) and then the impurity B is subjected to the annealing process.
To generate a semiconductor resistance.
【０００９】[0009]
【作用】半導体抵抗を構成するポリシリコン２の全面
を、酸素を透過せず、かつポリシリコン２に対して偏析
係数が１でなる物質の絶縁膜１１及び１２によつて包む
込んだことにより、アニール時に酸素の影響によつてポ
リシリコン２中の不純物の濃度が不均一になるおそれを
有効に回避することができる。Since the entire surface of the polysilicon 2 forming the semiconductor resistor is covered with the insulating films 11 and 12 of a substance which does not permeate oxygen and has a segregation coefficient of 1 with respect to the polysilicon 2, It is possible to effectively avoid the possibility that the concentration of impurities in the polysilicon 2 becomes non-uniform due to the influence of oxygen during annealing.
【００１０】[0010]
【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.
【００１１】図４との対応部分に同一符号を付して示す
図１において、１０は全体として不純物濃度が均一なポ
リシリコン抵抗を示し、ポリシリコン２の全表面をシリ
コン窒化膜１１及び１２によつて包み込んだことを除い
て同様の構成を有している。このポリシリコン抵抗１０
は図２に示す手順によつて形成される。まずシリコン基
板上に各素子を作り込む工程が終了した後、フイールド
領域の上に形成された酸化膜（ＳｉＯ2 ）上にシリコン
窒化膜１１をＣＶＤによつて堆積させる（図２
（Ａ））。In FIG. 1 in which parts corresponding to those in FIG. 4 are designated by the same reference numerals, reference numeral 10 denotes a polysilicon resistor having a uniform impurity concentration as a whole, and the entire surface of the polysilicon 2 is formed into silicon nitride films 11 and 12. It has the same structure except that it is wrapped around. This polysilicon resistor 10
Are formed by the procedure shown in FIG. First, after the step of forming each element on the silicon substrate is completed, the silicon nitride film 11 is deposited by CVD on the oxide film (SiO 2 ) formed on the field region (FIG. 2).
(A)).
【００１２】このシリコン窒化膜１１がポリシリコン抵
抗の底部とシリコン酸化膜１とを分離する膜となる。続
いてポリシリコン２をＣＶＤによつてシリコン窒化膜１
１上に重ねて堆積させ、ボロン（ＢＦ2 + ) をイオン注
入する（図２（Ｂ））。その後、ポリシリコン２の上に
レジストを塗布し、露光されたポリシリコン抵抗のパタ
ーンに沿つてポリシリコン２及びシリコン窒化膜１１を
取り除く（図２（Ｃ））。This silicon nitride film 11 serves as a film for separating the bottom of the polysilicon resistor from the silicon oxide film 1. Subsequently, polysilicon 2 is deposited by CVD on the silicon nitride film 1
1 is stacked and deposited, and boron (BF 2 + ) is ion-implanted (FIG. 2B). After that, a resist is applied on the polysilicon 2 and the polysilicon 2 and the silicon nitride film 11 are removed along the exposed pattern of the polysilicon resistance (FIG. 2C).
【００１３】続いてこれらポリシリコン２及びシリコン
窒化膜１１を上面から覆うようにシリコン窒化膜１２を
堆積し、その後、アニール処理することによつてポリシ
リコン２中にボロン（Ｂ）を均一に拡散させる。その後
はシリコン窒化膜１２を保護膜４によつて覆つた後、ポ
リシリコン抵抗パターンの両端位置にコンタクトホール
を形成してアルミニウムを蒸着することによりポリシリ
コン抵抗１０を形成するようになされている。Subsequently, a silicon nitride film 12 is deposited so as to cover the polysilicon 2 and the silicon nitride film 11 from the upper surface, and then an annealing treatment is performed to uniformly diffuse boron (B) into the polysilicon 2. Let After that, after covering the silicon nitride film 12 with the protective film 4, contact holes are formed at both end positions of the polysilicon resistance pattern and aluminum is vapor-deposited to form the polysilicon resistance 10.
【００１４】以上の工程によつて形成されたポリシリコ
ン抵抗１０はボロン（Ｂ）が注入されているポリシリコ
ン２の上面、側面および下面の全ての面が酸素を透過し
ない偏析係数１のシリコン窒化膜１１及び１２によつて
覆われているため、ボロン（Ｂ）の濃度はポリシリコン
２の界面付近でも中央付近の濃度とほぼ同じであり、層
内でほぼ均一となる（図１（Ｂ））。またポリシリコン
２を包み込むシリコン窒化膜１１及び１２のボロン濃度
はポリシリコン２の界面から急減するようにできる。The polysilicon resistor 10 formed by the above steps is a silicon nitride having a segregation coefficient of 1 in which all the upper surface, side surface and lower surface of the polysilicon 2 into which boron (B) is implanted do not transmit oxygen. Since it is covered with the films 11 and 12, the concentration of boron (B) is almost the same in the vicinity of the interface even in the vicinity of the interface of the polysilicon 2 and is almost uniform in the layer (FIG. 1 (B)). ). Further, the boron concentration of the silicon nitride films 11 and 12 enclosing the polysilicon 2 can be sharply reduced from the interface of the polysilicon 2.
【００１５】以上の構成によれば、ボロンをアニール処
理するときにおける酸素の影響によつてポリシリコンの
界面付近のボロン濃度が偏析現象によつて低減するおそ
れを有効に回避することができる。これによりポリシリ
コン抵抗１０の抵抗値を決定するボロンの濃度はイオン
注入時とほぼ同一となり、抵抗の精度が向上される。加
えて複数の抵抗をウエハ内に作り込む場合にも各抵抗の
抵抗値のばらつきが低減するためその抵抗比の精度も一
段と向上する。According to the above structure, it is possible to effectively avoid the risk that the concentration of boron in the vicinity of the polysilicon interface will decrease due to the segregation phenomenon due to the effect of oxygen when boron is annealed. As a result, the boron concentration that determines the resistance value of the polysilicon resistor 10 becomes substantially the same as that at the time of ion implantation, and the accuracy of the resistance is improved. In addition, even when a plurality of resistors are formed in the wafer, the variation in the resistance value of each resistor is reduced, so that the accuracy of the resistance ratio is further improved.
【００１６】なお上述の実施例においては、ポリシリコ
ン２を上方および下方からシリコン窒化膜１１及び１２
によつて包み込んでなるポリシリコン抵抗１０を単独で
生成する生成方法について述べたが、本発明はこれに限
らず、シリコン窒化膜１１又は１２はＭＩＳ（Metal In
sulate Semiconductor）容量を生成する過程において容
量の絶縁膜を形成する際に同時に堆積するようにしても
良い（図３）。In the above embodiment, the polysilicon 2 is formed from above and below the silicon nitride films 11 and 12.
Although the method for independently generating the polysilicon resistor 10 which is wrapped by the above has been described, the present invention is not limited to this, and the silicon nitride film 11 or 12 is not limited to the MIS (Metal In
sulate semiconductor) In the process of generating a capacitance, it may be deposited at the same time when the insulating film of the capacitance is formed (FIG. 3).
【００１７】ここでＭＩＳ容量はアルミニウムの配線５
とエミツタ拡散層１３との間で容量を構成するものであ
り、図３の場合、ポリシリコン抵抗１０を形成するポリ
シリコン２を上方から覆うシリコン窒化膜１２とポリシ
リコン１４を絶縁膜としている。Here, the MIS capacitor is the aluminum wiring 5
And the emitter diffusion layer 13 form a capacitor. In the case of FIG. 3, the silicon nitride film 12 and the polysilicon 14 which cover the polysilicon 2 forming the polysilicon resistor 10 from above are used as insulating films.
【００１８】また上述の実施例においては、抵抗パター
ンにパターニングされたポリシリコン２にボロン（Ｂ）
を抵抗値を決定する不純物として注入する場合について
述べたが、本発明はこれに限らず、ボロン以外の物質を
注入するようにしても良い。Further, in the above-described embodiment, boron (B) is added to the polysilicon 2 patterned into the resistance pattern.
Although the case of implanting as an impurity that determines the resistance value has been described, the present invention is not limited to this, and a substance other than boron may be implanted.
【００１９】さらに上述の実施例においては、アニール
時における酸素のポリシリコン２への透過を遮断する絶
縁層としてシリコン窒化膜を用いる場合について述べた
が、本発明はこれに限らず、ポリシリコンに対して偏析
係数が１であり、かつ酸素を透過しない他の物質を絶縁
膜として用いる場合にも広く適用し得る。Further, in the above-mentioned embodiment, the case where the silicon nitride film is used as the insulating layer for blocking the permeation of oxygen into the polysilicon 2 at the time of annealing has been described, but the present invention is not limited to this, and polysilicon is used. On the other hand, it can be widely applied to the case where another substance having a segregation coefficient of 1 and impermeable to oxygen is used as the insulating film.
【００２０】[0020]
【発明の効果】上述のように本発明によれば、半導体抵
抗を構成するポリシリコンの全面を、酸素を透過せず、
かつポリシリコンに対して偏析係数が１でなる物質の絶
縁膜によつて包む込んだことにより、アニール時に酸素
の影響によつてポリシリコン中の不純物の濃度が不均一
になるおそれを有効に回避することができる。As described above, according to the present invention, oxygen does not pass through the entire surface of the polysilicon forming the semiconductor resistor,
In addition, since the material having a segregation coefficient of 1 with respect to polysilicon is wrapped with an insulating film, it is possible to effectively avoid the possibility that the concentration of impurities in the polysilicon becomes non-uniform due to the influence of oxygen during annealing. can do.
【図１】本発明による半導体抵抗の一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor resistor according to the present invention.
【図２】その生成方法の説明に供する略線図である。FIG. 2 is a schematic diagram for explaining the generation method.
【図３】他の実施例の説明に供する断面図である。FIG. 3 is a cross-sectional view provided for explaining another embodiment.
【図４】従来における半導体抵抗の生成方法の説明に供
する略線図である。FIG. 4 is a schematic diagram for explaining a conventional method of generating a semiconductor resistance.
【図５】半導体抵抗の構造の説明に供する断面図であ
る。FIG. 5 is a sectional view for explaining the structure of a semiconductor resistor.
【図６】従来における半導体抵抗の生成方法の説明に供
する略線図である。FIG. 6 is a schematic diagram for explaining a conventional method of generating a semiconductor resistance.
【図７】半導体抵抗の構造の説明に供する断面図であ
る。FIG. 7 is a sectional view for explaining the structure of a semiconductor resistor.
１……シリコン酸化膜、２、１４……ポリシリコン、３
……レジスト、４……酸化膜、５……配線、６……保護
膜、７、１１、１２……シリコン窒化膜、１０……ポリ
シリコン抵抗、１３……エミツタ拡散層。1 ... Silicon oxide film, 2, 14 ... Polysilicon, 3
...... Resist, 4 ... Oxide film, 5 ... Wiring, 6 ... Protective film, 7, 11, 12 ... Silicon nitride film, 10 ... Polysilicon resistor, 13 ... Emitter diffusion layer.
Claims (3)
つて形成される半導体抵抗において、 上記ポリシリコンの全面が、酸素を透過せず、かつ上記
ポリシリコンに対して偏析係数が１でなる物質の絶縁膜
によつて包まれてなることを特徴とする半導体抵抗。1. A semiconductor resistor formed by introducing impurities into polysilicon, wherein the entire surface of the polysilicon is impermeable to oxygen and has a segregation coefficient of 1 with respect to the polysilicon. A semiconductor resistor characterized by being wrapped with an insulating film of.
包み込み、 その後、アニール工程によつて上記不純物を拡散させる
ことにより半導体抵抗を生成することを特徴とする半導
体抵抗の生成方法。2. After introducing impurities into the polysilicon, the entire surface of the polysilicon is covered with a silicon nitride film, and then the impurities are diffused by an annealing process to generate a semiconductor resistance. A method for producing a semiconductor resistance having a feature.
リコン窒化膜のうち上記ポリシリコンの上面又は底面を
覆うシリコン窒化膜を、金属と半導体によつて絶縁物を
挟むことによつて形成される半導体容量の絶縁物を生成
する際に同時に形成することを特徴とする請求項２に記
載の半導体抵抗の生成方法。3. A semiconductor formed by sandwiching an insulator between a metal and a semiconductor, a silicon nitride film covering the upper surface or the bottom surface of the polysilicon out of the silicon nitride film enclosing the entire surface of the polysilicon. The method for producing a semiconductor resistor according to claim 2, wherein the capacitor is formed at the same time when the capacitor insulator is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12795893A JPH06314770A (en) | 1993-04-30 | 1993-04-30 | Semiconductor resistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12795893A JPH06314770A (en) | 1993-04-30 | 1993-04-30 | Semiconductor resistor and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06314770A true JPH06314770A (en) | 1994-11-08 |
Family
ID=14972871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12795893A Pending JPH06314770A (en) | 1993-04-30 | 1993-04-30 | Semiconductor resistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06314770A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6844228B2 (en) | 2003-06-03 | 2005-01-18 | Renesas Technology Corp. | Manufacturing method of a semiconductor device capable of accurately setting a resistance value of a resistance element |
-
1993
- 1993-04-30 JP JP12795893A patent/JPH06314770A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6844228B2 (en) | 2003-06-03 | 2005-01-18 | Renesas Technology Corp. | Manufacturing method of a semiconductor device capable of accurately setting a resistance value of a resistance element |
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