JPH06310687A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent the breakdown of the antifuse at a low voltage and improve the reliability of the semiconductor device in which it is used. An antifuse of a semiconductor device is provided with an insulating layer 14 formed between a first metal wiring 11 and a second metal wiring 13, and a plurality of connection holes 15 formed in the insulating layer 14.
And an insulating film 17 formed in the connection hole 15 for insulating between the first metal wiring 11 and the second metal wiring 13, and the insulating film 17 is formed by vapor phase growth of the silicon film 17.
a and a laminated film composed of a silicon oxide film 17b and a tantalum oxide film 17c laminated on the silicon film 17a. Thus, by vapor-depositing the silicon film 17a on the metal surface of the first metal wiring 11,
The irregularities on the metal surface are alleviated. Then, by forming a metal oxide film on this, an extremely uniform metal oxide can be formed. For this reason, local overvoltage due to the influence of the unevenness of the metal surface is not applied, and the reliability of the device is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved antifuse suitable for wiring a field programmable gate array which is a field programmable gate array for a user.

[0002]

2. Description of the Related Art A field programmable gate array (hereinafter referred to as "FPGA") is a gate array that can be programmed in the field by a user among the gate arrays. The programming is performed by making a part of the FPGA wiring conductive.

As a method for forming FPGA wiring,
A method of forming a so-called antifuse structure by a connection hole provided with a thin insulating film between metal wirings has been proposed (IEEE Electron Device Let).
ter, Vol. 13, No. 9, September
1992 pp. 488-490). More specifically, the antifuse includes an insulating layer formed between the first metal wiring and the second metal wiring, a connection hole formed in the insulation layer, and the connection hole formed in the connection hole. And an insulating film that insulates between the first metal wiring and the second metal wiring. The antifuse is characterized in that a connection between metal wirings is obtained by applying electricity to cause dielectric breakdown.

The FPGA wiring has a plurality of antifuses as described above, and a desired program can be built by selectively subjecting some of the connection holes to dielectric breakdown. That is, in such an FPGA wiring, the insulation breakdown of the insulating film is performed by selectively applying a voltage to the plurality of connection holes, so that the wiring is electrically connected. On the other hand, in the connection hole in which the dielectric breakdown has not been performed, the wirings in the upper and lower layers are not electrically connected to each other, so that programming can be performed by selectively applying a voltage to the connection hole. Note that the voltage applied for dielectric breakdown of the insulating film is called a program voltage or a write voltage, but is called a write voltage in this specification.

Here, as a method for forming the antifuse structure of the FPGA, there is a method described in, for example, US Pat. No. 5,070,384. This US patent contains
In order to form the antifuse structure as described above, a metal film is formed on the surface of the metal wiring, and the metal oxide film formed by oxidizing the metal film formed on the surface of the metal wiring and the metal oxide film on the oxide film are formed. It describes a method of forming an insulating film from the formed silicon film and forming metal wiring on the insulating film.

[0006]

When an antifuse structure is used as the FPGA wiring, the insulating film in the connection hole must be dielectrically broken down at a predetermined voltage, while the insulating film must be insulated. It is necessary that the breakdown voltage does not cause dielectric breakdown (for example, the voltage generated when the device operates).

However, the above-mentioned conventional insulating film has a problem that it is extremely susceptible to dielectric breakdown due to the influence of the crystal grains on the metal surface adjacent thereto. This is because when the metal oxide film is formed on the metal film, unevenness is generated on the contact surface, so that a high voltage is locally applied. As described above, since the dielectric breakdown is extremely likely to occur due to the influence of the crystal grains on the metal surface, it has been difficult to form a thin insulating film having sufficient insulation resistance with the above-mentioned conventional technique.

This problem becomes more remarkable when the insulating film is thinned in accordance with the present tendency that the operating voltage of the element is gradually lowered. That is, when the operating voltage of the device is lowered, the breakdown voltage of the insulating film of the antifuse needs to be lowered accordingly. In order to reduce the breakdown voltage, it is necessary to reduce the thickness of the insulating film, and the influence of the unevenness on the metal surface increases as the thickness decreases. Therefore, as the operating voltage decreases,
The antifuse is destroyed by the weak operating voltage of the element that is not intended for insulation breakdown, and the reliability of the antifuse is reduced.

The present invention has been made in view of the above problems, and an object thereof is to provide a highly reliable antifuse which is not broken down by a voltage lower than a predetermined voltage, and an FPGA using the same. It is to improve the reliability of the (semiconductor device).

[0010]

In order to solve the above problems, in the present invention, the unevenness is alleviated by vapor-depositing a silicon film on the unevenness of the metal surface, and then the insulating film is formed thereon. It is characterized in that the body is laminated to form an insulating film.

That is, in the present invention, the antifuse insulating film is composed of the vapor-grown silicon film, the silicon oxide film laminated on this silicon film, and the laminated film made of a substance having a high dielectric constant. It is characterized by

More specifically, in the present invention, an insulating layer formed between the first metal wiring and the second metal wiring, a connection hole formed in the insulation layer, and a connection hole formed in the connection hole. In a semiconductor device having a plurality of antifuses formed of an insulating film for insulating between the first metal wiring and the second metal wiring, the insulating film is a vapor-grown silicon film, Silicon oxide laminated on this silicon film and at least Ti, Ta, Nb, Zr, Y, Hf,
And a laminated film made of an oxide of an element selected from Al.

Further, in the above semiconductor device, Ti, Ta, Nb, and
A nitride of an element selected from Zr, Y, and Hf, or T
It is characterized in that an intervening layer made of iB or TiC is interposed.

Further, in any one of the above semiconductor devices, a plurality of the laminated films are laminated in the insulating film.

In such a semiconductor device, the desired first metal wiring and second metal wiring can be formed by short-circuiting the insulating film of a predetermined connection hole among the plurality of connection holes of the semiconductor device. It is possible to establish continuity between them.

[0016]

In the present invention, the amorphous silicon layer is formed on the metal surface to alleviate the irregularities on the metal surface, and the metal oxide film is formed on the silicon layer by vapor phase chemical growth to achieve a very uniform surface. It is possible to form various metal oxides. That is, since the silicon layer is amorphous, it is possible to obtain an extremely smooth surface without crystal grain boundaries peculiar to crystals.

Further, by performing heat treatment in an oxidizing atmosphere after forming the metal oxide, the insulating property of the metal oxide is dramatically improved, and excellent reliability can be obtained. At this time, a silicon oxide layer grows on the interface between the silicon layer and the metal oxide. This oxidation dramatically reduces the defect density.

According to this structure, when the write voltage is applied to the connection hole, the silicon oxide layer and the metal oxide layer are dielectrically broken down, and then the metal silicide is formed by the silicon supplied from the thin silicon layer. A resistance conduction path is formed. Therefore, in the present invention, the electric resistance after dielectric breakdown can be reduced.

Further, by thinning and stacking the silicon layer and the metal oxide layer, the dielectric breakdown can be more surely performed and the low resistance conductive path can be promptly formed.

[0020]

1 is a schematic sectional view of an antifuse of a semiconductor device (FPGA) according to a preferred embodiment of the present invention.

This antifuse has a first metal wiring 1
Insulating layer 14 formed between the first and second metal wirings 13
And a connection hole 15 formed in the insulating layer 14, and an insulating film 17 formed in the connection hole 15 for insulating between the first metal wiring 11 and the second metal wiring 13. There is. Then, the semiconductor device (FPG
A) has a plurality of such antifuses.

A characteristic of this embodiment is that the insulating film 17 includes a silicon film 17a and the silicon film 17a.
a laminated film made of a silicon oxide film 17b and a tantalum oxide film 17c formed on a, and a first intervening layer 18 is formed between the insulating film 17 and the first metal wiring 11. That is, the second intervening layer 19 is formed between 17 and the second metal wiring 13. In the embodiment, both of the two intervening layers are made of titanium nitride. The silicon oxide film 17b is not formed by stacking silicon oxide, but is formed by covering the silicon film 17a with the tantalum oxide film 17c.

The antifuse according to this embodiment is formed as follows (FIG. 2). First, a titanium nitride film (0.1 μm) is formed as a first intervening layer 18 on the first metal wiring 11 made of a 0.8 μm aluminum layer, and an insulating layer 14 (1 0.0 μm)
To form. Then, by patterning and etching, an opening is formed in a predetermined portion of the insulating layer 14. As a result, the connection hole 15 is formed (FIG. 2A).

After the connection hole 15 is formed, monosilane gas is decomposed at a high frequency of 13.56 MHz under a reduced pressure, so that 5 n is formed on the entire insulating layer 14 in which the connection hole 15 is formed.
m amorphous silicon film 17a is deposited. Next, a 30 nm thick tantalum oxide film 17c is formed on the silicon film 17a.
Was formed by pyrolyzing the vapor of ethoxy tantalum alcoholate under a reduced pressure of 1 torr in an oxygen atmosphere. As a result, a silicon oxide film 17b having a thickness of 2 nm is formed at the interface between the silicon film 17a and the tantalum oxide film 17c. The silicon oxide layer 17b is a combination of a film formed of a natural oxide film on the silicon layer and a film formed by being oxidized during the formation of tantalum oxide (FIG. 2).
(B)).

Thereafter, titanium nitride (0.1 μm) and aluminum (0.8 μm) were laminated in this order to form the second intervening layer 19 and the second metal wiring 13. Then, after patterning the second metal wiring 13, a passivation film (not shown) is formed thereon as a protective layer, and external wiring is taken out to form wiring of the field programmable gate array.

FIG. 3 illustrates the first metal wiring 11 and the insulating film 1 in order to explain the effect of the antifuse according to this embodiment.
7 schematically shows the structure of the contact portion of No. 7.

FIG. 3 (a) schematically shows the structure by the conventional method for comparison, and FIG. 3 (b) schematically shows the structure by the method of this embodiment. .

First, in the conventional method, the first metal wiring 1
The metal oxide 22 is directly formed on the unevenness of the surface of No. 1 by oxidation, the silicon layer 23 is formed thereon, and the second metal wiring 13 is formed thereon. In this case,
The metal oxide 22 and the silicon layer 23 function as the insulating film 17. However, the metal oxide formed by oxidizing the metal film is extremely susceptible to dielectric breakdown due to the influence of the unevenness of the crystal grains on the metal surface. Therefore, it is extremely difficult to form a thin insulating film having a sufficient withstand voltage.
When this is used as an antifuse, it is necessary to perform dielectric breakdown at a predetermined voltage, but a voltage lower than the predetermined voltage according to the above technique is likely to cause dielectric breakdown, and there is a problem in reliability.

On the other hand, in the method of this embodiment, the method shown in FIG.
As shown in the schematic cross-sectional structure diagram of (b), a thin silicon layer 25 is first formed on the surface of the metal film 21, and then a silicon oxide 26 / metal oxide 27 laminated film is formed on the silicon layer 25.
The upper metal wiring 28 is formed. As a result, the effect of the unevenness of the crystal grains existing on the metal surface from the beginning is mitigated, and the antifuse becomes less likely to cause dielectric breakdown. That is, since the silicon layer is amorphous, it is possible to obtain an extremely smooth surface without crystal grain boundaries peculiar to crystals. The silicon dioxide layer 26 may be a natural oxide film on the silicon layer 25 or may be intentionally formed. Further, it also contains silicon oxide grown by heat treatment in an oxidizing atmosphere after forming the metal oxide 27.

Next, the semiconductor device (FPG
The specifications of A) will be described.

Two antifuses are shown in FIG. In the figure, the antifuse on the right side determines the connection between the second metal wiring 13 and the first metal wiring 11 on the right side,
On the other hand, the antifuse on the left side is the second metal wiring 1 on the left side.
The connection between 3 and the first metal wiring 11 is determined. The semiconductor device is covered with a passivation film 20 as a protective film.

In FIG. 4A, neither antifuse is dielectrically broken, and therefore neither the left or right wiring is connected. On the other hand, in FIG. 4B, the write voltage is applied to the antifuse on the right side, and this is dielectrically broken down. In the embodiment, the dielectric breakdown is performed by applying a voltage pulse between the first metal wiring 11 and the second metal wiring 13 on the right side. When a voltage pulse is applied, the tantalum oxide film 17c and the silicon oxide film 17b are dielectrically broken down, and the silicon film 17a and the tantalum oxide film 17c.
A conductive path Q made of a metal silicide is formed by mutual diffusion with. Then, the conduction path Q establishes conduction between the first metal wiring 11 and the second metal wiring 13 on the right side. On the other hand, a write voltage is not applied to the left antifuse, and the first metal wiring 11 and the second metal wiring 1 on the left side are not applied.
Between 3 is insulated.

Similarly, by selectively short-circuiting a plurality of antifuses formed on the element, any wiring connection can be made.

FIG. 5 and FIG. 6 are views for evaluating the effect of the semiconductor device according to the present embodiment in comparison with the conventional example.

In the conventional example which is a comparative example, the insulating film 17 is
It is composed of a titanium oxide film formed by oxidizing a titanium film formed on the first metal wiring 11. The thickness of the titanium oxide film is 40 nm. On the other hand, in this embodiment, the film thickness of the silicon oxide film 17b is set to 5 nm in order to make the capacities almost equal.

FIG. 5 shows the applied voltage dependence of the dielectric breakdown histogram. As shown in FIG. 5A, in the case of the titanium oxide / silicon laminated structure, the dielectric breakdown voltage greatly varies due to the influence of surface irregularities. On the other hand, as shown in FIG. 5B, when the structure of the present invention is used, extremely uniform dielectric breakdown characteristics are exhibited.
The result of FIG. 5A shows that in the conventional semiconductor device, when a voltage is applied for a long time during element operation, even an antifuse, which is not intended for dielectric breakdown, may be dielectrically destroyed. , And shows that it is extremely problematic in terms of reliability. However, from the result of FIG. 5B, it is understood that the semiconductor device according to the present embodiment does not have such a concern and the reliability of the device can be made extremely high.

FIG. 6A shows the distribution of the resistance value of the contact hole after the breakage when the titanium oxide film / silicon stack is used. FIG. 6B shows a case where the structure of the present invention is used.
A distribution comparable to the resistance variation during insulation is obtained.

The structure of the present invention is such that the first metal wiring 31 wired to the input or output of the block 30 composed of the logic circuit shown in FIG. 7 and the second metal wiring formed on the input or output thereof. By arranging the program elements having the structure of the present invention in an array between the wirings 32, blocks including various logic circuits can be freely wired. Further, since the logic circuit and the program element can be vertically stacked, an extremely high-density programmable gate array can be formed.

In the present embodiment, the case where the tantalum oxide film is used as the laminated film is shown, but Ti, Ta,
Similar effects can be obtained by using an oxide film of an element selected from Nb, Zr, Y, Hf, and Al as a laminated film. Further, although the amorphous silicon layer is used in the present embodiment, the same effect can be obtained by using a metal silicide film or an amorphous metal silicide instead.
Further, the same effect can be obtained even with a structure in which a silicon / silicon oxide / metal oxide structure is repeatedly laminated. Furthermore, by arranging a material such as titanium nitride, which does not easily react with silicon, on both sides of this structure, it is possible to realize a highly reliable programmable gate array.

Further, in this embodiment, titanium nitride is used as the intervening layer, but the intervening layer is not limited to titanium nitride, and other elements such as Ta, Nb, Zr, Y, and Hf are selected. Nitride, or TiB or Ti
C can be used.

[0041]

According to the present invention, the uniformity of a thin insulating film formed on a metal at the time of dielectric breakdown can be significantly improved. Therefore, the reliability of the antifuse of the field programmable gate array can be dramatically improved, and a highly reliable field programmable gate array can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an antifuse according to a preferred embodiment of the present invention.

FIG. 2 is a schematic cross-sectional structure diagram for explaining a manufacturing process of the antifuse according to the present embodiment.

FIG. 3 is a model diagram showing an effect of the present invention.

FIG. 4 is a schematic cross-sectional structure diagram of an antifuse portion when the structure of the present invention is used as a program element.

FIG. 5 is a diagram showing the applied voltage dependence of the dielectric breakdown frequency of the antifuse of this example and the prior art.

FIG. 6 is a diagram showing resistance variations after dielectric breakdown of the antifuse of this example and the prior art.

FIG. 7 is a conceptual diagram of wiring of a programmable gate array to which this embodiment is applied.

[Explanation of symbols]

 11 First Metal Wiring 13 Second Metal Wiring 14 Insulating Layer 15 Connection Hole 17 Insulating Film 17a Silicon Film 17b Silicon Oxide Film 17c Tantalum Oxide Film 18 First Intervening Layer 19 Second Intervening Layer

Claims (5)

[Claims] 1. An insulating layer formed between a first metal wiring and a second metal wiring, a connection hole formed in the insulating layer, and the first metal wiring formed in the connection hole. In a semiconductor device having a plurality of antifuses composed of an insulating film for insulating between second metal wirings, the insulating film is a vapor-grown silicon film and a silicon oxide layer on the silicon film. And at least Ti, Ta, Nb, Zr, Y, Hf, A laminated on the silicon film.
2. A semiconductor device, comprising: a laminated film made of an oxide of an element selected from l. 2. The semiconductor device according to claim 1, wherein Ti, T is provided between the first metal wiring and the insulating film.
a nitride of an element selected from a, Nb, Zr, Y and Hf,
Alternatively, a semiconductor device is characterized in that an intervening layer made of TiB or TiC is interposed. 3. The semiconductor device according to claim 1, wherein a plurality of the laminated films are laminated in the insulating film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a step of forming an insulating layer on the first metal wiring, and a step of forming a hole in a predetermined portion of the insulating layer by patterning and etching. And forming a connection hole by forming a contact hole, and after forming the connection hole, a monosilane gas is subjected to high-frequency decomposition under reduced pressure to deposit an amorphous silicon film on the entire insulating layer in which the connection hole is formed. And depositing the amorphous silicon film on the entire insulating layer, and then thermally decomposing the metal alcoholate vapor of claim 1 under reduced pressure in an oxygen atmosphere to oxidize the amorphous silicon film on the amorphous silicon film. A step of forming a metal film and a step of forming a pattern of the second metal wiring on the metal oxide film are included, and the silicon oxide film is formed at the interface between the silicon film and the metal oxide film. The method of manufacturing a semiconductor device according to claim. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a first intervening layer on the first metal wiring, and an insulating layer formed on the first intervening layer. And a step of forming a connection hole by forming an opening at a predetermined portion of the insulating layer by patterning and etching, and after forming the connection hole, high-frequency decomposition of monosilane gas under reduced pressure is performed. The step of depositing an amorphous silicon film on the entire insulating layer in which the connection hole is formed, and the step of depositing the amorphous silicon film on the entire insulating layer, and then vaporizing the metal alcoholate vapor in an oxygen atmosphere. A step of forming a metal oxide film on the amorphous silicon film by thermal decomposition in a vacuum atmosphere, and a step of forming a second metal wiring pattern on the metal oxide film; The method of manufacturing a semiconductor device characterized by a silicon oxide film at the interface of the metal oxide film is formed with.