JPH06310725A - Semiconductor device and fabrication thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide an IGBT capable of improving the short-circuit withstand capability without lowering the saturation voltage. [Structure] Under the interlayer insulating film 32, p + diffusion layer 22, n +
Type emitter region 23 and polycrystalline silicon gate electrode 41
A Ti layer 53 is formed corresponding to. The Ti layer 53 corresponding to the p + diffusion layer 22 and the emitter region 23 constitutes an emitter auxiliary electrode layer, and is composed of two layers of an unreacted pure Ti layer 53a and a titanium silicide layer 53b. Titanium silicide layer 53
Due to b, good ohmic contact is obtained between the p + diffusion layer 22 and the emitter region 23 and the emitter electrode 51. Ti is a high melting point metal and has low resistance and uniformity.
Since the emitter bypass ratio becomes 100%, the saturation voltage decreases, and the current flows evenly when the load is short-circuited, so there is no weak point and the short-circuit withstand capability improves. The Ti layer 53 corresponding to the gate electrode 41 is composed of two layers, an unreacted pure Ti layer 53a and a titanium polycide layer 53c, and serves to reduce the resistance of the gate electrode 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor, power M, having a double diffusion structure, for example.
The present invention relates to a semiconductor device such as an OSFET and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 4A shows, for example, an insulated gate bipolar transistor (hereinafter, referred to as a conventional semiconductor device).
(Referred to as "IGBT"). In the figure, 11 is a p + type single crystal silicon substrate, 12 is an n + type single crystal silicon epitaxial layer, and 13 is an n− type single crystal silicon epitaxial layer. Further, 21 is a p-type base region, 22 is a p + type hole bypass layer (hereinafter, referred to as "p +
A diffusion layer ") and 23 are n + type emitter regions.
Further, 31 is a gate oxide film, 41 is a polycrystalline silicon gate electrode, 32 is an interlayer insulating film, 51 is an emitter electrode, 5
2 is a collector electrode. FIG. 4B is a plan view of the IGBT before forming the emitter electrode 51.

FIG. 5 is a sectional view of steps showing a method of manufacturing an IGBT. 5, parts corresponding to those in FIG. 3 are designated by the same reference numerals. First, as shown in FIG. 5A, an n + type single crystal silicon epitaxial layer 12 and an n − type single crystal silicon epitaxial layer 13 are continuously formed on the entire surface of a p + type single crystal silicon substrate 11 by an epitaxial growth method. Form. Then normal DMOS
The gate oxide film 31, the polycrystalline silicon gate electrode 41, the p-type base region 21, and the p + diffusion layer 22 are formed in the same manner as in manufacturing.

Next, as shown in FIG. 5B, a high concentration n-type impurity is implanted by an ion implantation method using the photoresist 61 as a mask. The implanted n-type impurities form the n + -type emitter region 23 and are also implanted into the polycrystalline silicon gate electrode 41, thereby also fulfilling the role of reducing the electric resistance thereof. Next, FIG.
As shown in (c), an interlayer insulating film 32 is deposited on the polycrystalline silicon gate electrode 41, and a contact opening is provided by using a photolithography technique and an etching technique. Finally, Figure 4
As shown in (a), an emitter electrode 51 and a collector electrode 52 are provided to manufacture an IGBT.

[0005]

Since the conventional IGBT is constructed as described above, it has the following problems. That is, as can be seen from FIG. 4B, the conventional I
In the GBT, the n + type emitter region 23 is formed, and then the contact opening of the interlayer insulating film 32 is provided. Therefore, in order for the emitter region 51 and the n + type emitter region 23 to come in contact with each other, the n + type emitter region is protruded from the contact opening. The emitter region 23 must be formed, and the width L4 of the n + type emitter region 23
Becomes relatively large, and the pinch resistance Rb immediately below the n + type emitter region 23 becomes large.

Considering the operation of the IGBT, a current also flows just below the n + type emitter region 23, so that a voltage difference is generated between the n + type emitter region 23 and the p type base region 21. This is not a problem in normal use, but when the load is short-circuited, a large current flows through the entire IGBT, and the pinch resistor Rb causes a large voltage difference between the n + type emitter region 23 and the p type base region 21. Occurs, and these two regions 23 and 21 and the n − type single crystal silicon epitaxial layer 1
The NPN transistor composed of 3 and 3 is turned on, and as a result, the NPNP thyristor composed of the NPN transistor and the p + -type single crystal silicon substrate 11 is latched up, and the control by the gate voltage becomes impossible, so that it is turned on. Will remain.

As described above, when the load is short-circuited, a large current flows between the collector electrode 52 and the emitter electrode 51 with a high voltage difference, the NPNP thyristor latches up, and a large current continues to flow, and the element is destroyed. That is, the smaller the pinch resistance Rb, in other words, the smaller the width L4 of the n + type emitter region 23, the more difficult it is to latch up, and the time until the device is destroyed when the load is short-circuited (hereinafter referred to as "short-circuit withstand amount").
Becomes longer. However, in the conventional IGBT, since the width L4 of the n + type emitter region 23 is relatively large as described above, the short circuit withstand capability becomes short.

Therefore, conventionally, in order to increase the short circuit withstand capability,
Improved IG in which the width of the n + type emitter region 23 is reduced
BT has been proposed. 6A and 6B are plan views of the improved IGBT before the formation of the emitter electrode 51. In the example of FIG. 6A, the width L5 of the n + -type emitter region 23 is reduced, and the protrusion 23a is formed in a pattern so as to contact the emitter electrode 51. Further, in the example of FIG. 6B, the width L6 of the n + -type emitter region 23 is reduced, and the emitter electrode 5 is formed by the ladder-shaped portion 23b.
The pattern is formed so as to come into contact with 1.

In the example of FIGS. 6A and 6B, the widths L5 and L
In No. 6, it is possible to reduce the overlay precision limit of mask alignment, the photoresist patterning limit, and the oxide film etching process limit to the combined dimensions. However, even this improved IGBT has the following problems. That is, as shown in FIG. 7A, the repeating lengths of the ladder-shaped n + type emitter regions 23 are Ln and Lp, respectively, and the emitter bypass ratio is L.
It is assumed that n / (Ln + Lp). FIG. 7B shows the relationship between the emitter bypass ratio, the short-circuit tolerance (illustrated by the solid line a), and the saturation voltage when the IGBT is on (illustrated by the broken line b). There is a trade-off relationship between saturation voltage and short-circuit withstand capability,
Increasing the emitter bypass ratio lowers the saturation voltage, which is advantageous, but the short-circuit withstand capability deteriorates. This means that the emitter bypass lowers the short-circuit tolerance, that is, the emitter bypass portion is weak.

The present invention has been made to solve the above problems, and provides an IGBT, a power MOSFET, and a method of manufacturing the same having a double diffusion structure capable of improving the short-circuit resistance without lowering the saturation voltage. The purpose is to

[0011]

A semiconductor device according to the invention of claim 1 uses at least a refractory metal between the emitter electrode and the base region, the hole bypass region, and between the emitter electrode and the emitter region. And an emitter auxiliary electrode layer having a silicide layer is formed, the emitter region is electrically connected to the emitter electrode through the emitter auxiliary electrode layer, and the base region or the hole bypass region is electrically connected to the emitter electrode. Connected to each other.

A semiconductor device according to the invention of claim 2 is
A source auxiliary electrode layer formed of at least a refractory metal and having a silicide layer is provided between the source electrode and the base region, the hole bypass region, and between the source electrode and the source region. The source region is electrically connected to the source electrode via the electrode layer, and the base region or the hole bypass region is electrically connected to the source electrode.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which includes a step of forming a polycrystalline silicon electrode layer to be a gate electrode, a step of forming a first conductivity type base region, and a first step. Forming a conductive type hole bypass region, depositing an emitter auxiliary electrode layer formed by using at least a refractory metal layer on the entire surface, and patterning the emitter auxiliary electrode layer using a photoresist as a mask. And a step of implanting impurities into the base region and the hole bypass region using the photoresist as a mask to form a second conductivity type emitter region by a self-aligning method, and activating the impurities by annealing, and
It includes a step of forming a silicide layer or a polycide layer on the emitter auxiliary electrode layer and a step of depositing an interlayer insulating film.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a polycrystalline silicon electrode layer to be a gate electrode, a step of forming a first conductivity type base region, and a first step. Forming a conductive type hole bypass region, depositing a source auxiliary electrode layer formed by using at least a refractory metal layer on the entire surface, and patterning the source auxiliary electrode layer using a photoresist as a mask. And a step of implanting impurities into the base region and the hole bypass region by using the photoresist as a mask to form the second conductivity type source region by the self-alignment method, and activating the impurities by annealing and It includes a step of forming a silicide layer or a polycide layer on the auxiliary electrode layer and a step of depositing an interlayer insulating film.

[0015]

According to the first aspect of the present invention, a low melting point and uniform refractory metal is used between the emitter electrode and the base region, the hole bypass region and between the emitter electrode and the emitter region. Since the emitter auxiliary electrode layer including the silicide layer is provided, good ohmic contact can be obtained between the hole bypass region and the emitter region and the emitter electrode. Since the emitter bypass ratio becomes 100%, the saturation voltage decreases. Even if the load is short-circuited, the current flows evenly, so there are no weak points and the short-circuit withstand capability is improved.

According to the second aspect of the present invention, a uniform refractory metal having low resistance is used between the source electrode and the base region, the hole bypass region, and between the source electrode and the source region. Since the source auxiliary electrode layer having the silicide layer is provided, good ohmic contact can be obtained between the hole bypass region and the source region and the source electrode. Since the source bypass rate becomes 100%, the saturation voltage decreases. Even if the load is short-circuited, the current flows evenly, so there are no weak points and the short-circuit withstand capability is improved.

According to the third aspect of the present invention, since the emitter region is formed by the self-alignment method, its width can be made as small as possible without being affected by the size of the contact opening, and the chip size can be reduced. Is possible.

According to the fourth aspect of the invention, since the source region is formed by the self-aligning method, its width can be made as small as possible without being affected by the size of the contact opening, and the chip size can be reduced. Is possible.

[0019]

EXAMPLES Example 1. An embodiment of a semiconductor device according to the present invention will be described below with reference to FIG.
The case of application to T will be described as an example. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, 53 is the interlayer insulating film 32.
Underneath the T + layer formed corresponding to the p + diffusion layer 22, the n + type emitter region 23 and the polycrystalline silicon gate electrode 41.
i (titanium) layer.

P + diffusion layer 22 and n + type emitter region 2
The Ti layer 53 formed corresponding to No. 3 constitutes an emitter auxiliary electrode layer. The Ti layer 53 is composed of two layers, an unreacted pure Ti layer 53a and a titanium silicide layer 53b generated by reacting with silicon. The Ti layer 53 has a function of electrically connecting the p + diffusion layer 22 and the n + type emitter region 23 to the emitter electrode 51. In this case, the titanium silicide layer 53b causes p +
Good ohmic contact can be obtained between the diffusion layer 22 and the n + -type emitter region 23 and the emitter electrode 51.

The Ti layer 53 formed so as to correspond to the polycrystalline silicon gate electrode 41 includes an unreacted pure Ti layer 53a,
It is composed of two layers of a titanium polycide layer 53c generated by reacting with polycrystalline silicon. The Ti layer 53 serves to reduce the resistance of the gate electrode 41.

2 and 3 are process sectional views showing a method of manufacturing the IGBT of the example of FIG. First, as shown in FIG. 2A, in the same manner as in the conventional IGBT manufacturing method,
Gate oxide film 31, polycrystalline silicon gate electrode 41, p
A mold base region 21 and a p + diffusion layer 22 are formed. next,
As shown in FIG. 2B, a Ti layer 53 is formed on the entire surface by 2000.
It is formed to a thickness of angstrom by a sputtering method. Next, as shown in FIG. 2C, using the photoresist 61 as a mask, the Ti layer 53 is etched with an etching solution mainly containing hydrogen peroxide solution, and the photoresist 61 is directly used.
Is used as a mask to expose the As
(Arsenic) is implanted at an acceleration voltage of 50 KeV and an implantation amount of 5 × 10 15 ions / cm 2.

Next, as shown in FIG. 3A, the photoresist 61 is entirely removed, and annealing is performed at 900 ° C. for 30 seconds in an inert gas by a lamp heating type annealing device. At this time, the As implanted into the silicon is activated to form the n + type emitter region 23. At the same time, the Ti layer 5 is formed on the p + diffusion layer 22 and the n + type emitter region 23.
3, the titanium silicide layer 53b is generated, and good ohmic contact is obtained. Further, the titanium polycide layer 53c is generated from the Ti layer 53 on the polycrystalline silicon gate electrode 41, and the unreacted Ti layer 53a and the titanium polycide layer 53c reduce the resistance of the polycrystalline silicon gate electrode 41.

Next, as shown in FIG. 3B, an inter-layer insulating film 32 is deposited on the entire surface, and contact openings are formed by using photolithography and etching techniques. Finally, as shown in FIG. 1, the emitter electrode 51 and the collector electrode 52 are provided to manufacture the IGBT of the embodiment. Since the Ti layer 53 and the n + type emitter region 23 can be formed by the self-alignment method, the width L1 of the n + type emitter region 23 should be made as small as possible without being affected by the size of the contact opening. As a result, the chip size can be reduced.

Example 2. Although the Ti layer 53 is formed in the above-described embodiment, a layer of another refractory metal that can easily make ohmic contact with silicon may be formed. It is also possible to use an alloy composed of two or more kinds of metals such as a Ti-W (tungsten) layer. The layer thickness and annealing conditions differ depending on the type of refractory metal, and the optimum conditions can be selected for each.
The annealing temperature may be 0 angstrom or more, the annealing temperature may be 800 ° C. or more, and the annealing time may be 30 seconds or more.

Example 3. Further, in the above-mentioned embodiment, the case of the two-layer structure of titanium silicide / pure Ti using the Ti layer 53 is shown, but a structure of three layers or more such as titanium silicide / pure Ti / titanium nitride is also possible. . As a manufacturing method thereof, if annealing is performed in a nitrogen atmosphere or an atmosphere mainly containing ammonia gas at the time of annealing, it is easy to obtain 3
A layered structure can be obtained. Note that titanium nitride also has an effect as a barrier metal.

Example 4. Further, although the present invention is applied to the IGBT in the above-described embodiments, it can be applied to the power MOSFET having the double diffusion structure in the same manner, and the same effect can be obtained. In addition, power MOSFET
Has a structure excluding the layer of the p + -type single crystal silicon substrate 11 of the example of FIG. However,
In the example of FIG. 1, the portions related to the emitter and the collector are the portions related to the source and the drain, respectively.

[0028]

According to the invention of claim 1, at least a refractory metal is used between the emitter electrode and the base region, the hole bypass region and between the emitter electrode and the emitter region. An emitter auxiliary electrode layer having a silicide layer is provided, the emitter region is electrically connected to the emitter electrode through the emitter auxiliary electrode layer, and the base region or the hole bypass region is electrically connected to the emitter electrode. With the silicide layer, good ohmic contact can be obtained between the hole bypass region and the emitter region and the emitter electrode.
The refractory metal has low resistance and is uniform. Since the emitter bypass ratio becomes 100%, the saturation voltage can be lowered, and even if the load is short-circuited, the current flows uniformly, so that there are no weak points and the short-circuit withstand capability is improved.

According to the second aspect of the invention, at least a refractory metal is used between the source electrode and the base region, the hole bypass region and between the source electrode and the source region, and the silicide layer is formed. A source auxiliary electrode layer having a is provided, the source region is electrically connected to the source electrode through the source auxiliary electrode layer, and the base region or the hole bypass region is electrically connected to the source electrode. The silicide layer provides good ohmic contact between the hole bypass region and the source region and the source electrode, and the refractory metal has low resistance and is uniform. Since the source bypass rate becomes 100%, the saturation voltage can be reduced, and even if the load is short-circuited, the current flows evenly, so that there are no weak points and the short-circuit withstand capability is improved.

According to the third aspect of the present invention, the step of forming a polycrystalline silicon electrode layer to be a gate electrode, the step of forming a first conductivity type base region, and the first conductivity type hole. A step of forming a bypass region, a step of depositing an emitter auxiliary electrode layer formed using at least a refractory metal layer on the entire surface, a step of patterning the emitter auxiliary electrode layer using a photoresist as a mask, A step of injecting impurities into the base region and the hole bypass region by using the resist as a mask to form a second conductivity type emitter region by a self-aligning method, and activating the impurities by annealing and forming a silicide on the emitter auxiliary electrode layer. The step of forming a layer or a polycide layer and the step of depositing an interlayer insulating film are sequentially performed, and the emitter region is self-aligned. To form the down method, the width can be reduced as much as possible without being influenced size of the contact hole, the effect of such possible reduction of the chip size.

According to the invention of claim 4, a step of forming a polycrystalline silicon electrode layer to be a gate electrode, a step of forming a base region which is a first conductor, and a step of forming a first conductivity type A step of forming a hole bypass region, a step of depositing a source auxiliary electrode layer formed using at least a refractory metal layer on the entire surface, a step of patterning the source auxiliary electrode layer using a photoresist as a mask, A step of implanting impurities into the base region and the hole bypass region by using the photoresist as a mask to form a second conductivity type source region by a self-aligning method, and activating the impurities by annealing and forming a source auxiliary electrode layer on the source auxiliary electrode layer. A step of forming a silicide layer or a polycide layer and a step of depositing an interlayer insulating film are sequentially performed, and the source region is self-aligned. Therefore in order to form, the width can be reduced as much as possible without being influenced size of the contact hole, the effect of such possible reduction of the chip size.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process sectional view of the first half showing an embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a second-half process sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view and a plan view showing a conventional semiconductor device.

5A to 5C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a plan view showing a conventional improved semiconductor device.

FIG. 7 is a diagram showing a relationship between an emitter bypass ratio, a saturation voltage, and a short-circuit withstand amount for explaining problems of the conventional improved semiconductor device.

[Explanation of symbols]

 11 P + type single crystal silicon substrate 12 n + type single crystal silicon epitaxial layer 13 n− type single crystal silicon epitaxial layer 21 p type base region 22 p + type hole bypass layer (p + diffusion layer) 23 n + type emitter region 31 gate oxide film 32 interlayer insulating film 41 polycrystalline silicon gate electrode 51 emitter electrode 52 collector electrode 53 Ti layer 53a pure Ti layer 53b titanium silicide layer 53c titanium polycide layer 61 photoresist

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[Procedure amendment]

[Submission date] September 9, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

Example 2. Although the Ti layer 53 is formed in the above-described embodiment, a layer of another refractory metal that can easily make ohmic contact with silicon may be formed. It is also possible to use an alloy composed of two or more kinds of metals such as a Ti-W (tungsten) layer. Layer thickness, annealing conditions differs depending on the kind of the refractory metal, have good if you choose optimal conditions, respectively.

Claims (4)

[Claims] 1. An emitter auxiliary electrode formed by using at least a refractory metal and having a silicide layer between the emitter electrode and the base region, the hole bypass region, and between the emitter electrode and the emitter region. A layer is provided, and the emitter region is electrically connected to the emitter electrode through the emitter auxiliary electrode layer, and the base region or the hole bypass region is electrically connected to the emitter electrode. . 2. A source auxiliary electrode formed of at least a refractory metal and having a silicide layer between the source electrode and the base region, the hole bypass region, and between the source electrode and the source region. A semiconductor layer, a layer is provided, and the source region is electrically connected to the source electrode through the source auxiliary electrode layer, and the base region or the hole bypass region is electrically connected to the source electrode. . 3. A step of forming a polycrystalline silicon electrode layer to be a gate electrode, a step of forming a first conductivity type base region, a step of forming a first conductivity type hole bypass region, and an entire surface. A step of depositing an emitter auxiliary electrode layer formed by using at least a refractory metal layer, a step of patterning the emitter auxiliary electrode layer with a photoresist as a mask, and a step of patterning the base with the photoresist as a mask. A step of implanting an impurity into the region and the hole bypass region to form a second conductivity type emitter region by a self-aligning method, and activating the impurity by annealing, and forming a silicide layer or a polycide layer on the emitter auxiliary electrode layer. And a step of depositing an interlayer insulating film, the method for manufacturing a semiconductor device. 4. A step of forming a polycrystalline silicon electrode layer to be a gate electrode, a step of forming a first conductivity type base region, a step of forming a first conductivity type hole bypass region, and an entire surface. A step of depositing a source auxiliary electrode layer formed by using at least a refractory metal layer, a step of patterning the source auxiliary electrode layer with a photoresist as a mask, and a step of patterning the base with the photoresist as a mask. A step of implanting an impurity into the region and the hole bypass region to form a source region of the second conductivity type by a self-alignment method, and activating the impurity by annealing, and also forming a silicide layer or a polycide layer on the source auxiliary electrode layer. And a step of depositing an interlayer insulating film, the method for manufacturing a semiconductor device.