JPH06326587A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a MOS transistor in a MOS integrated circuit at the time of a low temperature operation and to prevent the slowing down of operation speed at high temperature operation time by obtaining reference potential having a positive temperature coefficient based on the difference of the temperature coefficients of diodes characteristic elements which mutually differ and outputting internal voltage proportional to the reference potential. CONSTITUTION:In circuits provided with the diode characteristic elements P1, P2, Pa, Pb and Pc, and P3, P4, Na, Nb and P5, which mutually differ, positive reference potential VREF is obtained based on the difference of the temperature coefficient, and internal voltage proportional to potential VREF is outputted. The deterioration of the MOS transistor TR in the MOS integrated circuit owing to a hot carrier can be prevented. At the time of a regular temperature and high temperature operation, the deterioration of the speed of MOSTR, which occurs a the time of the normal temperature and high temperature operation, can be compensated by outputting high internal voltage corresponding to the temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with an internal power supply generation circuit which is supplied with an external power supply and supplies a constant voltage to an internal circuit in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices (hereinafter referred to as LSI
The problem of deterioration due to hot carriers has arisen in the MOS transistors that form the LSI as a result of the miniaturization. In order to overcome this problem and ensure its reliability,
It has become necessary to adopt a power supply voltage lower than the power supply voltage of 5V used so far. However, there is a strong demand from the system side to keep the power supply voltage at 5V, which is 5V.
The number of cases where the voltage of the external power supply is dropped inside the LSI and used is increasing. Conventionally, in this type of LSI, the voltage of the internal power supply output from an internal power supply generation circuit (hereinafter, referred to as an internal voltage down converter) for stepping down the voltage of the external power supply is a constant voltage having no temperature dependency, for example, 4V. Is.

A conventional internal step-down circuit is shown in FIG. P1
5 is a P-channel MOS transistor, Ia and Ib are constant current sources, F1 is a negative feedback amplifier circuit, R1 and R2 are resistors, and T
1 represents a constant voltage circuit, respectively. The current value of the first constant current source Ia of the constant voltage circuit T1 is set to 2 of the current value of the second constant current source Ib.
It is set to double, for example, Ia is 2 μA, Ib
By selecting 1 μA as, I2 and I3 are respectively set to 1 μA. The threshold voltage (VTP high) of the first P-channel transistor set P1 and P2 connected in series with each other is set to a high value (absolute value) at the time of manufacturing, and for example, | VTP high | = 1.5V. Is set.

The threshold voltage V of the second P-channel transistor set P3, P4 connected in series with each other.
TP is a normal value at the time of manufacture, for example | VTP | = 0.8
V and the threshold voltage | VTP high | of the first P-channel transistor set P1 and P4 are set lower. First and second P-channel transistor sets P1 to P4
Since it is necessary to accurately output a predetermined constant voltage in combination with a constant current source, set the gate and drain to the same potential,
In addition, the source and the bulk have the same potential structure so that the constant voltage does not change due to the influence of the variation in the potential difference between the bulk potential and the source potential.

That is, each of the P-channel transistor sets P1 and P2, P3 and P4 functions as a first and second diode characteristic element which gives a predetermined forward voltage. A node where the cathode of the second diode characteristic element outputs the reference potential VREF by maintaining the cathode of the first diode characteristic element at the GND potential and commonly connecting the anodes of the first and second diode characteristic elements. Configured as B.

Each P-channel transistor P1 to P4 is
When the gate-source voltage V _GS (equal to the drain-source voltage V _DS ) is 5 V, the on-current is set to a current value of, for example, several mA to tens of mA, and the current is actually applied in the circuit. The current value is sufficiently larger than the current value. By adopting this configuration, the potential of the node A forming the output of the first P-channel transistor set P1 and P2 is 1 μm.
A forward voltage as a diode characteristic element is formed by a combination of a constant current source Ia having a current capacity of A and a P-channel transistor set P1 and P2 having a diode function,
2 | VTP high |, which is the amount of increase of the P-channel transistors P1 and P2, becomes exactly 3V.

Due to the combination of the constant current source Ib and the second P-channel transistor set P3, P4, the reference potential VREF at the node B rises from the potential of the node A to the threshold voltage of the P-channel transistor set P3, P4. Potential minus 3 minutes (forward voltage), 3V-2x
It becomes 0.8V = 1.4V. That is, the reference potential at the node B is 2 (| VTP high |-| VTP |), and the threshold voltage is a normal value from the threshold voltage of the first P-channel transistor set P1 and P2 having a high threshold voltage. Is set to twice the difference between the threshold voltages of the second P-channel transistor sets P3 and P4.

FIG. 6 is a graph showing the temperature dependence of the threshold voltages | VTP high | and | VTP | of both transistor sets. As shown in FIG.
The temperature coefficient of the threshold voltage of the MOS transistor is about 2 mV / ° C., and both threshold voltages | VTP high | and | VTP | decrease as the temperature rises, and the shift amount with respect to temperature is almost the same. Therefore, the reference potential VREF, which is determined by the difference between the threshold voltages of the two transistor groups, has no temperature dependence. In FIG. 5, this reference potential VREF
Is amplified (R1 + R2) / R2 times by the negative feedback amplifier F1 and output as the internal voltage VINT.

The circuit shown in FIG. 7 shows another conventional circuit. The constant voltage circuit T1 is the constant voltage circuit T shown in FIG.
Same as 1. In general, an LSI requires a burn-in test in which stress is applied for a predetermined time under a predetermined high voltage and a high temperature in order to eliminate an initial failure defect. Therefore, the internal voltage down converter may output a constant voltage when the LSI is operating, and may output an internal voltage corresponding to a change in the external voltage when the external voltage becomes equal to or higher than a predetermined voltage during burn-in. desirable. The circuit shown in FIG. 7 is an example of an internal step-down circuit having such an output voltage.

The comparator C1 compares the reference voltage VR (the same voltage value as the internal voltage VINT) with the potential of the node B divided by the resistors R5 and R6, and the node B depending on the external voltage has the reference voltage VR. When the potential becomes higher, the inverter INV1 is inverted and the negative feedback amplifier F3
To be activated. The negative feedback amplifier F3 is configured as a voltage follower, and when it is in an active state, the power supply voltage changes the internal voltage VINT to the resistances R3 and R3.
The potential of the node C divided by 4 is tracked and changed.

The partial pressures of the above resistances are calculated by (R5 + R6): R6
= 6.5: 4 and (R3 + R4): R4 = 5: 4, respectively. With this setting, when the external voltage reaches 6.5 V, the comparator C1 inverts the inverter INV1 in comparison with the reference voltage VR (4 V). Therefore, when the external voltage is 6.5 V or higher, the voltage follower F3 replaces the internal voltage VIN instead of the voltage follower F2.
Determine T.

FIG. 8 shows the relationship between the internal voltage and the external voltage in the circuit configuration of FIG. As shown in FIG. 8, the output voltage VINT of the internal step-down circuit has an external voltage of 4V to VB.
When T, the predetermined constant voltage is 4V and the external voltage is VB.
When T or more, it becomes 4/5 of the external voltage and follows the external voltage.

The reason why the internal voltage is set to 4/5 of the external voltage when the external voltage is VBT or higher is that the internal voltage generating circuit and the internal circuit of the semiconductor integrated circuit operate at 5V and 4V in normal times, respectively. This is because the voltage stress is applied to both of them in the burn-in test at the same voltage ratio as in the normal time. Further, it is desirable that the voltage VBT has a sufficient margin for both the external power supply voltage (5V ± 0.5V) during the normal operation and the external power supply voltage (for example, 7.5V) during the burn-in test. As described above, it is set to 6.5 V which is an intermediate value between the upper limit of 5.5 V of the external power supply voltage during the normal operation and the external power supply voltage of 7.5 V during the burn-in test.

[0014]

In the conventional LSI, if the internal voltage output from the internal step-down circuit is set to be suitable for the operation of the MOS transistor at room temperature, the deterioration of the MOS transistor of the internal circuit is accelerated during low temperature operation. There is a drawback that. This is because when the MOS transistors are operated at the same drain voltage, the stress applied to the MOS transistors due to hot carriers during the low temperature operation is substantially higher than that during the room temperature operation and the high temperature operation.

Therefore, in the conventional LSI, the internal voltage is set to a low voltage determined by the hot carrier withstand capability of the MOS transistor during low temperature operation. However, if such a low voltage is adopted, L
A new problem arises that the operation speed of SI becomes slow.

It is an object of the present invention to provide a semiconductor integrated circuit device which prevents deterioration of a MOS transistor due to hot carriers during low temperature operation and compensates for a decrease in operating speed of the MOS transistor during normal temperature and high temperature operations. is there.

[0017]

To achieve the above object, a semiconductor integrated circuit device according to the present invention includes an internal power supply generation circuit for generating an internal power supply having a predetermined internal voltage when an external power supply is supplied, and a predetermined power supply. In a semiconductor integrated circuit device having an internal circuit having a function and being supplied with the internal power,
The internal voltage has a positive temperature coefficient with respect to temperature changes.

In the internal power generation circuit, a reference potential having a positive temperature coefficient is obtained based on the difference between the temperature coefficients of different diode characteristic elements, and an internal voltage proportional to the reference potential is output. Since the required positive temperature coefficient is easily obtained, the structure of the internal power supply generation circuit is simplified.

The semiconductor integrated circuit has a second internal power supply generation circuit whose output voltage depends on an external voltage and has no temperature coefficient, and output selection means for selecting one of the outputs of both internal power supply generation circuits. Further, if a configuration is adopted in which the output selection means selects the output of the second internal power supply generation circuit when the power supply voltage is equal to or higher than a predetermined value, a voltage that can be applied during both normal operation and burn-in test An internal voltage having a value is obtained.

[0020]

Since the internal voltage output from the internal power supply generation circuit changes with a positive temperature coefficient with respect to the temperature change, by outputting a low internal voltage when the operating temperature of the semiconductor integrated circuit device is low, While operating the MOS transistor at a low voltage that is less likely to be deteriorated by hot carriers, when the operating temperature is high, by outputting a high internal voltage, the MOS transistor in the internal circuit can be operated at a high voltage under a high voltage. To compensate for the speed loss that occurs at normal and high temperatures.

[0021]

The present invention will be further described with reference to the drawings. FIG. 1 shows the configuration of an internal step-down circuit which constitutes an internal voltage generation circuit in an LSI according to the first embodiment of the present invention. This internal step-down circuit includes a constant voltage circuit T1, P-channel MOS transistors P1, P2, Pa, Pb, Pc, and P5, constant current sources Ia and Ib, a negative feedback amplifier circuit F1, and a resistor R.
1a and R2a. In addition, as for these reference numerals, similar reference numerals are used for similar elements in the following embodiments.

In the circuit of the embodiment shown in FIG. 1, in the constant voltage circuit T1, the constant current source Ia and the P channel MOS transistor groups P1 and P2 are used to make the P channel transistor P1.
Of the constant current source Ib and the P-channel MOS transistor group Pa, Pb, P
With the forward voltage drop determined by c, the reference potential VREF is obtained at the drain of the P-channel transistor Pc. Based on this reference potential VREF, the negative feedback amplifier F1
An internal voltage VINT forming a constant voltage is generated. Internal voltage V
INT is supplied to the internal circuit L1.

The circuit of FIG. 1 differs from the conventional circuit in that the conventional circuit has a reference potential of 2 (| VTP high |-| VT
P |), the reference potential is 2 in the circuit of the embodiment.
(| VTP high | -3 | VTP |). That is, in the circuit of this embodiment, the number of transistors P1 and P2 having a high threshold voltage (| VTP high | = 1.5 V) is 2, and the number of transistors Pa, Pb, and Pc having a normal threshold voltage is 3. Is.

Therefore, in the circuit of the above embodiment, the reference potential FREF, and therefore the internal voltage VINT forming the output voltage.
Has a temperature coefficient of one transistor having a normal threshold voltage. In this case, if the reference potential VREF is too low, the operation characteristics of the negative feedback amplifier F1 are deteriorated. Therefore, the threshold voltage | VTP | of the transistors Pa, Pb, and Pc having the normal threshold voltage is set to 0, for example. Set to 0.55 V at ° C. As a result, the reference potential VREF at 0 ° C. is 2 × 1.5.
It can be set to 0−3 × 0.55 = 1.35V.

To set the internal voltage to 4V at 0 ° C.
R1a and R2a are set so that 4 / 1.35 = (R1a + R2a) / R2a. Generally, the temperature coefficient of the threshold voltage of the PMOS transistor is about -2 m.
Since it is V / ° C., the threshold voltage changes by about −0.2 V when the temperature changes from 0 ° C. to 100 ° C. 0
Since the reference potential at 100 ° C. is 1.35V, the reference potential at 100 ° C. is 2 × 1.30−3 × 0.35 = 1.55V.

(R1a + R2a) /R2a=4/1.3
From 5, the internal voltage, which is 4V when the operating temperature is 0 ° C, is
At operating temperature of 100 ° C, approx. 1.55V x (R1a
+ R2a) /R2a=4.59V. Therefore, in this embodiment, the operating temperature of 0 ° C. to 10 ° C., which occurs in the conventional LSI having an internal step-down circuit having no temperature dependence, is used.
It is possible to compensate for an operating speed delay of about 1.15 which is a temperature coefficient of operating speed up to 0 ° C. For example, in a conventional LSI having a MOS transistor having an operating speed of 20 ns at an operating temperature of 0 ° C. and an operating speed of 23 ns at an operating temperature of 100 ° C., the delay of about 3 ns can be compensated. Therefore, with the configuration of the above-described embodiment, it is possible to obtain substantially the same operating speed when the operating temperature is 0 ° C. and when it is 100 ° C. FIG. 2 shows the configuration of the internal step-down circuit of the LSI according to the second embodiment of the present invention. The difference from the embodiment of FIG. 1 is that a MOS transistor having a high threshold voltage is composed of an N-channel transistor. In this case, the reference potential is 2 (| VTN high |-| VTP |). That is, the difference between the threshold voltage of the NMOS transistor having a high threshold voltage and the threshold voltage of the PMOS transistor of the normal threshold voltage is doubled.

As shown in FIG. 3, the temperature coefficient of VT of a PMOS transistor is generally -2 mV / ° C.
The temperature coefficient of VT of the transistor is about -1.5 mV / ° C. For comparison with the LSI of the first embodiment, | VTN
| = 1.5V and | VTP | = 0.825V. In this case, the reference potential when the operating temperature is 0 ° C is 2 (1.5-
0.825) = 1.35V, operating temperature 100 ℃
At that time, the reference potential is 2 (1.35-0.625) =
It becomes 1.45. Therefore, when the operating temperature is 0 ° C, the internal voltage of 4V is about 1.45V when the operating temperature is 100 ° C.
X (R1 + R2) /R2=4.30V.

In the case of the embodiment shown in FIG. 2, the temperature coefficient of the operating speed from 0 ° C. to 100 ° C. of the operating temperature of the conventional LSI having an internal step-down circuit which does not depend on temperature is about 1.075. It is possible to prevent a delay in operating speed due to fluctuations.
For example, in a conventional LSI including a MOS transistor having an operating speed of 20 ns at an operating temperature of 0 ° C. and 23 ns at an operating temperature of 100 ° C., a delay of about 1.5 ns, which is half the delay, can be shortened. it can.

FIG. 4 is a circuit diagram of an internal step-down circuit of an LSI according to the third embodiment of the present invention. The difference from the conventional circuit of FIG. 7 is that the constant voltage circuit T1 outputs two types of reference potentials, a reference potential 1 (VREF1) and a reference potential 2 (VREF2). Reference potential 1 is 2 (| VTP high | -3 | V
TP |), and has the same temperature coefficient as the reference potential of the first embodiment. Further, the reference potential 2 is 2 (| VTP high |-| V
TP |) and does not have temperature dependence like the reference potential of the conventional circuit. The respective reference potential outputs are respectively amplified by the negative feedback amplifiers F1 and F4, and VR1 and VR2 are respectively amplified.
Becomes In this example, the current value of the constant current source Ia1 is set to be three times the current value of the constant current sources Ib1 and Ic1 so that the current values I1 and I1 flowing through the respective shunts of the constant voltage circuit T1 are set.
2 and I3 are made equal to each other.

In the conventional LSI of FIG. 7, assuming that the reference potential VREF of the constant voltage circuit T1 has temperature dependency, the voltage VB shown in FIG.
T is different. For example, the reference potential VREF is 4V at 0 ° C.
Thus, it is 4.59V at 100 ° C. Therefore, the voltage VBT that activates the voltage follower F3 is also
It will change from 6.5V to 7.46V. Therefore, when stress is applied with an external voltage of 7.5 V, there is almost no margin for activating the voltage follower F3, and the necessary stress voltage may not be applied reliably.

However, in the embodiment of FIG. 4, the reference potential 2 having no temperature coefficient is used for the input of the comparator C1, so that the voltage VBT for activating the voltage follower F3 has no temperature dependence. . Therefore, during normal operation, the power supply voltage of the internal circuit has temperature dependence due to the reference potential 1 having a temperature coefficient, but the voltage V
The BT can have a structure having no temperature dependence.
Therefore, there is no fear that the margin between the voltage VBT and the voltage during the normal operation and the voltage during the burn-in test becomes insufficient regardless of the temperature.

In the internal step-down circuit of the LSI of the present invention, the LS
A low internal voltage is output during low temperature operation of I to prevent deterioration of MOS transistors forming an internal circuit due to hot carriers, and a high internal voltage corresponding to the temperature is output during normal temperature and high temperature operation, so that It compensates for the speed reduction of the MOS transistor that occurs during high temperature operation. This makes it possible to maintain high-speed operation of the LSI and improve its reliability. Conventionally, an internal step-down circuit that outputs an internal voltage that gives a positive temperature coefficient as described above has not been known.

In each of the above embodiments, the diode characteristic element is formed of the MOS transistor.
The diode characteristic element in the internal step-down circuit of the LSI of the present invention is not limited to the MOS transistor in particular, and at least a part thereof may be formed of, for example, a bipolar transistor or a diode.

[0034]

As described above, in the semiconductor integrated circuit device of the present invention, the internal power supply generation circuit for outputting the internal voltage having a positive temperature coefficient is provided, so that the operating speed of the LSI during high temperature operation can be improved. Since it is possible to prevent the deterioration of the MOS transistor due to hot carriers at the time of low-temperature operation without lowering the temperature, it is possible to secure high-speed operation of the semiconductor integrated circuit device and improve reliability.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an internal step-down circuit of an LSI according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an internal step-down circuit of an LSI according to a second embodiment of the present invention.

FIG. 3 is a temperature characteristic diagram of threshold voltages of general NMOS and PMOS transistors.

FIG. 4 is a circuit diagram showing a configuration of an internal step-down circuit of an LSI according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an internal step-down circuit of an LSI of a first conventional example.

FIG. 6 is a temperature characteristic diagram of threshold voltages of a PMOS transistor having a high threshold voltage and a PMOS transistor having a normal threshold voltage.

FIG. 7 is a circuit diagram showing a configuration of an internal step-down circuit of an LSI of a second conventional example.

8 is a graph showing the relationship between the output voltage of the internal voltage down converter of FIG. 7 and the external voltage.

[Explanation of symbols]

P1 to P8, Pa to Pc P channel type MOS transistor Na to Nc N channel type MOS transistor R1 to R7, R1a, R2a, R1b, R2b Resistor F1 to F4 Negative feedback amplifier circuit C1 Comparator INV1 Inverter Ia, Ib, Ia1, Ib1 , Ic1 constant current source T1 constant voltage circuit

Claims (8)

[Claims] 1. A semiconductor integrated circuit device comprising: an internal power supply generation circuit which is supplied with an external power supply to generate an internal power supply having a predetermined internal voltage; and an internal circuit which has a predetermined function and is supplied with the internal power supply. 2. The semiconductor integrated circuit device according to claim 1, wherein the internal voltage has a positive temperature coefficient with respect to temperature change. 2. The internal power supply generation circuit comprises: a first diode characteristic element that generates a first forward voltage drop when a cathode is maintained at a predetermined potential and a first current is applied in a forward direction; A second diode characteristic element that is connected to the anode of the first diode characteristic element and is supplied with a second current in the forward direction to generate a second forward voltage drop,
The voltage generation circuit which is supplied with the external power source and outputs the internal voltage proportional to the reference potential with the cathode potential of the second diode characteristic element as a reference potential. Semiconductor integrated circuit device. 3. The method according to claim 2, wherein each of the first and second diode characteristic elements is composed of a MOS transistor in which a gate and a drain and a bulk and a source are connected to each other. Semiconductor integrated circuit device. 4. Each of the MOS transistors forming the first and second diode characteristic elements is composed of at least two MOS transistors having the same threshold voltage and connected in series. The semiconductor integrated circuit device according to claim 3. 5. The semiconductor integrated circuit device according to claim 4, wherein the number of MOS transistors forming the first and second diode characteristic elements are different from each other. 6. The semiconductor integrated circuit according to claim 3, wherein one of the MOS transistors forming the first and second diode characteristic elements is a P-channel transistor and the other is an N-channel transistor. apparatus. 7. A second internal power supply generation circuit, the output voltage of which is dependent on the external voltage and has no temperature coefficient, and output selection means for selecting one of the outputs of both internal power supply generation circuits. 7. The semiconductor integrated circuit device according to claim 1, wherein the output selection means selects an output of the second internal power supply generation circuit when the power supply voltage is equal to or higher than a predetermined value. 8. The positive temperature coefficient is in the range of about 1.075 to about 1.15.
1. A semiconductor integrated circuit device according to 1.