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JPH06334188A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06334188A
JPH06334188A JP5115582A JP11558293A JPH06334188A JP H06334188 A JPH06334188 A JP H06334188A JP 5115582 A JP5115582 A JP 5115582A JP 11558293 A JP11558293 A JP 11558293A JP H06334188 A JPH06334188 A JP H06334188A
Authority
JP
Japan
Prior art keywords
layer
concentration
low
junction
breakdown voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5115582A
Other languages
Japanese (ja)
Other versions
JP3185474B2 (en
Inventor
Toshibumi Ohata
俊文 大畠
Yoshitaka Sugawara
良孝 菅原
Yasuki Nakano
安紀 中野
Yoshiteru Shimizu
喜輝 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
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Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11558293A priority Critical patent/JP3185474B2/en
Publication of JPH06334188A publication Critical patent/JPH06334188A/en
Application granted granted Critical
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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00Thyristors
    • H10D18/251Lateral thyristors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/108Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having localised breakdown regions, e.g. built-in avalanching regions 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 

Landscapes

  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】本発明の目的は更に高耐圧化に適したターミネ
ーション構造を提供することにある。 【構成】低濃度のp層を主接合p層のコーナ部を覆うよ
うに深く形成したターミネーション構造で主接合p層の
表面横方向の先端から主接合p層からの電極の先端まで
の距離を主接合p層の表面横方向の先端から低濃度p層
端までの距離と略同じでない構造とする。 【効果】半導体素子の耐圧特性が向上する。
(57) [Summary] [Object] An object of the present invention is to provide a termination structure suitable for further increasing the withstand voltage. [Structure] A termination structure in which a low-concentration p-layer is deeply formed so as to cover a corner portion of the main-junction p-layer has a distance from a tip in the lateral direction of the main-junction p-layer to a tip of the electrode from the main-junction p-layer. The distance from the tip of the main junction p-layer in the lateral direction to the end of the low-concentration p-layer is not substantially the same. [Effect] The withstand voltage characteristic of the semiconductor element is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高耐圧化に適したターミ
ネーション構造を有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a termination structure suitable for high breakdown voltage.

【0002】[0002]

【従来の技術】従来、高耐圧化のためのターミネーショ
ン構造として(ISPSD 88,p107−p11
0)論文に記載された構造が知られている。その構造の
例を図11に示す。1はn型基板、2はn埋込層、3,
9は絶縁膜、4は支持基板、5は電極、6は主接合のp
層、主接合のp層6より段階的に低濃度かつ浅い接合で
電界緩和層71,72,73を構成する。31はある等
電位線を示す。電極5は横方向に伸びているが、低濃度
p層71端より内側で止まっている。主接合層6と基板
1に逆バイアスすると空乏層がpn接合から伸びる。こ
のように高耐圧接合の端部に順次低濃度、且つ浅いp層
を接触しながら形成することで、接合の端部における電
界集中を緩和する方法が知られている。この方法の原型
は(IEEE1979年,p238−p241)に詳しく記
載されている、RESURF(ReducedSurface Field)効果と
呼ばれるもので以下簡単に説明する。
2. Description of the Related Art Conventionally, as a termination structure for increasing the breakdown voltage (ISPSD 88, p107-p11
0) The structure described in the paper is known. An example of the structure is shown in FIG. 1 is an n-type substrate, 2 is an n-buried layer, 3,
9 is an insulating film, 4 is a support substrate, 5 is an electrode, and 6 is a main junction p
The electric field relaxation layers 71, 72 and 73 are formed by a junction having a shallower concentration and a shallower concentration than the layer and the p layer 6 of the main junction. Reference numeral 31 indicates a certain equipotential line. The electrode 5 extends in the lateral direction, but stops inside the end of the low-concentration p-layer 71. When the main junction layer 6 and the substrate 1 are reverse biased, the depletion layer extends from the pn junction. As described above, there is known a method of relaxing the electric field concentration at the end of the junction by sequentially forming a low concentration and shallow p layer in contact with the end of the high breakdown voltage junction. Prototype (IEEE 1979 years, P238-P241) of the method is described in detail in, briefly described below what is called RESURF (Re duced Sur face F ield ) effect.

【0003】例えばn型基板内にボロン拡散等によりp
n接合を作る場合、どうしてもp層の表面の方が不純物
濃度が幾分高くなる事また、半導体の表面は不安定要因
が多く電界強度が弱い事等の理由から、横方向(表面方
向)の空乏層は縦方向(深さ方向)より伸びないので、
耐圧は横方向(表面方向)で決まってしまう。
For example, p is formed in an n-type substrate by boron diffusion or the like.
When an n-junction is formed, the impurity concentration on the surface of the p-layer is inevitably higher than that on the surface of the semiconductor, and the semiconductor surface has many instability factors and weak electric field strength. Since the depletion layer does not extend in the vertical direction (depth direction),
The breakdown voltage is determined in the lateral direction (surface direction).

【0004】RESURF構造では、素子のターミネーション
部に低濃度のp層を適切な濃度と接合深さで設け、空乏
層が低濃度のp層内を伸びやすくすることによって、電
界を緩和するものである。横方向における電界が(降伏
が起きる)臨界電界に達する前に、低濃度のp層内を下
の接合部から(すなわち縦方向から)伸びてきた空乏層
端が半導体素子表面まで達してしまう。すると、低濃度
のp層全体が空乏層化し、横方向の空乏層は拡大する。
よって、横方向における電界が緩和され素子の耐圧が向
上する。
In the RESURF structure, a low-concentration p-layer is provided at an appropriate concentration and a junction depth in the termination portion of the device, and the depletion layer easily extends in the low-concentration p-layer, thereby relaxing the electric field. is there. Before the electric field in the lateral direction reaches the critical electric field (breakdown occurs), the depletion layer edge extending from the lower junction portion (that is, from the vertical direction) in the low-concentration p-layer reaches the semiconductor element surface. Then, the entire low-concentration p-layer becomes a depletion layer, and the lateral depletion layer expands.
Therefore, the electric field in the lateral direction is relaxed and the breakdown voltage of the device is improved.

【0005】図11は低濃度p層71,72,73を段
階的に濃度を低く、接合を浅くすることで主接合p層の
コーナの曲率を擬似的に大きくし高耐圧化する効果も加
味してある。
FIG. 11 shows that the low-concentration p-layers 71, 72, 73 are gradually reduced in concentration and the junction is shallowed to artificially increase the corner curvature of the main-junction p-layer to increase the breakdown voltage. I am doing it.

【0006】又、従来からの代表的なターミネーション
構造としてp層主接合から電極により表面接合の近傍に
おける電界集中をその電位によって横方向に緩和して高
耐圧化する手法が知られており、フィールドプレート
(以下FPと略す)効果と称している。図11では、論
文に詳細は言及されていないが、主接合からの電極が低
濃度のp層を越えない範囲でしか伸びていないことか
ら、この構造はRESURF効果を主に期待しているといえ
る。
As a typical conventional termination structure, a method is known in which the electric field concentration in the vicinity of the surface junction is relaxed laterally by the potential from the p-layer main junction to the electrode to increase the breakdown voltage. It is called a plate (hereinafter abbreviated as FP) effect. In FIG. 11, although not described in detail in the paper, the structure mainly expects the RESURF effect because the electrode from the main junction extends only within the range not exceeding the low-concentration p-layer. I can say.

【0007】[0007]

【発明が解決しようとする課題】RESURFおよびFPとい
った手法はp層主接合の表面付近の電界を半導体の表面
横方向に緩和することで高耐圧化を図るものであるが、
主接合が深い場合は、最大電界となる深さ方向のp層の
コーナ部(図中A)の電界があまり緩和できない。よっ
て、低濃度のp層を更に横方向に延ばしても耐圧を僅か
しか向上できず、素子面積が大きくなってしまう割に大
幅な高耐圧化は期待できない。
The methods such as RESURF and FP are intended to increase the breakdown voltage by relaxing the electric field near the surface of the p-layer main junction in the lateral direction of the semiconductor surface.
When the main junction is deep, the electric field in the corner portion (A in the figure) of the p layer in the depth direction, which is the maximum electric field, cannot be relaxed so much. Therefore, even if the low-concentration p-layer is further extended in the lateral direction, the withstand voltage can be improved only slightly, and a large increase in withstand voltage cannot be expected despite the increase in the element area.

【0008】低濃度のp層の表面は外的要因により誘導
される表面濃度の変動が著しく、これが空乏層の拡がり
に影響を与える。ところが、低濃度のp層7に主接合か
らの電極5が掛かっていることで素子の信頼性を向上す
ることができる。この点においては主接合からの電極5
を低濃度のp層を越えて伸ばすのが一番望ましいが、素
子がブロッキング状態では、電極5が逆バイアスになり
表面接合に対し負電位になっているため、主接合からの
電極5下に正孔が蓄積し高濃度p層化するのでRESURFの
効果がなくなってしまう。図11はRESURF効果を期待し
た構造であり、なるべく低濃度のp層上に主接合からの
電極を伸ばさない方がいいが、前述のように素子の信頼
性を保証するためにある程度必要である。
On the surface of the low concentration p-layer, the fluctuation of the surface concentration induced by an external factor is remarkable, which affects the spread of the depletion layer. However, since the low-concentration p-layer 7 is covered with the electrode 5 from the main junction, the reliability of the device can be improved. In this respect the electrode 5 from the main junction
Is most desirable to extend beyond the low-concentration p-layer, but when the device is in the blocking state, the electrode 5 is reverse biased and has a negative potential with respect to the surface junction. Since holes are accumulated and a high-concentration p-layer is formed, the effect of RESURF disappears. FIG. 11 shows a structure in which the RESURF effect is expected, and it is better not to extend the electrode from the main junction on the p-layer having a low concentration, but it is necessary to ensure the reliability of the device to some extent as described above. .

【0009】本発明の目的は少ないターミネーション面
積で高耐圧化するのに適したターミネーション構造を提
供することにある。
An object of the present invention is to provide a termination structure suitable for achieving a high breakdown voltage with a small termination area.

【0010】[0010]

【課題を解決するための手段】本発明のターミネーショ
ンは基本的には低濃度のp層を主接合p層のコーナ部を
覆うように深く形成した構造で、主接合p層の表面横方
向の先端から主接合p層からの電極の先端までの距離
(以下LFPと略す)が主接合p層の表面横方向の先端
から低濃度p層端までの距離(以下LPと略す)と略同
じでない構造である。
The termination of the present invention basically has a structure in which a low-concentration p-layer is deeply formed so as to cover a corner portion of the main-junction p-layer. The distance from the tip to the tip of the electrode from the main junction p-layer (hereinafter abbreviated as LFP) is not approximately the same as the distance from the tip in the lateral direction of the surface of the main junction p-layer to the low-concentration p-layer edge (hereinafter abbreviated as LP). It is a structure.

【0011】この課題を解決する第1の手段である本発
明のターミネーションは低濃度のp層を主接合p層のコ
ーナ部を覆うように深く形成した構造で、LFPをLP
より短くした構造である。
The termination of the present invention, which is the first means for solving this problem, is a structure in which a low-concentration p-layer is deeply formed so as to cover the corner portion of the main junction p-layer, and the LFP is an LP.
It is a shorter structure.

【0012】この課題を解決する第2の手段である本発
明のターミネーションは低濃度のp層を主接合p層のコ
ーナ部を覆うように深く形成した構造で、LFPをLP
より長くした構造である。
The termination of the present invention, which is the second means for solving this problem, is a structure in which a low-concentration p-layer is deeply formed so as to cover the corner portion of the main junction p-layer.
It has a longer structure.

【0013】[0013]

【作用】本発明者等の実験によると、例えば低濃度のp
層の濃度が約1018cm-3以上では低濃度のp層のコーナ
部が最大電界となり、ここで耐圧が決まる。この時FP
またはRESURFの効果はない。
According to the experiments by the present inventors, for example, a low concentration of p
When the concentration of the layer is about 10 18 cm -3 or more, the corner portion of the low concentration p layer has the maximum electric field, and the breakdown voltage is determined here. At this time FP
Or RESURF has no effect.

【0014】低濃度のp層の濃度が約1017cm-3以下で
は低濃度のp層の濃度に比べて、電極が逆バイアスされ
ることによってLFP下に誘起されるp層の濃度の方が
はるかに高くなり、この高濃度の蓄積層端が最大電界と
なる。
When the concentration of the low-concentration p-layer is about 10 17 cm −3 or less, the concentration of the p-layer induced under the LFP by the reverse bias of the electrode is lower than that of the low-concentration p-layer. Is much higher, and the maximum electric field is at the edge of the high-concentration storage layer.

【0015】LFP<LPの場合は(LP−LFP)の
長さの分の低濃度のp層によってRESURF効果が現れ、耐
圧が向上できる。(LP−LFP)を大きくするほどRESU
RF効果が大きいが、先述した信頼性の問題がありおのず
と限度がある。
When LFP <LP, the RESURF effect appears due to the low concentration p layer corresponding to the length of (LP-LFP), and the breakdown voltage can be improved. The larger (LP-LFP) is, the more RESU
Although the RF effect is large, it is naturally limited due to the reliability problem mentioned above.

【0016】LFPとLPが略等しい時は、RESURF効果
が小さくなる。
When LFP and LP are substantially equal, the RESURF effect becomes small.

【0017】LFP>LPの時は(LFP−LP)の長
さの分FP効果が現れる。すなわち、逆バイアスされた
主接合からの電極の低濃度のp層端を越えn基板上につ
きでた部分が空乏化するため、蓄積層端の最大電界を下
げ、耐圧が大きくなる。但し、この場合蓄積層端は低濃
度p層のコーナ部に位置するので、蓄積層端が低濃度p
層の内部にある上記LFP<LPの場合に比べ、この部
分の空乏層の伸びは小さい。よってLFP>LPの場合
はLFP<LPの場合に比べ耐圧特性は悪くなる。ま
た、電極を伸ばすことはターミネーション領域の拡大に
繋がる可能性があり、その場合素子面積を増大させるこ
とになる。
When LFP> LP, the FP effect appears by the length of (LFP-LP). That is, since the portion of the electrode from the reverse-biased main junction beyond the low-concentration p-layer edge and depleted on the n-substrate is depleted, the maximum electric field at the edge of the storage layer is lowered, and the breakdown voltage is increased. However, in this case, since the edge of the storage layer is located at the corner of the low concentration p layer, the edge of the storage layer has a low concentration p.
The extension of the depletion layer in this portion is smaller than that in the case of LFP <LP inside the layer. Therefore, in the case of LFP> LP, the breakdown voltage characteristic becomes worse than in the case of LFP <LP. Further, stretching the electrode may lead to expansion of the termination region, in which case the element area will be increased.

【0018】[0018]

【実施例】以下、本発明半導体装置を図面を用いて具体
的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be specifically described below with reference to the drawings.

【0019】図1は本発明のターミネーション構造を高
耐圧の誘電体絶縁分離型パワーICに適用した場合の一
実施例であり、図2はその動作を示す説明図である。1
はn型基板、2はn埋込層、3,9は絶縁膜、4は支持
基板、5は電極、6は主接合のp層、7は横方向の電界
緩和の低濃度p層である。電極5は横方向に伸びている
が、低濃度p層7端より内側で止まっている。主接合層
6と基板1に逆バイアスすると空乏層がpn接合から伸
びる。点線で示す蓄積層101は電極5が逆バイアスさ
れたときに生じる。当然、逆バイアス電圧が大きいほど
高濃度化される。図11の従来構造では低濃度のp層7
1,72,73のRESURF効果があるがA部の最大電界で
耐圧が決まってしまう。
FIG. 1 is an embodiment in which the termination structure of the present invention is applied to a high voltage dielectric insulation isolation type power IC, and FIG. 2 is an explanatory view showing its operation. 1
Is an n-type substrate, 2 is an n-buried layer, 3 and 9 are insulating films, 4 is a support substrate, 5 is an electrode, 6 is a main junction p-layer, and 7 is a low-concentration p-layer for lateral electric field relaxation. . The electrode 5 extends in the lateral direction, but stops inside the end of the low-concentration p-layer 7. When the main junction layer 6 and the substrate 1 are reverse biased, the depletion layer extends from the pn junction. The storage layer 101 shown by the dotted line occurs when the electrode 5 is reverse biased. Naturally, the higher the reverse bias voltage, the higher the concentration. In the conventional structure of FIG. 11, the low concentration p layer 7 is formed.
Although there is a RESURF effect of 1, 72, 73, the breakdown voltage is determined by the maximum electric field in the A section.

【0020】本発明構造では主接合よりも曲率の大きい
低濃度のp層7によるガードリング効果に低濃度のp層
7が空乏化することによる電界緩和効果(RESURF効果)
が重なり、A部の最大電界は低くなる。この時の耐圧
は、逆バイアスされた電極5によってLFP下に生じた
蓄積層101のコーナ部(B部)の最大電界で決まる。
このB点の電界を緩和させるためには、蓄積層101端
から低濃度p層7端までの低濃度のp層分がB点に対し
てのRESURF効果となることから、LPを伸ばすかLFP
を短くしなければならない。当然、素子面積を大きくし
ないためにはLPを伸ばさず、素子の信頼性を保証する
範囲でLFPを短くする方法が望ましい。蓄積層101
は逆バイアス電圧が大きいほど高濃度化されるので、高
耐圧の素子であるほど本発明構造の効果は著しい。本発
明者らの実験では、低濃度のp層71,72,73の形
状以外は図11と同じ条件のダイオードで比較してみた
場合、n型基板1が150Ω、主接合のp層6の拡散深
さが6μmで濃度が1×1019cm-3、電界緩和の低濃度
p層7の拡散深さが7μmで濃度が1×1016cm-3であ
る時、図11構造では耐圧約1200Vなのが図1の構
造は耐圧約2100Vであった。ちなみに図11の低濃
度のp層72,73が無い構造では耐圧約600Vであ
った。
In the structure of the present invention, the electric field relaxation effect (RESURF effect) due to the depletion of the low concentration p layer 7 due to the guard ring effect of the low concentration p layer 7 having a curvature larger than that of the main junction
Overlap with each other, and the maximum electric field in the area A becomes low. The breakdown voltage at this time is determined by the maximum electric field of the corner portion (B portion) of the storage layer 101 generated under the LFP by the reverse-biased electrode 5.
In order to alleviate the electric field at the point B, the low concentration p layer from the edge of the storage layer 101 to the edge of the low concentration p layer 7 becomes the RESURF effect for the point B.
Must be shortened. Of course, in order not to increase the element area, it is desirable that the LP is not extended and the LFP is shortened within the range in which the reliability of the element is guaranteed. Storage layer 101
Since the higher the reverse bias voltage is, the higher the concentration becomes, the higher the breakdown voltage of the element, the more remarkable the effect of the structure of the present invention. In an experiment conducted by the present inventors, when compared with a diode under the same conditions as in FIG. 11 except for the shapes of the low-concentration p layers 71, 72, 73, the n-type substrate 1 has a resistance of 150Ω and the p-layer 6 of the main junction has When the diffusion depth is 6 μm and the concentration is 1 × 10 19 cm −3 , and the diffusion depth of the low-concentration p-layer 7 for electric field relaxation is 7 μm and the concentration is 1 × 10 16 cm −3 , the breakdown voltage of the structure of FIG. The structure of FIG. 1 has a withstand voltage of about 2100V, which is 1200V. Incidentally, the breakdown voltage was about 600 V in the structure without the low-concentration p layers 72 and 73 in FIG.

【0021】図3は本発明のターミネーション構造の第
2の実施例であり、図4はその動作を示す説明図であ
る。1はn型基板、2はn埋込層、3,9は絶縁膜、4
は支持基板、5は電極、6は主接合のp層、7は横方向
の電界緩和の低濃度p層である。電極5は低濃度p層7
端を越えて横方向に伸びている。主接合層6と基板1に
逆バイアスすると空乏層がpn接合から伸びる。
FIG. 3 shows a second embodiment of the termination structure of the present invention, and FIG. 4 is an explanatory view showing the operation thereof. 1 is an n-type substrate, 2 is an n-buried layer, 3 and 9 are insulating films, 4
Is a support substrate, 5 is an electrode, 6 is a main junction p-layer, and 7 is a low-concentration p-layer for lateral electric field relaxation. Electrode 5 is low concentration p layer 7
It extends laterally beyond the edges. When the main junction layer 6 and the substrate 1 are reverse biased, the depletion layer extends from the pn junction.

【0022】主接合から伸びた電極5により低濃度p層
7上(すなわちLPの範囲)は蓄積層102化し、B点
の最大電界が大になるが、n基板1上(すなわち(LF
P−LP)の範囲103)が空乏化するためB点の最大
電界を下げ、耐圧が大きくなる。但しA点の最大電界よ
りB点の方が最大電界は大きいため、耐圧はB点で決ま
る。
The electrode 5 extending from the main junction makes the storage layer 102 on the low-concentration p-layer 7 (that is, the range of LP), and the maximum electric field at the point B becomes large, but on the n-substrate 1 (that is, (LF
Since the range 103) of (P-LP) is depleted, the maximum electric field at the point B is lowered and the breakdown voltage is increased. However, since the maximum electric field at point B is larger than the maximum electric field at point A, the breakdown voltage is determined at point B.

【0023】蓄積層102は逆バイアス電圧が大きいほ
ど高濃度化されるので、高耐圧の素子であるほど本発明
構造の効果は著しい。本発明者らの実験では、低濃度の
p層7の形状と電極5が低濃度のp層7端を越えて伸び
ていること以外は図11と同じ条件のダイオードで比較
してみた場合、n型基板1が150Ω、主接合のp層6
の拡散深さが6μmで濃度が1×1019cm−3、7
は電界緩和の低濃度p層7の拡散深さが7μmで濃度が
1×1016cm-3である時、図11構造では耐圧約1200V
なのが図3の構造では耐圧約1900Vであった。
Since the concentration of the storage layer 102 increases as the reverse bias voltage increases, the effect of the structure of the present invention becomes more remarkable as the element has a higher breakdown voltage. In the experiments conducted by the present inventors, a comparison was made with a diode under the same conditions as in FIG. 11 except that the shape of the low-concentration p-layer 7 and the electrode 5 extend beyond the end of the low-concentration p-layer 7. n-type substrate 1 is 150Ω, main junction p-layer 6
Has a diffusion depth of 6 μm and a concentration of 1 × 10 19 cm −3 , 7
When the diffusion depth of the low-concentration p-layer 7 for electric field relaxation is 7 μm and the concentration is 1 × 10 16 cm −3 , the structure of FIG.
The breakdown voltage of the structure of FIG. 3 was about 1900V.

【0024】図5は図1,図3及び図11で示したター
ミネーション構造における耐圧を、電極5のLFPをパ
ラメータに示す。実線11は本発明構造の耐圧を、点線
10は従来構造の耐圧を示す。従来構造では主接合p層
が深い場合には、RESURF効果及びFP効果が顕著には現
れない。
FIG. 5 shows the breakdown voltage in the termination structure shown in FIGS. 1, 3 and 11 with the LFP of the electrode 5 as a parameter. The solid line 11 shows the breakdown voltage of the structure of the present invention, and the dotted line 10 shows the breakdown voltage of the conventional structure. In the conventional structure, when the main junction p-layer is deep, the RESURF effect and the FP effect do not significantly appear.

【0025】本発明の構造ではLFPが図中A点までは
RESURFの効果で耐圧が高く、LFPが短いほど耐圧は高
くなる。A点以降はFPの効果で耐圧が高く、LFPが
長いほど耐圧は高くなる。このA点はLPとLFPが略
等しいある点である。
In the structure of the present invention, the LFP is up to the point A in the figure.
Due to the effect of RESURF, the breakdown voltage is high, and the shorter the LFP, the higher the breakdown voltage. After point A, the breakdown voltage is high due to the effect of FP, and the longer the LFP, the higher the breakdown voltage. This point A is a point where LP and LFP are substantially equal.

【0026】A点に対し、LFPを長くする方が短くす
る方より効果が少ない。これはFP効果を狙う場合の蓄
積層端は低濃度p層のコーナ部に位置するので、蓄積層
端が低濃度p層の内部にあるLFP<LPの場合に比
べ、この部分の空乏層の伸びは小さいため、LFP<L
Pの場合に比べ耐圧特性は悪くなることによる。
For point A, increasing the LFP is less effective than decreasing the LFP. This is because the edge of the storage layer when aiming at the FP effect is located at the corner portion of the low-concentration p layer, so that the depletion layer of this portion is less than the case of LFP <LP where the edge of the storage layer is inside the low-concentration p layer. Since the growth is small, LFP <L
This is because the breakdown voltage characteristics are worse than in the case of P.

【0027】図6は本発明のターミネーションをダイオ
ードに適用した場合の平面パターンの例を示す。主接合
6は周辺を低濃度層7で囲まれ、電極5が主接合6と低
濃度層7の間まで覆っている構造である。又、カソード
とオーミック接触するためのn層14がある。本構造に
よればターミネーション部の電界を緩和できるため、ダ
イオードの耐圧を高くできる。ここではダイオードを例
に説明したが、トランジスタ,サイリスタ,MOSFET,I
GBT,MOSサイリスタ等でも同様に耐圧を高くでき
る。図1の説明で述べた諸条件を適用すると耐圧を従来
の約600Vから約2100Vに向上できる。
FIG. 6 shows an example of a plane pattern when the termination of the present invention is applied to a diode. The main junction 6 has a structure in which the periphery is surrounded by the low-concentration layer 7, and the electrode 5 covers the space between the main junction 6 and the low-concentration layer 7. There is also an n-layer 14 for making ohmic contact with the cathode. According to this structure, since the electric field of the termination portion can be relaxed, the breakdown voltage of the diode can be increased. Although a diode is used as an example here, a transistor, a thyristor, a MOSFET, an I
Similarly, with a GBT, a MOS thyristor, etc., the breakdown voltage can be increased. By applying the conditions described in the description of FIG. 1, the withstand voltage can be increased from the conventional about 600V to about 2100V.

【0028】図7は本ターミネーション構造をトランジ
スタに適用した場合の断面の例を示す。主接合のp層を
ベースとし、このp層6の中にエミッタ層のn層16を
形成している。15はコレクタのコンタクト層である、
17はエミッタ電極、18はベース電極、51はコレク
タ電極である。本構造によれば、従来の基板抵抗でより
高耐圧化が可能である。又、従来と同じ耐圧でより低抵
抗の基板を使用できるので、トランジスタのコレクタ抵
抗成分を小さくできる。
FIG. 7 shows an example of a cross section when this termination structure is applied to a transistor. An n layer 16 of an emitter layer is formed in the p layer 6 based on the p layer of the main junction. 15 is a collector contact layer,
Reference numeral 17 is an emitter electrode, 18 is a base electrode, and 51 is a collector electrode. According to this structure, it is possible to increase the breakdown voltage with the conventional substrate resistance. Further, since a substrate having the same breakdown voltage as that of the conventional one and a lower resistance can be used, the collector resistance component of the transistor can be reduced.

【0029】図8は縦型nMOSFETに本ターミネーション
構造を適用した場合を示す。チャネル層及び主接合のp
層6の中にソース層19を形成している。211はドレ
インコンタクト層、20はゲート、21はソース電極、
52はドレイン電極である。本構造によれば、従来の基
板抵抗でより高耐圧化が可能である。又、従来と同じ耐
圧でより低抵抗の基板を使用できるので、MOSFETのオン
抵抗を小さくできる。図9はラテラルサイリスタに本タ
ーミネーション構造を適用した場合を示す。アノード層
22,pベース層23は高耐圧接合層であり、pベース
層23の中にカソード層24を形成している。25はゲ
ートコンタクト層、26はアノード電極、27はpゲー
ト電極、28はカソード電極、29はnゲート電極であ
る。このように高耐圧層は1素子に複数個存在しても一
向に構わない。
FIG. 8 shows a case where this termination structure is applied to a vertical nMOSFET. P of channel layer and main junction
The source layer 19 is formed in the layer 6. 211 is a drain contact layer, 20 is a gate, 21 is a source electrode,
52 is a drain electrode. According to this structure, it is possible to increase the breakdown voltage with the conventional substrate resistance. Moreover, since a substrate having the same breakdown voltage as that of the conventional one and a lower resistance can be used, the on-resistance of the MOSFET can be reduced. FIG. 9 shows a case where this termination structure is applied to a lateral thyristor. The anode layer 22 and the p base layer 23 are high breakdown voltage junction layers, and the cathode layer 24 is formed in the p base layer 23. Reference numeral 25 is a gate contact layer, 26 is an anode electrode, 27 is a p gate electrode, 28 is a cathode electrode, and 29 is an n gate electrode. As described above, it does not matter if a plurality of high breakdown voltage layers are present in one element.

【0030】図10は縦型IGBTに本ターミネーショ
ン構造を適用した場合を示す。チャネル層及び主接合の
p層205の中にエミッタ層204を形成している。9
1はコレクタ層、203はゲート、202はエミッタ電
極、53はコレクタ電極である。本構造によれば、従来
の基板抵抗でより高耐圧化が可能である。又、従来と同
じ耐圧でより低抵抗の基板を使用できるので、IGBT
のオン抵抗を小さくできる。本発明者らの実験では、n
型基板1が100Ωで厚さが300μm、主接合のp層
6の拡散深さが6μmで濃度が1×1018cm-3、電界緩
和の低濃度p層7の拡散深さが7μmで濃度が1×10
16cm-3である時、耐圧約2000Vであった。
FIG. 10 shows a case where the present termination structure is applied to a vertical IGBT. An emitter layer 204 is formed in the p layer 205 of the channel layer and the main junction. 9
1 is a collector layer, 203 is a gate, 202 is an emitter electrode, and 53 is a collector electrode. According to this structure, it is possible to increase the breakdown voltage with the conventional substrate resistance. In addition, since it is possible to use a substrate with the same breakdown voltage and lower resistance as the conventional one, the IGBT
ON resistance of can be reduced. In our experiments, n
The mold substrate 1 has a thickness of 100Ω and a thickness of 300 μm, the main junction p-layer 6 has a diffusion depth of 6 μm and a concentration of 1 × 10 18 cm −3 , and the electric field relaxation low-concentration p-layer 7 has a diffusion depth of 7 μm. Is 1 × 10
When the pressure was 16 cm -3 , the breakdown voltage was about 2000V.

【0031】[0031]

【発明の効果】本発明によればターミネーションの占め
る素子面積の増加を少なくすると共に高耐圧化に適した
ターミネーション構造を提供でき、耐圧特性に優れた半
導体素子及びそれを使った回路構成又はそれを内蔵した
半導体集積回路が得られる。
According to the present invention, it is possible to provide a termination structure suitable for a high breakdown voltage while suppressing an increase in the device area occupied by termination, and a semiconductor device excellent in breakdown voltage characteristics, and a circuit configuration using the same or a semiconductor device using the same. A built-in semiconductor integrated circuit can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明半導体装置のターミネーション構造の断
面の例を示す。
FIG. 1 shows an example of a cross section of a termination structure of a semiconductor device of the present invention.

【図2】図1のターミネーション構造の動作説明図であ
る。
FIG. 2 is an operation explanatory diagram of the termination structure of FIG.

【図3】本発明のターミネーション構造の断面の例を示
す。
FIG. 3 shows an example of a cross section of a termination structure of the present invention.

【図4】図3のターミネーション構造の動作説明図であ
る。
FIG. 4 is an operation explanatory view of the termination structure of FIG.

【図5】本発明と従来のターミネーション構造の耐圧を
主接合p層の表面横方向の先端から主接合p層からの電
極の先端までの距離(LFP)による依存性を比較した
結果を示す。
FIG. 5 shows the results of comparison of the breakdown voltages of the present invention and the conventional termination structure depending on the distance (LFP) from the tip in the lateral direction of the main junction p-layer to the tip of the electrode from the main junction p-layer.

【図6】本発明のターミネーション構造を用いたダイオ
ードの平面パターンの例を示す。
FIG. 6 shows an example of a plane pattern of a diode using the termination structure of the present invention.

【図7】本発明のターミネーション構造を用いたnpn
トランジスタの断面構造を示す。
FIG. 7 is an npn using the termination structure of the present invention.
The cross-sectional structure of a transistor is shown.

【図8】本発明のターミネーション構造を用いた縦型n
MOSFETの断面構造の例を示す。
FIG. 8 is a vertical n using the termination structure of the present invention.
An example of the cross-sectional structure of a MOSFET is shown.

【図9】本発明のターミネーション構造を用いた高耐圧
ラテラルのサイリスタの断面構造を示す。
FIG. 9 shows a cross-sectional structure of a high breakdown voltage lateral thyristor using the termination structure of the present invention.

【図10】本発明のターミネーション構造を用いた縦型
IGBTの断面構造の例を示す。
FIG. 10 shows an example of a cross-sectional structure of a vertical IGBT using the termination structure of the present invention.

【図11】従来のターミネーション構造の断面の例を示
す。
FIG. 11 shows an example of a cross section of a conventional termination structure.

【符号の説明】[Explanation of symbols]

1…基板、2…埋込層、3,9…絶縁膜、4…支持基
板、5,17,18,21,26,27,28,29,
51,52,53,202,203…電極、6,205
…主接合、7,71,72,73…電界緩和層、14,
15,25…n層、16,204…トランジスタのエミ
ッタ層、19…nMOSFETのソース層、20…MOSFETのゲ
ート、22…サイリスタのアノード層、23…サイリス
タのpベース層、24…サイリスタのカソード層、31
…等電位線、91…IGBTのコレクタ層、101,1
02…蓄積層、103…空乏化する部分、201…バッ
ファ層、211…ドレインコンタクト層。
1 ... Substrate, 2 ... Buried layer, 3, 9 ... Insulating film, 4 ... Support substrate, 5, 17, 18, 21, 26, 27, 28, 29,
51, 52, 53, 202, 203 ... Electrodes, 6,205
... Main junction, 7, 71, 72, 73 ... Electric field relaxation layer, 14,
15 ... 25 n layer, 16, 204 ... Transistor emitter layer, 19 ... nMOSFET source layer, 20 ... MOSFET gate, 22 ... Thyristor anode layer, 23 ... Thyristor p base layer, 24 ... Thyristor cathode layer , 31
... equipotential lines, 91 ... IGBT collector layer, 101, 1
02 ... Accumulation layer, 103 ... Depleted portion, 201 ... Buffer layer, 211 ... Drain contact layer.

フロントページの続き (72)発明者 清水 喜輝 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内Continuation of front page (72) Inventor Yoshiteru Shimizu 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】すくなくとも第1の導電型の第1の半導体
層とこれより不純物濃度の高い第2導電型の第2の半導
体層とから形成される主接合を有する半導体装置におい
て、第2の半導体層より低濃度の第2導電型の第3の半
導体層を主接合の第2の半導体層に接触して形成し、更
にこの低濃度の第3の半導体層と第1の半導体層で形成
する接合は主接合の第2の半導体層と同じもしくは深い
接合であり、その接合の表面横方向の先端位置が主接合
の第2の半導体層からの電極の先端と略同じ位置ではな
いことを特徴とするターミネーション構造を具備した半
導体装置。
1. A semiconductor device having a main junction formed of at least a first-conductivity-type first semiconductor layer and a second-conductivity-type second semiconductor layer having a higher impurity concentration than the first-conductivity-type second semiconductor layer. A third semiconductor layer of the second conductivity type having a concentration lower than that of the semiconductor layer is formed in contact with the second semiconductor layer of the main junction, and further formed of the third semiconductor layer of the low concentration and the first semiconductor layer. The junction formed is the same as or deeper than the second semiconductor layer of the main junction, and the tip position of the junction in the lateral direction of the surface is not substantially the same as the tip of the electrode from the second semiconductor layer of the main junction. A semiconductor device having a characteristic termination structure.
【請求項2】請求項1において、低濃度の第3の半導体
層と第1の半導体層で形成する接合の表面横方向の先端
は主接合の第2の半導体層からの電極の先端より外側で
あることを特徴とするターミネーション構造を具備した
半導体装置。
2. The tip in the lateral direction of the surface of the junction formed by the low-concentration third semiconductor layer and the first semiconductor layer is outside the tip of the electrode from the second semiconductor layer of the main junction. And a semiconductor device having a termination structure.
JP11558293A 1993-05-18 1993-05-18 Semiconductor device Ceased JP3185474B2 (en)

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Applications Claiming Priority (1)

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JP11558293A JP3185474B2 (en) 1993-05-18 1993-05-18 Semiconductor device

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Publication Number Publication Date
JPH06334188A true JPH06334188A (en) 1994-12-02
JP3185474B2 JP3185474B2 (en) 2001-07-09

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ID=14666164

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Country Link
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US7772677B2 (en) 2006-02-02 2010-08-10 Fuji Electric Systems Co., Ltd. Semiconductor device and method of forming the same having a junction termination structure with a beveled sidewall
US7911020B2 (en) 2007-07-12 2011-03-22 Fuji Electric Systems Co., Ltd. Semiconductor device having breakdown voltage maintaining structure and its manufacturing method
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