JPH06348780A - Layout editor device - Google Patents

Abstract

PURPOSE:To perform a layout considering electromigration and stroke by calculating the wiring width of each wire from a current on each wire by a wiring width decision means, and deciding the wiring width of each wire to be plotted on a layout drawing. CONSTITUTION:When the current value of the current on each wire is calculated by a current value calculation means 11, the wiring width decision means 12 decides the wiring width of each wire based on the current value. For example, when relation between the wiring width and the current value is decided by the design rule of process as current <= constant lX(wiring width-constant 2), it goes to wiring width >= current/constant 1 + constant 2 by transforming the above equation, and the value of current/constant 1 + constant 2 that is the minimum value of the equation is decided as a prescribed wire. Also, when a connection element is displayed while the means 11 is being operated, the wiring width is decided setting the minimum width as a default. In this way, the layout considering the electromigration and the stroke can be performed and also, processing speed can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout editor device used for IC layout design.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing a schematic configuration of a conventional layout editor device of this type. In the figure, reference numeral 1 is a common database that centrally manages each element and its layout information necessary for generating a circuit diagram and layout diagram, and connection information between each element, and 2 is a common database for accessing each element and An element for extracting the recognition information and its recognition information extracting means, 3 is an element connection information extracting means for extracting connection information between the elements by accessing the common database 1, 4 and 5 are elements and their recognition information extracting means. 2 and the information from the device connection information extracting means 3, respectively, to generate and display a circuit diagram and a layout diagram. Circuit diagram editing, display means and layout diagram editing, display means, 6 is wiring of wiring on the circuit diagram. Wiring width determining means for determining the width, and 7 is wiring spacing checking means for checking the wiring spacing of the wirings on the layout diagram.

The conventional layout editor device is constructed as described above, and the element and its recognition information extraction means 2 have an automatic initial placement function, and the element connection information extraction means 3 have an placement guidance function. That is, the element and its recognition information extraction means 2 recognize the element such as the transistor 8 and the resistor 9 on the circuit diagram as shown in FIG. 1 is extracted from the common database 1 as shown in FIG.
As shown in FIG. 2 (B), cells 8a and 9a for the layout diagram corresponding to the respective elements 8 and 9 on the circuit diagram on the layout diagram
To place. At this time, each cell 8 on the layout diagram
The relative positional relationship between a and 9a is as follows.
This is in agreement with the relative positional relationship of 9.

On the other hand, the element connection information extracting means 3 selects a terminal of an element to be wired on the circuit diagram or the layout diagram to search the common database 1 for a partner terminal to be connected to the terminal. Then, as shown by the X mark in FIG. 13B, the terminals and wirings are highlighted on the layout diagram to provide an index so that the layout designer does not make wiring mistakes. Further, the wiring width determining means 6 determines the fixed width determined by the designer based on the design rule of the process as the wiring width of the wiring 10 unless the designer changes the width. It is determined to be the wiring width of the wiring 10a. Furthermore, the wiring interval checking means 7 checks whether or not the minimum interval determined based on the process design rule is satisfied.

[0005]

Since the conventional layout editor device is constructed as described above, when the wiring is performed on the layout diagram, the wiring width determining means unless the designer changes the wiring width. Since the fixed width determined in 6 is not taken into consideration and the current value actually flowing in each wiring is not taken into consideration, there are problems such as disconnection and electromigration caused by exceeding the wiring capacitance when the current value becomes large. Further, the wiring interval is also checked by the wiring interval checking means 7 in consideration of only the design rule of the process without considering the signal passing through each wiring, so that there is a problem that crosstalk occurs when a large amplitude signal is parallel. was there.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a layout editor device capable of a layout in consideration of electromigration and crosstalk.

[0007]

A layout editor device according to claim 1 of the present invention includes a current value calculating means for calculating a current value flowing through each wiring by performing a circuit simulation using a circuit diagram, and each current value. And a wiring width determining means for determining the wiring width of each wiring and determining the wiring width of each wiring drawn on the layout diagram.

According to a second aspect of the present invention, a layout editor device uses a circuit diagram to perform a circuit simulation to calculate a frequency of a signal passing through each wiring, and a wiring interval between wirings from each frequency. And a wiring space check means for displaying an error on the layout diagram when the wiring space is smaller than the wiring space corresponding to the preset frequency.

The layout editor device according to claim 3 of the present invention is the layout editor device according to claim 2, wherein the frequency calculation means does not carry out a circuit simulation for a wiring judged to pass a signal that does not change. is there.

[0010]

The wiring width determining means of the layout editor device according to claim 1 of the present invention calculates the wiring width of each wiring from the current value of the current flowing through each wiring, and the wiring width of each wiring drawn on the layout diagram. To determine each.

According to the second aspect of the present invention, in the wiring interval checking means of the layout editor device, each wiring interval between the wirings is smaller than a wiring interval corresponding to a preset frequency from the frequency of the signal passing through each wiring. If
Display an error on the layout diagram.

The frequency calculating means of the layout editor device according to the third aspect of the present invention does not carry out the circuit simulation for the wiring which is judged to pass the unchanged signal.

[0013]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a schematic configuration of a layout editor device according to a first embodiment of the present invention. In the figure, the same parts as those of the conventional device shown in FIG. Reference numeral 11 is a current value calculation means for performing a circuit simulation using a circuit diagram to calculate the current value of the current flowing through each wiring, and 12 is this current value calculation means 11
It is a wiring width determining unit that calculates the wiring width of each wiring from each current value calculated by the above and determines the wiring width of each wiring drawn on the layout diagram.

Next, the operation of the current value calculating means 11 will be described with reference to the flow chart shown in FIG. First, circuit diagram connection information (hereinafter referred to as a netlist) obtained by circuit simulation of node numbers of elements on the circuit diagram
Extracted (Step S ₁₎ from. Then, the device having the same number as the extracted node number, that is, the transistor connected to the first extracted device is searched from the net list (step S ₂ ). 3 and 4 are diagrams showing examples of netlists and circuit simulation results.

When the transistor search is confirmed (step S ₃ ), the base terminal and collector terminal currents I _B and I _C output for each transistor are extracted as currents flowing through the terminals or wiring (step S ₃ ). S ₄ ) The current I _E flowing through the emitter is I _E = I _B + I _C
Can be found at. On the other hand, if the transistor search is not confirmed, the resistor is searched from the net list (step S ₅ ). Then, the search of the resistor is confirmed (Step S _6), Ru determined using a simulation result (Step S ₇₎ was determined current value from the voltage difference between the resistor ends (step S _8). Then, if the resistance cannot be confirmed in step S ₆ , that is, if the transistor and the resistance are not connected to the specified terminal or wiring, the connection element (none) is labeled (step S ₉ ).

In this way, when the current value of the current flowing through each wiring is calculated by the current value calculating means 11, the wiring width determining means 12 determines the wiring width of each wiring based on this current value. However, for example, when the relationship between the wiring width and the current value is defined as current ≦ constant 1 × (wiring width−constant 2) in the process design rule, if this equation is modified, wiring width ≧ current / current It becomes constant 1 + constant 2, and the minimum value of this equation, current / constant 1 + constant 2, is determined as the predetermined wiring width.

When the connection element (none) is marked in step S ₉ during the operation of the current value calculating means 11, the wiring width is determined by defaulting the minimum width of the process. Note that FIG. 5 shows an example in which the wiring widths of the wirings 13 and 14 are determined according to the current values of the currents flowing through the wirings as described above. Are formed differently because the current value of the current flowing through them is different.

Example 2. FIG. 6 is a block diagram showing the schematic arrangement of a layout editor device according to the second embodiment of the present invention. In the figure, the same parts as those of the device of the first embodiment shown in FIG. Reference numeral 15 is a frequency calculation means for performing a circuit simulation by using a circuit diagram to calculate the frequency of a signal passing through each wiring, and 16 is a wiring interval between the wirings in advance based on each frequency calculated by the frequency calculation means 15. It is a wiring interval checking means for displaying an error on the layout diagram when the wiring interval is smaller than the wiring interval corresponding to the set frequency.

Next, the operation of the frequency calculating means 15 and the wiring interval checking means 16 will be described based on the flow chart shown in FIG. First, the node number of the wiring on the circuit diagram is extracted from the net list obtained by the circuit simulation (step S ₁₁ ). Next, the frequency of the signal passing through the wiring of the extracted node number is calculated (step S
₁₂ ) Do. The frequency calculation in step S ₁₂ is
As shown in FIG. 8, in the circuit simulation as well, by using the result of the time base response called transient analysis, the time T ₁ and T _{When 2} , T ₃ , ..., Have almost the same value, it is judged that the signal is in a steady state and 1 / T≈1.
Let / T ₁ (≈1 / T ₂ ≈1 / T ₃ ) be the frequency of the signal.

Then, it is judged whether or not another wiring already exists on the layout diagram (step S ₁₃ ), and if the existence of another wiring is confirmed, the frequency of the other wiring is checked. difference determines whether exceeds a predetermined value determined in advance (step S _14). Now, previously prescribed value determined in step S ₁₄ is set, for example, a value such as several times the frequency of counterpart. Then, when it is confirmed that the difference between the two frequencies at step S ₁₄ exceeds a predetermined value, the wiring distance between the wiring and the mating of the wiring to be now wiring, in accordance with the pre-frequency difference determining whether exceeds the reference wiring interval are determined (step S _15). Then, when it is confirmed that the wiring interval does not exceed the reference wiring interval, that is, the wiring interval is not sufficient, as an error display (step S ₁₆ ), for example, as shown in FIG. The error mark 19 is displayed on. In addition, in each of steps S ₁₃ , S ₁₄ , and S ₁₅ , when it is confirmed that there is no other wiring, or when it is confirmed that the difference between the two frequencies does not exceed the predetermined value,
And if the wiring interval exceeds the standard wiring interval,
Wiring is drawn on each layout diagram (step S ₁₇ ).

Example 3. In the first embodiment, the case where the current value of the current flowing through each wiring is calculated by the current value calculating means 11 and the wiring width of each wiring is determined by the wiring width determining means 12 from the calculated current value. Further, in the second embodiment, the frequency of the signal passing through each wiring is calculated by the frequency calculating means 15, the difference between the frequencies of the signals passing through the wirings is obtained by the wiring space checking means 16, and the corresponding wirings between both wirings are calculated. The case where the error display is described when the wiring interval is narrower than the reference wiring interval predetermined according to the frequency difference has been described, but as shown in FIG.
Both the current value calculating means 11 and the frequency calculating means 15 are provided, and the wiring width determining means 12 and the wiring interval checking means 16 determine the wiring width of each wiring.
Needless to say, even if an error is displayed when the wiring interval is insufficient, the same effects as those of the above-described embodiments can be exhibited.

Example 4. In each of the above embodiments,
The case has been described in which the frequency of the signal passing through each wiring is calculated by the frequency calculating means 15 one by one. However, as in the case of the power supply, GND wiring, etc., the signal passing in advance is stable and stable. About what is known is also possible to omit the calculation of the frequency by the step S ₁₂ in FIG. 7, in this case, there is an effect that the processing speed can be shortened one step processing time increases.

Example 5. Furthermore, in each of the above embodiments, the case where the circuit simulation is performed by the current value calculation means 11 and the frequency calculation means 15 has been described.
Even if a means for performing circuit simulation is added in addition to Nos. 1 and 15, the same effect as each of the above-described embodiments is exhibited.

[0024]

As described above, according to claim 1 of the present invention, a current value calculating means for calculating a current value flowing through each wiring by performing a circuit simulation using a circuit diagram, and each current value from each current value A wiring width determining means for calculating the wiring width of the wiring and determining the wiring width of each wiring drawn on the layout diagram,

According to a second aspect of the present invention, there is provided a frequency calculation means for performing a circuit simulation using a circuit diagram to calculate a frequency of a signal passing through each wiring, and a wiring interval between the wirings from each frequency. A wiring interval check means for displaying an error on the layout diagram when the wiring interval is smaller than the preset frequency,

According to a third aspect of the present invention, in the second aspect, the frequency calculation means does not carry out the circuit simulation for the wiring which is determined to pass a signal that does not change. It is possible to provide a layout editor device capable of performing layout in consideration of migration and crosstalk and increasing processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a layout editor device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of a current value calculation means of the layout editor device shown in FIG.

FIG. 3 is a diagram showing a part of an example of a net list.

FIG. 4 is a diagram showing a part of an example of a circuit simulation result.

FIG. 5 is a layout diagram showing an example in which a wiring width of each wiring is determined according to a current value flowing in each wiring.

FIG. 6 is a block diagram showing a schematic configuration of a layout editor device according to a second embodiment of the present invention.

7 is a flowchart showing the operation of a frequency calculating means and a wiring interval checking means of the layout editor device shown in FIG.

FIG. 8 is a diagram showing a signal waveform that is periodically repeated.

FIG. 9 is a layout diagram showing an example of displaying an error by drawing an error mark between wirings.

FIG. 10 is a block diagram showing a schematic configuration of a layout editor device according to a third embodiment of the present invention.

FIG. 11 is a block diagram showing a schematic configuration of a conventional layout editor device.

FIG. 12 is for explaining the automatic initial placement function,
(A) is a circuit diagram and (B) is a layout diagram.

13A and 13B are diagrams for explaining a wiring guidance function, in which FIG. 13A is a circuit diagram and FIG. 13B is a layout diagram.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 common database 2 element and its recognition information extraction means 3 element connection information extraction means 4 circuit diagram input / edit, display means 5 layout diagram input / edit, display means 6, 12 wiring width determination means 7, 16 wiring interval check means 11 Current value calculating means 13, 14, 17, 18 Wiring 19 Error mark S _{1 to} S ₉ , S _{11 to} S ₁₇ steps

Claims (3)

[Claims] 1. A layout having an automatic initial placement function for generating a layout diagram from a circuit diagram edited based on input circuit information and a wiring guidance function for highlighting terminals to be wired on the layout diagram. In the editor device, a circuit simulation is performed using the circuit diagram to calculate a current value flowing through each wiring, and a wiring width of each wiring is calculated from each current value and drawn on the layout diagram. And a wiring width determining means for determining the wiring width of each of the wirings. 2. A layout having an automatic initial placement function for generating a layout diagram from a circuit diagram edited based on input circuit information and a wiring guidance function for highlighting terminals to be wired on the layout diagram. In the editor device, frequency calculation means for performing a circuit simulation using the circuit diagram to calculate the frequency of a signal passing through each wiring, and wiring for each wiring interval between the wirings corresponding to the preset frequency A layout editor device, comprising: wiring interval check means for displaying an error on the layout diagram when the distance is smaller than the interval. 3. The layout editor device according to claim 2, wherein the frequency calculation means does not perform a circuit simulation on the wiring that is determined to pass a signal that does not change.