JPH0635696A - Control device - Google Patents

Abstract

(57) [Abstract] [Purpose] The microprocessor accesses the peripheral I / O at an appropriate timing corresponding to the battery voltage to speed up the processing in the microprocessor. A voltage comparing means 9 compares respective output voltages of a reference voltage generating means 7 for generating a constant reference voltage from the output of the battery 5 and a voltage dividing means 8 for dividing the output voltage of the battery 5 at a constant ratio. Then, the active time width of the wait signal input from the wait signal generating means 10 to the microprocessor 1 is changed according to the output signal from the voltage comparing means 9. [Effect] The weight signal generating means 10 detects a change in the battery voltage, and the active time width of the wait signal input to the microprocessor 1 can be changed in accordance with the change in the battery voltage. The peripheral I / O can be accessed at an appropriate timing corresponding to the voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for peripheral I / O such as a memory by a microprocessor.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional control device. In FIG. 3, reference numeral 1 is a microprocessor whose access timing to a peripheral I / O is variable by inputting a wait signal from the outside.

First, the operation when the microprocessor 1 accesses a peripheral I / O will be described with reference to FIG. FIG. 4A is a timing chart showing the state of the machine cycle of the microprocessor in the non-wait state, and T1, T2, T are synchronized with the clock signal.
It consists of 3 states of 3.

The wait signal is sampled by the microprocessor at the falling edge of the clock in the T2 state. If it is "1", the wait signal is in the non-wait state, and the T3 state comes immediately after the T2 state. On the contrary, if it is "0", the Tw state is inserted immediately after the T2 state as shown in FIGS. Further, the wait signal is sampled even at the falling edge of the clock in the Tw state, and if it is "0", the Tw state is inserted next time, and the next state in which the wait signal is detected as "1" is the T3 state. Become.

Generally, a microprocessor outputs an address signal indicating an address to be accessed and an address enable signal indicating a timing at which the address signal is stable and valid. The address signal is output at the rising edge of the clock in the T1 state. Assume that the address enable signal changes from the falling edge of the clock in the T1 state to the falling edge of the clock in the T3 state, by controlling the active time width of the wait signal as described above.
The active time width of the address signal and the address enable signal can be controlled.

Since the signal which takes the AND condition of the address enable signal and the address signal is used as the chip select signal of the peripheral I / O, the peripheral I / O is eventually controlled by controlling the active time width of the wait signal.
The active time width of the chip select signal can be controlled.

Conversely, in order for the microprocessor to normally access the peripheral I / O whose access time changes, the active time width of the wait signal may be controlled.

In FIG. 3, reference numeral 2 is a peripheral I / O such as a memory, and 3 is an address decoder for generating a peripheral I / O chip select signal by ANDing an address signal output from a microprocessor and an address enable signal. Reference numeral 4 is an oscillator for supplying a clock signal to the microprocessor and the wait signal generating means, 5 is a battery for supplying power to the device, and 6 is a microprocessor for normal I / O to peripheral devices based on the clock signal and the chip select signal.
Is a wait signal generating means for generating a wait signal for accessing the.

Based on the above, the operation of the conventional control device will be described with reference to FIGS. 3 and 4B and 4C. A clock signal is supplied from the oscillator 4 to the microprocessor 1, and the microprocessor 1 accesses the peripheral I / O 2 in synchronization with this clock signal. When the microprocessor 1 attempts to access the peripheral I / O 2, the microprocessor 1 outputs the address signal in synchronization with the rising edge of the clock signal in the T1 state and outputs the address enable signal in synchronization with the falling edge of the clock signal. Output.

In the address decoder 3, a signal that satisfies the AND condition of this address signal and the address enable signal is generated, and this signal is output to the peripheral I / O 2 and the wait signal generating means 6 as a chip select signal. When the chip select signal becomes active, the peripheral I / O 2 has the exclusive right of the bus of the microprocessor 1, and the microprocessor 1 can be accessed. At this time, the wait signal generating means 6 recognizes that the peripheral I / O 2 has been accessed by the chip select signal, so that the wait signal is activated for the required time in synchronization with the clock signal supplied from the oscillator 4. Therefore, the Tw state is inserted in the machine cycle of the microprocessor 1, and as a result, the active time width of the chip select signal is extended and the access time of the peripheral I / O2 is guaranteed.

Here, how to set the active time width of the wait signal will be described. The power supply of the device is supplied by the battery 5, and the voltage of the battery 5 decreases as the usage time increases. On the other hand, it is known that the peripheral I / O2 typified by a memory or the like has a reduced power supply voltage and an increased access time. Therefore, the access time of the peripheral I / O2 increases as the usage time of the device increases.

From this, for example, when the device is started to be used, that is, when the battery voltage is maximum, the active time width of the wait signal is set to one cycle of the clock signal and one Tw state is inserted as shown in FIG. 4B. Although the access time could be guaranteed only by using the device, as the battery voltage drops when the device is used, if the voltage is below a certain value,
As shown in (C), it may be necessary to insert two Tw states. In such a case, since the conventional control device is not configured to notify the wait signal generating means of the decrease in the battery voltage, it corresponds to the access time of the peripheral I / O2 in the minimum value of the battery voltage range in which the device is used. The active time width of the wait signal that realizes the number of inserted Tw states is set.

[0013]

As described above, in the conventional control device, the active time width of the wait signal is set corresponding to the access time of the peripheral I / O at the minimum value of the battery voltage range in which the device is used. Therefore, the Tw state is inserted more than necessary even at the beginning of use of a device having a high battery voltage, which causes a problem of slowing down the processing in the microprocessor.

The present invention solves the above-mentioned problems, and a control in which the microprocessor can access the peripheral I / O at an appropriate timing corresponding to the voltage of the battery to speed up the processing in the microprocessor. The purpose is to provide a device.

[0015]

In order to achieve the above object, the control device of the present invention comprises a reference voltage generating means for generating a constant reference voltage from the output of the battery and a constant output voltage of the battery. A voltage dividing means for dividing voltage, a voltage comparing means for comparing the output voltage of the reference voltage generating means with the output voltage of the voltage dividing means, and an active wait signal input to the microprocessor according to the output signal from the voltage comparing means. A weight signal generating means for changing the time width is provided.

[0016]

According to the present invention, with the above configuration, the output voltage of the voltage dividing means for dividing the output voltage of the reference voltage generating means for generating a constant reference voltage regardless of the battery voltage and the output voltage of the battery at a constant ratio. By the voltage comparing means and transmitting the result as a signal to the weight signal generating means,
The wait signal generating means can detect whether or not the battery voltage has dropped below a certain voltage, and therefore the active time width of the wait signal input to the microprocessor can be changed according to the change in the battery voltage. .

[0017]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a control device according to the present invention. In FIG. 1, reference numeral 1 is a microprocessor, 2 is a peripheral I / O such as a memory, 3 is an address decoder, 4 is an oscillator, and 5 is a battery. However, the description is omitted.

Reference numeral 10 is a weight signal generating means for generating a weight signal according to a weight switching signal from a voltage comparing means 9 which will be described later on the basis of the clock signal and the chip select signal, and 7 is a constant reference voltage from the output of the battery. Reference voltage generating means such as a three-terminal regulator for generating, 8 is a voltage dividing means for dividing the output voltage of the battery at a constant ratio, and 9 is a comparison between the output voltage from the reference voltage generating means and the output voltage from the voltage dividing means. In the voltage comparison means, the weight switching signal is "0" when the output voltage from the reference voltage generating means 7 is higher and "1" when the output voltage from the voltage dividing means 8 is higher. Output to the generating means 10. In response to this, the wait signal generating means 10 outputs the wait switching signal "
If it is "1", a wait signal that is active for one cycle of the clock signal is output, and if the wait switching signal is "0", a wait signal that is active for two cycles of the clock signal is output.

Next, the operation of the control device of this embodiment will be described with reference to FIGS. 1 and 2. A clock signal is supplied from the oscillator 4 to the microprocessor, and the microprocessor 1 synchronizes with the clock signal to obtain the peripheral I / O.
Access to O2. When the microprocessor 1 attempts to access the peripheral I / O 2, the microprocessor 1 outputs the address signal in synchronization with the rising edge of the clock signal in the T1 state, and the address enable signal is output in synchronization with the falling edge of the clock signal. Is output.

The address decoder 3 generates a signal that satisfies the AND condition of this address signal and the address enable signal, and outputs this signal to the peripheral I / O 2 and the wait signal generating means 10 as a chip select signal. When the chip select signal becomes active, the peripheral I / O 2 has the exclusive right of the bus of the microprocessor 1, and the microprocessor 1 can be accessed. At that time, the wait signal generating means 10 knows that the peripheral I / O 2 has been accessed by the chip select signal. Therefore, in synchronization with the clock signal supplied from the oscillator 4, the wait signal active for the time corresponding to the wait switching signal is active. Generate. Therefore, the Tw state is inserted in the machine cycle of the microprocessor 1, and as a result, the active time width of the chip select signal is extended and the access time of the peripheral I / O2 is guaranteed.

FIG. 2 (A) shows a battery 5 at the beginning of use of the device.
Peripheral I / O of the microprocessor 1 when the voltage of the
2 is a timing chart showing how to access 2; at this time, the output voltage from the voltage dividing means 8 is still higher than the output voltage from the reference voltage generating means 7, and the weight switching signal is "1". Therefore, the wait signal generating means 10 becomes active for one clock signal cycle, one Tw state is inserted, and the active time width of the chip select signal is extended by that amount.

FIG. 2B is a timing chart showing how the peripheral I / O 2 of the microprocessor 1 is accessed when the voltage of the battery 5 drops after a considerable amount of time the device has been used. The output voltage from the reference voltage generating means 7 is higher than the output voltage from the voltage dividing means 8 and the weight switching signal is "0". Therefore, the wait signal generating means 10 becomes active for two clock signal cycles, two Tw states are inserted, and the active time width of the chip select signal is extended by that amount.

Here, at the battery voltage at which the access time of the peripheral I / O2 becomes larger than the active time width of the chip select signal when one Tw state is inserted, the voltage comparison means 9 is just "0". If the reference voltage of the reference voltage generating means 7 and the voltage dividing ratio of the voltage dividing means 8 are set so as to output the weight switching signal, the microprocessor 1 operates as the peripheral I / O at an appropriate timing corresponding to the voltage of the battery. Can be accessed to speed up the processing in the microprocessor 1.

[0024]

As described above, according to the present invention, the reference voltage generating means for generating a constant reference voltage from the output voltage of the battery, the voltage dividing means for dividing the output voltage of the battery at a constant ratio, and the reference voltage. A voltage comparison means for comparing the output voltage from the generation means with the output voltage of the voltage dividing means, and a weight signal generation means for changing the active time width of the wait signal input to the microprocessor according to the output signal from the voltage comparison means. Since the change in the battery voltage is detected by the weight generation means, it is possible to change the active time width of the wait signal input to the microprocessor according to the change in the battery voltage. It is possible to access the peripheral I / O at an appropriate and appropriate timing to speed up the processing in the microprocessor. That excellent control device is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a control device according to the present invention.

FIG. 2 is a timing chart of an embodiment of a control device according to the present invention.

FIG. 3 is a block diagram of a control device in a conventional example.

FIG. 4 is a timing chart of a control device in a conventional example.

[Explanation of symbols]

 1 Microprocessor 2 Peripheral I / O 3 Address Decoder 4 Oscillator 5 Battery 7 Reference Voltage Generating Means 8 Voltage Dividing Means 9 Voltage Comparing Means 10 Wait Signal Generating Means

Claims (1)

[Claims] 1. A microprocessor having a variable access timing to peripheral I / O by inputting a wait signal from the outside, a battery for supplying power to the device, and a reference for generating a constant reference voltage from the output of the battery. Voltage generating means, voltage dividing means for dividing the output voltage of the battery at a constant ratio, voltage comparing means for comparing the output voltage from the reference voltage generating means with the output voltage of the voltage dividing means, and the voltage comparison A control device comprising a wait signal generating means for changing an active time width of a wait signal input to the microprocessor according to an output signal from the means.