JPH065855A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor device that solves surface roughness during processing and maximizes the capability of a stacked diffusion layer type semiconductor device. A method of manufacturing a semiconductor device, which includes a step of depositing amorphous silicon as a stacked diffusion layer 3 and a step of separating a previously implanted impurity layer by self-alignment. [Effect] It is possible to prevent the surface of the substrate from being roughened during processing, and solve the problems such as the reduction of the current and the breakdown voltage of the gate oxide film due to the roughened surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a structure in which a diffusion layer region is stacked on a semiconductor substrate with high accuracy.

[0002]

2. Description of the Related Art Silicon LSI (Large Scale Integrat)
field effect transistors (MOSFET: Metal Oxide Semicon) made of metal / oxide film / semiconductor that have supported ed circuits
In the past, ductorField Effect Transistor) has achieved miniaturization of dimensions according to the basic concept of proportional reduction law. This proportional reduction rule is that the power supply voltage is reduced according to the size, the gate oxide film is thinned, and the diffusion layer Is made shallower and the concentration of the substrate is further increased. As the substrate concentration increases, the width of the depletion layer extending from the diffusion layer becomes smaller, and the distance between the diffusion layers can be narrowed. As a result, performance improvements such as lower power consumption and higher operating speed have been achieved.

However, as shown in FIG.
In MOSFET, a diffusion layer 6 is formed in the substrate, and
Since the ion implantation method is used for forming the diffusion layer, the diffusion depth is limited. Normally, 0.1μ
It is difficult to form a diffusion layer of m or less. In particular, in a p-type semiconductor device using holes as carriers, since a boron having a large diffusion coefficient is used, compared with an n-type semiconductor device in which an impurity having a small diffusion layer coefficient such as arsenic can be used, Becomes deeper. The depth of the diffusion layer affects the operable size of the semiconductor (the lateral size of the gate electrode indicated by 10 in FIG. 15), and the smaller the depth, the smaller the size.

The thinning of the gate oxide film 9 is determined by the tunnel leak of the oxide film, and the limit is about 4 nm. Furthermore, an increase in substrate concentration causes an increase in threshold voltage and causes performance deterioration such as an increase in diffusion layer capacitance and a decrease in diffusion layer withstand voltage.

From this point of view, it is considered that the MOSFET used so far has a limit of miniaturization of 0.2 to 0.3 μm in the gate dimension.

Here, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 6 is a diffusion layer, 9 is a gate oxide film, 10 is a gate electrode, 12 is an interlayer insulating film, 13 is a contact hole, and 14 is a wiring. is there.

On the other hand, a dynamic-random-access memory (DRAM), which is a representative of highly integrated memories,
For Random Access Memory), mass production of 16 megabits using 0.5 μm technology is currently being promoted. If high integration progresses at this pace, in the second millennium AD,
1 Gigabit memory is required, and the design size at this time must be 0.2 μm or less. However, as described above, there is a limit to miniaturization of the conventional MOSFET.

As a transistor structure capable of breaking through the miniaturization limit, a trench gate MOSFET shown in FIG. 16 has been proposed. This transistor structure is
As disclosed in JP-A-60-124874 and JP-A-62-35570, the structure is such that a part of the diffusion layer is stacked on the substrate 1 or the element isolation oxide film 2. The diffusion layer 6 inside the substrate is formed by using the impurity diffusion from here. Further, since the channel portion of the transistor is formed on the sidewall of the groove inside the substrate 1, the channel length can be changed according to the depth of the groove. For this reason, even if the planar dimension is the operation limit, the substantial channel length in the substrate is long, so that it is possible to create a MOSFET that operates stably.

Here, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 3 is a stacked silicon film, 4 is an insulating film, 6 is a diffusion layer inside the substrate, 8 is a sidewall insulating film, and 9 is a gate oxide film. Reference numeral 10 is a gate electrode, 12 is an interlayer insulating film, 13 is a contact hole, and 14 is a wiring.

[0010]

[Problems to be solved by the invention] Stacking type
In MOSFET, polycrystalline silicon 3 is deposited on the substrate 1,
There has been used a method of introducing impurities by using an ion implantation method and further diffusing the impurities by heat treatment. Known chemical vapor deposition methods have been used to deposit polycrystalline silicon. However, the polycrystalline silicon is composed of a large number of crystal grains like letters, and the surface of the deposited film has unevenness due to the difference in crystal orientation. This polycrystalline silicon is separated on the substrate in order to form a stacked diffusion layer, but since the same material as the substrate is used, the substrate can be dug.
At that time, the irregularities on the surface of the polycrystalline silicon are transferred to the substrate as they are, and the substrate region which becomes the channel is roughened. This MOSFET
Then, since this region becomes a channel as it is, the unevenness of the surface causes a performance deterioration such as a decrease in current and an increase in interface state.

Since the diffusion layer 6 inside the substrate is formed by impurity diffusion from the stacked polycrystalline silicon 3 as described above, the side wall for insulating the gate electrode 10 and the stacked polycrystalline silicon 3 from each other. The distribution of impurities under the oxide film 8 and the impurities at the source and drain ends must all be controlled by heat treatment. As shown in FIG. 16, in the case of a single MOSFET, one type of impurity diffusion may be considered, but generally, two types of MOSFETs having different conductivity types are used.
It is almost impossible to set the optimum heat treatment temperature for both impurities because they are complementary and have a mixture of. In particular, arsenic used in the n-type MOSFET and boron used in the p-type have very different diffusion coefficients, so that boron is excessively diffused at the optimum temperature for arsenic.

[0012]

[Means for Solving the Problems] As described above,
The stacked diffusion layer MOSFET shown in FIG. 16 has a possibility of breaking through the miniaturization limit of the conventional structure. However, in the manufacturing methods up to now, characteristic deterioration due to the roughening of the channel region and different types of MOSFETs can be avoided. At the same time, it has the drawback of being difficult to make on the same substrate.

The roughness of the substrate when separating the stacked diffusion layers is due to the fact that the stacked silicon is polycrystalline silicon. Since it is polycrystalline silicon, there are crystal grains with different crystal orientations in the film, and since the growth rates at the time of film formation are also different, the surface has irregularities. Therefore, in the present invention, amorphous silicon having no crystal grains is deposited instead of polycrystalline silicon. Since the surface of the amorphous silicon film is very smooth, the scraped substrate surface is kept smooth even when the stacked diffusion layers are separated. As a preferred embodiment of the present invention, a method of growing at 520 ° C. using a compound of silicon and hydrogen called disilane was used.

Next, impurities are ion-implanted into this amorphous silicon, and an oxide film (FIG. 16) is formed on the entire surface thereof.
The part indicated by 4. ) Is deposited. At this time, if the growth temperature is high, the amorphous silicon is polycrystallized. Therefore, in the present invention, a method capable of film growth at a temperature of 500 ° C. or lower is adopted.

Further, a part of the diffusion layer region in the substrate is formed by diffusing the stacked silicon films by heat treatment afterwards. As described above, in order to form different kinds of MOSFETs on the same substrate, the channel region is preliminarily ion-implanted with an impurity serving as a diffusion layer, and a groove is formed in the substrate to remove only the impurity region of the channel portion. Adopted the method.

[0016]

Since the surface of the deposited film is very smooth because it is amorphous silicon, even if the film is separated on a silicon substrate, the surface of the groove formed in the substrate is kept smooth. Be done. On the other hand, in the case of polycrystalline silicon, the surface irregularities are transferred to the substrate and the surface becomes rough. in this way,
The smooth surface is indispensable for improving the characteristics of the MOSFET, and can be realized only by using amorphous silicon. As a result of the smooth surface, the characteristics of the gate insulating film grown there are also markedly improved, and the withstand voltage is improved.

Furthermore, since the impurity distribution at the source / drain ends of the MOSFET can be adjusted by an ion implantation method with good controllability without depending much on the heat treatment, a complementary element can be easily manufactured.

[0018]

EXAMPLE A manufacturing method of a first example of the present invention will be described below.
This will be described with reference to FIGS. 1 to 14.

First, as shown in FIG. 1, a p-type semiconductor substrate 1 containing 5 × 10 ¹⁵ / cm ³ or more of boron as an impurity.
An element isolation oxide film 2 is grown only on a desired portion using a known selective oxide film growth method. The oxide film growth temperature is 1000 ° C., and the oxide film thickness is 250 to 350 n.
m. The selective oxidation method is a technique that utilizes the fact that the surface of a silicon substrate covered with a nitride film is not oxidized. At this time, using the nitride film as a mask, impurities of the same conductivity type as the substrate, in this case, boron are ion-implanted at a dose of about 1 × 10 ¹³ / cm ² . As a result, a high-concentration region higher than the substrate concentration is formed so as to surround the element isolation oxide film, and the element isolation characteristic is improved.

Next, as shown in FIG. 2, the surface of the semiconductor substrate is exposed, and the amorphous silicon 3 is chemically converted into a known chemical substance under the condition that an extremely thin oxide film such as a natural oxide film is not formed on this surface. It is deposited by the vapor deposition method. The procedure is as follows. First, the reaction furnace is set to a temperature of about 200 ° C., an inert gas such as nitrogen gas is sufficiently flown therein, and oxygen is completely expelled from the reaction furnace. Then, the substrate is loaded into the furnace while being careful not to trap oxygen in the atmosphere. Further, while the inside of the furnace is evacuated, the temperature is raised to about 520 ° C. When Si ₂ H ₆ (disilane) is introduced here, amorphous silicon 3 having a clean interface is deposited.
The film thickness was 100 nm. The amorphous silicon 3 is doped with impurities having a conductivity type different from that of the substrate 1, specifically, phosphorus.
Ion implantation was performed with a KeV and a dose amount of 2 × 10 ¹⁵ / cm ² . Under this condition, phosphorus remains in the amorphous silicon film and does not reach the substrate.

An oxide film 4 is deposited on the amorphous silicon film 3 as shown in FIG. This oxide film 4 is usually 75
It is grown at a temperature of about 0 ° C. using a known chemical vapor deposition method. However, at this temperature, the amorphous silicon film 3
Becomes polycrystal, and irregularities due to crystal grain boundaries occur at the interface with the oxide film 4. Although the unevenness is much smaller than that in the case where polycrystalline silicon is directly deposited, it is clear that the unevenness is transferred to the surface of the substrate 1 when the silicon film 3 is processed.

Further, since phosphorus is ion-implanted in the amorphous silicon film 3, even at a temperature of about 750 ° C., phosphorus can diffuse from the silicon film into the substrate and penetrate into the end of the element isolation oxide film 2. There is a nature. As will be described later, the impurities that have entered the substrate are removed at the time of etching the substrate, but the impurities that have penetrated into the end of the inter-element isolation oxide film 2 serve as a path for leak current, which is not preferable.

Therefore, in the present invention, a method of depositing an oxide film at 450 ° C. is adopted. Oxide film formation at 750 ° C,
The formation at 450 ° C is essentially the same, using chemical vapor deposition, but the former is usually done in a dilute gas atmosphere while the latter is grown at atmospheric pressure. .
Further, since the temperature is different, the denseness of the oxide film formed is also different. However, as will be described later, after the amorphous silicon film 3 is separated, a heat treatment at about 800 ° C. is applied, and thereafter, there is no great difference in the properties of the film.
Here, a 150 nm oxide film was deposited.

In the present embodiment, the stacked diffusion layer is made of a silicon film, but in order to further reduce the resistance, a stacked diffusion layer made of a stacked film of a silicon film and a metal silicide was also manufactured as a prototype. Also in this case, similarly, amorphous silicon is deposited, and tungsten silicide is deposited on the surface of the amorphous silicon by a known sputtering method. When the deposition temperature is about 350 ° C., the silicide film also remains amorphous. The film thickness is 50 nm for the silicon film and 50 nm for the silicide film.
Impurities are introduced into the silicon film by ion implantation through the silicide film.

Next, as shown in FIG. 4, the oxide film 4 and the amorphous silicon film 3 are separated into the source and drain of the stacked diffusion layer. Therefore, although not shown in the figure, an organic film that is sensitive to light was applied to the entire surface of the substrate, and a desired pattern was formed by using a known photolithographic technique. Using this as a mask, first, the oxide film 4 is etched by a known dry etching method to remove the organic film used as the mask, and then the oxide film 4 is used as a mask to form the underlying amorphous silicon. Membrane 3 was processed. The reason why the organic film is removed and the silicon film is processed using the oxide film as a mask is to improve the selectivity between the silicon film and the oxide film.

By the way, in the semiconductor device manufactured by the manufacturing method of the present invention, as will be described later, the gate electrode is formed in the gap between the stacked diffusion layers in a self-aligned manner. In order to manufacture a semiconductor device having a gate length of 0.1 to 0.15 μm, which is required at the level of 1 gigabit, it is preferable that the gap between the stacked diffusion layers is narrow in advance. That is, even though the gate length can be determined by self-alignment, if this gap is 0.5 μm, for example, as described later, if the sidewall oxide film is not 0.2 μm, the gate length is 0.1 μm. It won't be long. As a result, a parasitic resistance is connected to the source and drain of the semiconductor device, which causes characteristic deterioration.

Therefore, in the present invention, a known phase shift method is adopted. In the past, pattern formation was performed using light of the same phase, whereas the phase shift method positively utilizes the fact that the light intensity becomes zero by reversing the phase by 180 degrees, and thus the photolithography is performed. This is a method for realizing dimensions below the processing limit of. It is known that the phase shift method is particularly suitable for the step of separating into two islands as shown in FIG. Also in the present embodiment, by using this phase shift method, the stacked diffusion layers were successfully separated at intervals of about 250 nm, which is narrower than 365 nm which is the wavelength of photolithography.

By the way, since the stacked amorphous silicon 3 and the substrate 1 are made of the same material, the substrate is scraped to some extent during the processing of the amorphous silicon as shown in FIG. This is because the stacked diffusion layer is deposited on the inter-element isolation oxide film 2, and therefore the amorphous silicon film 3 must be excessively etched by the amount of steps during the processing. . In this embodiment, 0.05
The substrate was scraped by μm.

Next, in order to ion-implant an impurity having a conductivity type different from that of the substrate into the gap between the stacked diffusion layers 4,
As shown in FIG. 5, an oxide film 5 is deposited with a thickness of 10 nm to control the depth of impurities and prevent contaminants due to ion implantation from entering the substrate.
Since the oxide film 5 is as thin as 10 nm, a low pressure chemical vapor deposition method at 750 ° C. was adopted in order to form it with good uniformity. By the heat treatment during the formation of the oxide film, the amorphous silicon film 3 is changed to polycrystalline silicon, and further, part of phosphorus implanted in the silicon film diffuses into the substrate to form a diffusion layer. To do. In addition, the density of the oxide film on the silicon film 3 is improved by the effect of baking by the heat treatment.

Then, as shown in FIG. 6, a diffusion layer 7 of the same conductivity type as the diffusion layer 6 formed in the substrate is formed in the gap between the stacked diffusion layers 3 by using the ion implantation method. Specifically, arsenic capable of forming a shallow junction was implanted at an energy of 10 to 20 KeV and about 1 × 10 ¹⁵ / cm ² .

After removing the oxide film 5 which has become the protective film, as shown in FIG. 7, a nitride film 8 is deposited on the entire substrate by using the well-known low pressure chemical vapor deposition. Although the film thickness also depends on the distance between the stacked diffusion layers 3, in the present invention, the film thickness was adjusted so that the gap sandwiched by the sidewall nitride films 8 was 0.1 μm or less. Specifically, 0.0
A 5 to 0.1 μm nitride film was deposited. The deposition temperature of the nitride film 8 is 770 ° C., and during this process, the arsenic 7 implanted into the substrate is subjected to thermal annealing, the crystal defects associated with the ion implantation are repaired, and a slight amount. , Arsenic diffuses inside the substrate. The diffusion depth is
It is about 0.05 μm.

Next, when the entire surface of the nitride film 8 is etched by a known anisotropic etching method, as shown in FIG. 8, the nitride film 8 remains only on the sidewalls of the stacked diffusion layers 3 and 4, and the sidewall nitride film is formed. Is formed, the stacked diffusion layer is insulated in a self-aligned manner. At that time, the substrate region, which is a gap between the stacked diffusion layers, is exposed. Here, the reason why the nitride film is used to insulate the side wall is that the oxide film on the element isolation oxide film 2 and the stacked diffusion layer 3 is processed at the time of processing by utilizing the selection ratio with the underlying oxide film. This is to prevent 4 from being scraped.

The formation of the sidewall nitride film 8 exposes the substrate region in the gap between the stacked diffusion layers. Since arsenic has been previously implanted in this portion, the region in which the arsenic has been implanted is dug down, and the channel region exists at a position slightly deeper than the depth of the diffusion layer 7, as shown in FIG. To do so. Specifically, the substrate was dug to a depth of 0.06 μm by using a known anisotropic dry etching method. The effective channel length of the semiconductor device can be adjusted according to the depth to be dug into this substrate.

The substrate is damaged by the etching of the substrate, and if a gate oxide film or the like is formed as it is, it will cause a decrease in the interface state and the breakdown voltage. Since this damaged layer has a depth of several tens of liters from the surface, this damaged layer was removed by a known substrate surface cleaning method. Then, as shown in FIG. 10, a gate oxide film 9 is grown on the surface of the cleaned substrate. A silicon oxide film obtained by oxidizing the surface of the substrate can be used as the gate oxide film as in the conventional semiconductor device. However, in the method of manufacturing the semiconductor device, in order to suppress the diffusion layer 7 from expanding due to the heat treatment, a high temperature heat treatment is performed. An oxide film deposition method that does not require In particular, a tantalum oxide film was used in this example. Since the tantalum oxide film has a larger dielectric constant than the silicon oxide film, it is possible to effectively form a film thinner than the silicon oxide film. In particular, the silicon oxide film has a thinning limit of about 4 nm, but if a tantalum oxide film is used, it is effectively 2 to 3 n.
It is also possible to use an oxide film of m. In this embodiment, the thickness is set to 3 nm in terms of silicon oxide film.

A known reactive sputtering method was used for forming the tantalum oxide film. This method is a film forming method in which a tantalum target is sputtered with a mixed gas of argon and oxygen to deposit tantalum oxide on a substrate. Since the substrate is exposed to the plasma atmosphere, the substrate is easily damaged. Therefore, in this example, after forming the tantalum oxide film, heat treatment was performed in an oxygen atmosphere to grow a thin silicon oxide film at the interface between the tantalum oxide and the substrate. As a result, the interface characteristics are improved to the level of the silicon oxide film.

Next, as shown in FIG. 11, the gate electrode 10 is deposited on the entire surface. As described above, since the tantalum oxide film is used for the gate oxide film 9 in this embodiment, tungsten that does not react with the tantalum oxide film is used for the gate electrode. In conventional semiconductor devices, polycrystalline silicon containing impurities has been used, but polycrystalline silicon is
Since it has a property of depriving oxygen from the tantalum oxide film,
It cannot be used for this structure. By the way, the sheet resistance of tungsten is 1Ω / □, and the sheet resistance of polycrystalline silicon is 50
Much smaller than Ω / □. As a result, there is an advantage that the gate resistance is reduced.

As shown in FIG. 12, a photo-sensitive organic film 11 is applied thereon to form a gate electrode pattern, which is then used as a mask to process the underlying tungsten 10. When processing tungsten, the oxide film 4 on the stacked diffusion layer 3 serves as a base, and the gate electrode is not exposed to processing. In this way, processing the gate electrode 10
One of the features of the method of manufacturing the present semiconductor device is that it is not necessary to perform it on the thin gate insulating film 9. Therefore, even if the selection ratio is not so large, such as the tungsten electrode and the tantalum oxide film, the gate electrode can be processed without damaging the substrate.

Next, as shown in FIG. 13, an interlayer insulating film 12 is deposited on the surface. In the present invention, flattening was performed by depositing a laminated film of an oxide film containing about 4 mol% of phosphorus and organic glass. The film thickness of the laminated film is 0.5 μm. As shown in the figure, the contact hole 1 is formed in the interlayer insulating film 12.
3 is opened to expose the stacked diffusion layer 3. Although not shown in this sectional view, contact holes are also opened in the gate electrode 10 and the semiconductor substrate 1.

Finally, fill this contact with metal,
The wiring pattern as shown in FIG. 14 is formed, and the semiconductor device manufacturing method of the present invention is completed. In addition, in metal,
Aluminum containing silicon was used.

Next, a method of manufacturing a complementary semiconductor device using the method of manufacturing a semiconductor device of the present invention will be described. In the complementary semiconductor device, semiconductor devices having different conductivity types are formed on the same substrate, but the essential manufacturing method is the same as that of the single semiconductor device described above.

First, regions having different conductivity types are formed on the same semiconductor substrate surface. Here, details of the manufacturing method are not mentioned, but the outline is as follows. First, a nitride film is deposited on the surface of the substrate, and one of the substrate regions having the conductivity type is opened. Here, phosphorus ions are added in an amount of 1 to 10 × 10 ¹² / cm.
Type in about ² . This region becomes the n-type 103. When the surface is oxidized after ion implantation, an oxide film grows on the surface of the n-type region not covered with the nitride film. When the nitride film used as the mask for the selective oxidation is removed, an oxide film grows in the n-type region. With this as a mask, the remaining region is implanted with boron at about 1 to 10 × 10 ¹² / cm ^2. . This region becomes the p-type 102. Then, heat treatment is applied to the substrate so that the diffusion depth becomes a desired value. Thereby, two conductive type regions can be formed with one mask.

After the two conductivity type regions are formed on the same substrate as described above, the inter-element isolation oxide film 2 is formed by the selective oxidation method as shown in FIG.

The surface of the substrate was cleaned and the entire surface was removed as shown in FIG.
Amorphous silicon is deposited as shown in FIG. And
As shown in the figure, an organic film mask 11 is formed in one conductivity type region, and impurities are ion-implanted into the exposed silicon film 3. Here, in the region where the substrate is the p-type 102, phosphorus is implanted in the silicon film, and in the silicon film on the n-type 103 region, boron is implanted. The dose amount of ion implantation is 1 to 5 × 10 ¹⁵ / cm ² in both cases. The implantation energy is set so that the impurity ions do not reach the substrate.

After removing the surface contamination and the like due to the ion implantation, an oxide film 4 is deposited on the entire substrate as shown in FIG. As described above, the deposition temperature is the silicon film 3
A deposition method at 450 ° C. was used to prevent impurity diffusion from the substrate.

Next, as shown in FIG. 20, the silicon film 3 and the oxide film 4 are separated into stacked diffusion layers. Again, as described above, the phase shift method was used to separate the gap into 0.2 μm. At this time, the substrate is scraped by about 50 nm.

After the contamination and the like caused by the processing of the stacked diffusion layers are removed by using a cleaning method, the oxide film 5 to be the contamination prevention film and the ion depth control film in the next ion implantation step is formed on the entire substrate. Is deposited to a thickness of 10 nm (FIG. 21). As described above, the oxide film growth method at 750 ° C. was used to deposit this film. In the process of this heat treatment, the accumulated diffusion layers 3
Changes from amorphous to polycrystalline, and the impurities in the silicon film 3 diffuse into the substrate.

Next, as shown in FIG. 22, impurities are ion-implanted in advance in the gaps between the stacked diffusion layers 3 which will be the channel regions, in order to form diffusion layers. Since the substrates have different conductivity types, one region is covered with the organic film 11 and this is used as a mask. For p-type substrates, 2 arsenic
Implantation was carried out under the conditions of 0 KeV and 2 × 10 ¹⁵ / cm ² , and for an n-type substrate, boron was used as BF ₂ and 20 KeV and 2 × 1 were used.
Ion implantation was performed under the condition of 0 ¹⁵ / cm ² . As a result, the diffusion layer region 7 is formed as shown in FIG.

After removing contaminants and the like due to ion implantation by a cleaning method, as shown in FIG.
A nitride film 8 to be a sidewall insulating film is deposited to a film thickness of 100 nm. The formation temperature is 750 ° C.

When the entire surface of this nitride film is etched, the structure shown in FIG.
As shown in FIG. 4, the nitride film remains only on the side wall of the stacked diffusion layer having a step on the surface, and the side wall nitride film 8 is formed.
At this time, the substrate region, which is the gap between the stacked diffusion layers and becomes the channel region, is exposed.

Then, as shown in FIG. 25, only the exposed substrate portion is dug down to remove the impurity layer 7 in the region to be the channel while protecting the diffusion layer under the sidewall nitride film 8. By this step, the diffusion layer of the semiconductor device is separated. The depth of digging the substrate depends on the depth of the impurity layer, but since both n-type and p-type are about 0.05 μm,
In this embodiment, the substrate is dug by 0.05 to 0.06 μm.

Next, after removing the damage on the surface due to the processing of the substrate and cleaning, the tantalum oxide film 9 is deposited as a gate oxide film as described in the first embodiment (see FIG. 26). As described above, by depositing a tantalum oxide film using the reactive sputtering method and further performing heat treatment in an oxygen atmosphere, a thermal oxide film having excellent interface characteristics between the tantalum oxide film and the semiconductor substrate is formed. Grow. This treatment improves the interface characteristics and breakdown voltage of the gate oxide film.

Next, as shown in FIG. 27, tungsten is deposited as the gate electrode 10, and this is processed into a desired gate electrode shape as shown in FIG.

Further, as shown in FIG. 29, the whole surface of the substrate is covered with an interlayer insulating film 12, and a contact hole 13 is opened in this.

Finally, as shown in FIG. 30, the wiring layer 14 is formed to complete the manufacturing method of the complementary semiconductor device of the present invention.

Next, the mask pattern required for manufacturing the semiconductor device of the present invention will be described.

FIG. 31 shows a mask pattern necessary for manufacturing a complementary semiconductor device. First, using a pattern of 40, a first conductivity type substrate region is formed in a region surrounded by the pattern, and a second conductivity type substrate region is formed in the other region. The specific method is as described above. Next, an inter-element isolation oxide film is formed.
The pattern of 1 is used. The nitride film on the substrate is processed into this pattern and serves as a mask for selective oxidation, so that an element activation region is formed only in the region surrounded by this pattern. At the time of selective oxidation, there is a thin oxide film also in the region surrounded by the pattern 41 which becomes the active region, so the pattern 42 is used to remove this. As a result, the oxide film on the active region can be removed without thinning the inter-element isolation oxide film.

Next, a stacked diffusion layer is deposited. Then, using the pattern 44, ion implantation is performed to obtain a desired conductivity type. Specifically, boron is implanted in the region 44 to make it p-type, and arsenic is implanted in the other region to make n.
Use as a mold. Furthermore, this is separated using the pattern 43. An impurity layer to be a diffusion layer is preliminarily ion-implanted into a semiconductor substrate region to be a channel, and a sidewall nitride film of a stacked diffusion layer is formed. However, since this is performed by self-alignment, no mask pattern is required. . However, in order to prevent impurities from being introduced into the ends of the inter-element isolation oxide film when forming the impurity layer, patterns 48 and 49 are used at the time of ion implantation. Two types of patterns are required because the substrates have different conductivity types. And 4
A gate electrode is formed by using the pattern of 5, the contact hole is opened by the pattern of 46, and finally wiring is formed by the pattern of 47.

Although the embodiments of the present invention have been described with respect to the manufacturing method of the single and complementary type semiconductor devices, this manufacturing method can be applied to all the semiconductor devices to which the stacked diffusion layer type semiconductor device is applicable, that is, the DRAM. A logic L typified by a typical semiconductor memory or a microprocessor
It is applicable to the manufacture of SI and the like.

[0059]

When amorphous silicon is used as the silicon film of the stacked diffusion layer, it is possible to solve the biggest problem that the performance is deteriorated, that is, the roughness of the substrate during the processing. Therefore, in the stacked diffusion layer type semiconductor device manufactured by this method, a decrease in current or the like is not observed even compared with the conventional semiconductor devices in which the channel region is not exposed to processing. Further, unlike the conventional method of controlling the impurity distribution by heat treatment, the complementary semiconductor is a method in which impurities are ion-implanted in the channel region in advance and trenches are formed in the substrate to separate the diffusion layers. Another feature is that the device is easy to make.

As a result, a semiconductor device having a gate length of about 0.1 μm can be stably manufactured by the conventional method, and a gigabit class memory and a logic circuit are realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view of a conventional semiconductor device.

FIG. 16 is a cross-sectional view of a conventional stacked-type diffusion layer semiconductor device.

FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 30 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 31 is a plan view of a mask pattern for forming a complementary semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation oxide film, 3 ... Stacked diffusion layer, 4 ... Oxide film, 5 ... Oxide film, 6 ... Diffusion layer, 7 ... Diffusion layer, 8 ... Sidewall nitride film, 9 ... Gate oxide film Reference numeral 10 ... Gate electrode, 11 ... Organic film, 12 ... Interlayer insulating film, 13 ... Contact hole, 14 ... Wiring metal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Dai Hisamoto 1-280, Higashi Koikekubo, Kokubunji, Tokyo

Claims (6)

[Claims] 1. A first-conductivity-type semiconductor substrate having an element isolation region has second-conductivity-type semiconductor regions formed at certain intervals, and is in contact with the semiconductor substrate through a gate insulating film. A method for manufacturing a semiconductor device, wherein a current flowing between the second-conductivity-type semiconductor regions is controlled by applying a voltage to a gate electrode, wherein an amorphous second-conductivity-type conductor is provided on the semiconductor substrate. A step of depositing a laminated film of an insulating film, a step of separating the laminated film to form the semiconductor region of the second conductivity type, and a step of separating the semiconductor substrate from the semiconductor substrate through a separation groove of the laminated film. Ion-implanting different impurities, a step of covering only the side wall of the laminated film with an insulating film, a step of digging a substrate portion not covered with the side-wall insulating film to separate an impurity-implanted region, and a substrate surface Gate insulation film Forming step, forming a gate electrode in contact with the gate insulating film, forming an interlayer insulating film covering the gate electrode, penetrating the interlayer insulating film, the gate electrode and the second conductive film. Mold laminated film,
And a step of forming an opening reaching the semiconductor substrate, and forming a wiring in contact with the gate electrode, the second conductive type laminated film, and the semiconductor substrate through the opening. Manufacturing method. 2. The laminated film forming a part of the second conductivity type according to claim 1, wherein the laminated film of amorphous silicon containing an impurity of the second conductivity type and an insulating film, or the second conductivity type. A method of manufacturing a semiconductor device comprising a laminated film of an amorphous silicon containing an impurity, a metal silicide, and an insulating film. 3. The silicide according to claim 2, wherein the metal silicide is
A method for manufacturing a semiconductor device, which is a compound of silicon with a metal such as tungsten, molybdenum, cobalt, titanium, and nickel. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the sidewall insulating film covering the sidewall of the laminated film forming a part of the second conductivity type is a nitride film. 5. The gate insulating film according to claim 1, comprising a silicon oxide film or a laminated film of a silicon oxide film and tantalum pentoxide, and the gate electrode further comprises a polycrystalline silicon film containing impurities and an impurity. A method for manufacturing a semiconductor device comprising a laminated film of a polycrystalline silicon film containing a metal silicide and a refractory metal film of tungsten or molybdenum. 6. The semiconductor device according to claim 1, wherein:
A method of manufacturing a semiconductor device, wherein semiconductor regions having different conductivity types are present, and semiconductor devices having different conductivity types from those of the semiconductor substrate are simultaneously formed in the respective semiconductor regions.