JPH0670990B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0670990B2 JPH0670990B2 JP28986588A JP28986588A JPH0670990B2 JP H0670990 B2 JPH0670990 B2 JP H0670990B2 JP 28986588 A JP28986588 A JP 28986588A JP 28986588 A JP28986588 A JP 28986588A JP H0670990 B2 JPH0670990 B2 JP H0670990B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- semiconductor device
- edge portion
- reflow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 8
- 239000005380 borophosphosilicate glass Substances 0.000 description 28
- 238000010438 heat treatment Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の製造方法にかかるものであり、
特に、VLSIなどに応用される絶縁膜のリフロー処理の改
良に関するものである。The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to improvement of reflow treatment of insulating film applied to VLSI and the like.
［従来の技術］ 半導体装置、特にVLSIにおいては、デバイスの微細化が
進んで構造が複雑となり、シリコンウエハ表面の凹凸も
一層激しくなる。すなわち、表面の凹凸の高低差が従来
のものよりも一層大きくなる。そして、更に、この高低
差を有する表面上に、各種の膜を均一に形成する必要が
ある。[Prior Art] In a semiconductor device, especially in a VLSI, the device becomes finer, the structure becomes complicated, and the unevenness of the surface of the silicon wafer becomes more severe. That is, the height difference of the surface irregularities becomes larger than that of the conventional one. Further, it is necessary to uniformly form various films on the surface having the height difference.
特に、金属膜の場合は、凹凸の段差部分で断線が生じた
り、膜厚が薄くなったりして、デバイスの信頼性に著し
い影響を与える恐れがある。そこで、金属膜形成、すな
わちメタライゼーションの前に絶縁膜ないし誘電膜の表
面の凹凸を滑らかにするため、リフロー処理が行なわれ
る。In particular, in the case of a metal film, disconnection may occur at the step portion of the unevenness or the film thickness may become thin, which may significantly affect the reliability of the device. Therefore, a reflow treatment is performed before the metal film is formed, that is, metallization, in order to smooth the unevenness of the surface of the insulating film or the dielectric film.
このリフロー処理については、例えば、ソリッドステー
トテクノロジー（Solid State Technology）／日本版,1
984年,4月号「VLSI応用へのPECVDボロンリンガラス膜プ
ロセスと膜の評価」において検討されている。For this reflow process, see, for example, Solid State Technology / Japan version, 1
This is discussed in the April, 984 issue, "PECVD Boron Phosphorus Glass Film Process and Film Evaluation for VLSI Applications."
第３図には、MOSトランジスタにおけるリフロー処理の
従来例が示されている。同図において、Si基板10上に
は、ゲート酸化膜12を挟んでゲート電極14が形成され
る。次に、ゲート酸化膜12,ゲート電極14上には、層間
絶縁膜としてリンやボロンの不純物を含むSiO2膜、いわ
ゆるBPSG膜16が形成される。そして、RIE（リアクティ
ブ・イオン・エッチング）により、BPSG膜16及びゲート
酸化膜12の一部が各々エッチングされ、コンタクトホー
ル18が形成される。この状態が同図(A)に示されてい
る。FIG. 3 shows a conventional example of reflow processing in a MOS transistor. In the figure, a gate electrode 14 is formed on a Si substrate 10 with a gate oxide film 12 interposed therebetween. Next, on the gate oxide film 12 and the gate electrode 14, a so-called BPSG film 16, which is an SiO 2 film containing impurities such as phosphorus or boron, is formed as an interlayer insulating film. Then, the BPSG film 16 and a part of the gate oxide film 12 are each etched by RIE (reactive ion etching) to form a contact hole 18. This state is shown in FIG.
この状態で、水蒸気，酸素，又は窒素雰囲気中で熱処理
が行なわれる。これによって、BPSG膜16の表面が熔融
し、同図(B)に示すように、BPSG膜16のコンタクトホー
ル側のエッジ部分20,22が丸みを帯びるようになる。In this state, heat treatment is performed in a steam, oxygen, or nitrogen atmosphere. As a result, the surface of the BPSG film 16 is melted, and the edge portions 20 and 22 of the BPSG film 16 on the contact hole side are rounded as shown in FIG.
これによって、Al等の配線材料のステップカバレージが
改善され、断線等の不良の発生が低減される。This improves the step coverage of the wiring material such as Al and reduces the occurrence of defects such as disconnection.
［発明が解決しようとする課題］ しかしながら、以上のような従来のリフロー処理法で
は、第４図(A)に示すように、フローが矢印FAで示す方
向にのみ進行するため、BPSG膜16のエッジ部分に十分な
丸みないしテーパ形状が得られない。[Problems to be Solved by the Invention] However, in the conventional reflow processing method as described above, as shown in FIG. 4 (A), the flow proceeds only in the direction indicated by the arrow FA, so that the BPSG film 16 is not removed. Sufficient roundness or taper cannot be obtained at the edge.
これに対し、高温，長時間の熱処理を行なうようにする
と、エッジ部分になだらかな丸み形状を形成することが
できる。しかし、この場合には、同図(B)に示すよう
に、エッジ部分に異常な膨らみ24が生じ、必ずしも好ま
しいとは言えない結果となる。更に、このような高温，
長時間の熱処理は、Si基板10内に注入した不純物の再拡
散を招き、半導体装置の特性に悪い影響を及ぼすという
不都合もある。On the other hand, when heat treatment is performed at high temperature for a long time, a gentle rounded shape can be formed at the edge portion. However, in this case, as shown in FIG. 7B, an abnormal bulge 24 is generated at the edge portion, which is not necessarily preferable. Furthermore, such high temperatures,
The heat treatment for a long time also causes the diffusion of impurities implanted into the Si substrate 10 and adversely affects the characteristics of the semiconductor device.
本発明は、かかる点に鑑みてなされたもので、比較的低
温，短時間の熱処理で一層効果的なリフロー処理を行な
ってステップカバレージの向上を図ることができる信頼
性の高い半導体装置の製造方法を提供することを、その
目的とするものである。The present invention has been made in view of the above points, and is a method of manufacturing a highly reliable semiconductor device capable of improving the step coverage by performing a more effective reflow process by a heat treatment at a relatively low temperature for a short time. The purpose is to provide.
［課題を解決するための手段］ 本発明のひとつは、基板主面上に形成されたエッジ部分
を有する膜体に対し、そのエッジ部分に丸み形状を形成
するリフロー処理が行なわれる半導体装置の製造方法に
おいて；前記エッジ部分の形成時に、除去すべき膜体の
一部を残す工程を含み、この工程の後に前記リフロー処
理を行なうことを特徴とするものである。[Means for Solving the Problems] One of the aspects of the present invention is to manufacture a semiconductor device in which a film body having an edge portion formed on a main surface of a substrate is subjected to a reflow process for forming a rounded shape at the edge portion. The method is characterized by including a step of leaving a part of the film body to be removed at the time of forming the edge portion, and performing the reflow treatment after this step.
他の発明は、基板主面上に形成されたエッジ部分を有す
る第１の膜体に対し、そのエッジ部分に丸み形状を形成
するリフロー処理が行なわれる半導体装置の製造方法に
おいて；前記基板の表面のうち，前記エッジ部分の形成
時に前記第１の膜体が除去された部分に酸化膜を形成す
る工程と；この工程の基板主面上に，前記第１の膜体に
含まれる不純物と同一不純物を一種類以上含む第２の膜
体を形成する工程とを各々含み；これらの工程の後に前
記リフロー処理を行なうことを特徴とするものである。Another invention is a method for manufacturing a semiconductor device, in which a first film body having an edge portion formed on a main surface of a substrate is subjected to a reflow process for forming a rounded shape at the edge portion; A step of forming an oxide film in a portion where the first film body is removed at the time of forming the edge portion; and the same impurities as those contained in the first film body on the main surface of the substrate in this step. And a step of forming a second film body containing one or more kinds of impurities; the reflow treatment is performed after these steps.
［作用］ 本発明のひとつによれば、半導体装置、例えばMOSトラ
ンジスタのコンタクトホールにおけるBPSG膜は、完全に
は除去されず、一部が残された状態でリフロー処理が行
なわれる。[Operation] According to one aspect of the present invention, the BPSG film in the contact hole of the semiconductor device, for example, the MOS transistor is not completely removed, and the reflow process is performed with a part left.
他の発明によれば、前記BPSG膜が完全に除去されたコン
タクトホールの基板表面に熱酸化膜が形成され、更に、
この基板主面上にBPSG膜に含まれる不純物と同一の不純
物を一種類以上含む他の膜、例えばBPSG膜が形成され
る。そして、その後にリフロー処理が行なわれる。According to another invention, a thermal oxide film is formed on the substrate surface of the contact hole where the BPSG film is completely removed.
On this main surface of the substrate, another film containing one or more kinds of impurities identical to those contained in the BPSG film, for example, a BPSG film is formed. Then, the reflow process is performed thereafter.
いずれであれ、BPSG膜はコンタクトホール側にもフロー
する。In any case, the BPSG film also flows to the contact hole side.
［実施例］ 以下、本発明の実施例について、添付図面を参照しなが
ら説明する。なお、上述した従来例と同様の構成部分に
ついては、同一の符号を用いることとする。EXAMPLES Examples of the present invention will be described below with reference to the accompanying drawings. The same reference numerals are used for the same components as those of the conventional example described above.
〈第１実施例〉 最初に、第１図を参照しながら、本発明の第１実施例に
ついて説明する。第１図には、第３図に示したMOSトラ
ンジスタのコンタクトホール18部分が拡大して示されて
いる。<First Embodiment> First, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows an enlarged view of the contact hole 18 portion of the MOS transistor shown in FIG.
同図において、Si基板10上には、まず、熱酸化などの方
法でゲート酸化膜12が形成され、更にその上に、BPSG膜
16の堆積が行なわれる（同図(A)参照）。そして、上述
したRIEによってBPSG膜16の一部のエッチングが行なわ
れ、コンタクトホール18の形成が行なわれる。In the figure, a gate oxide film 12 is first formed on the Si substrate 10 by a method such as thermal oxidation, and a BPSG film is further formed thereon.
16 deposits are made (see FIG. 3A). Then, part of the BPSG film 16 is etched by the above-mentioned RIE, and the contact hole 18 is formed.
このとき、BPSG膜16は、コンタクトホール相当部分の全
体がエッチングされずに、一部が残される（同図(B)参
照）。残されたBPSG膜16の厚さは、例えば約2000Å程度
である。At this time, the BPSG film 16 is not entirely etched in the portion corresponding to the contact hole, but is left in part (see FIG. 6B). The thickness of the remaining BPSG film 16 is, for example, about 2000Å.
このような状態で、上述したようにしてリフロー処理が
行なわれる。すなわち、水蒸気，酸素，又は窒素雰囲気
中で、Si基板10の主面の熱処理が行なわれる。これによ
って、BPSG膜16の表面が熔融することとなる。In such a state, the reflow process is performed as described above. That is, the heat treatment of the main surface of the Si substrate 10 is performed in an atmosphere of water vapor, oxygen, or nitrogen. This causes the surface of the BPSG film 16 to melt.
ところが、同図(B)に示すようにSi基板10の主面全体がB
PSG膜16によって覆われているので、上述した従来技術
よりも濡れ性がよい。このため、同図(C)に矢印FB,FCで
示す両方向、すなわち山側のみならず谷側にもフローす
るようになる。However, the entire main surface of the Si substrate 10 is
Since it is covered with the PSG film 16, it has better wettability than the above-mentioned conventional technique. Therefore, the flow will flow in both directions shown by arrows FB and FC in FIG. 6C, that is, not only on the mountain side but also on the valley side.
従って、エッジ部分30には、従来と同様もしくはそれ以
下のリフロー条件で良好に丸み形状が形成されることと
なり、第４図(B)に示したような膨らみは生じない。ま
た、従来と同等の丸み形状を得るとした場合でも、より
低温，短時間の処理を行なうのみでよい。Therefore, the edge portion 30 has a good rounded shape under the reflow condition similar to or lower than the conventional one, and the bulge shown in FIG. 4 (B) does not occur. Further, even if the rounded shape equivalent to the conventional one is obtained, it is only necessary to perform the processing at a lower temperature for a shorter time.
以上のリフロー処理の後、同図(D)に矢印FDで示すよう
に、主体全面に対してRIEが行なわれ、コンタクトホー
ル部分のBPSG膜16,ゲート酸化膜12が各々除去されて、
コンタクトホール18が完全に形成される。After the above reflow treatment, as shown by an arrow FD in FIG. 3D, RIE is performed on the entire surface of the main body to remove the BPSG film 16 and the gate oxide film 12 in the contact hole portion,
The contact hole 18 is completely formed.
このように、第１実施例によれば、次のような効果があ
る。As described above, according to the first embodiment, the following effects can be obtained.
(1)従来よりも低温，短時間で良好なリフロー効果が得
られる。(1) A good reflow effect can be obtained at a lower temperature and in a shorter time than before.
(2)層間絶縁膜であるBPSG膜の主成は、通常通り一回で
すむ。(2) The BPSG film, which is an interlayer insulating film, needs to be formed only once as usual.
(c)層間絶縁膜とSi基板10との境界面もなだらかにな
る。従って、Al等の配線材料の断線の発生が良好に低減
され、デバイスの信頼性が向上してサブミクロンコンタ
クトへの対応が可能となる。(c) The boundary surface between the interlayer insulating film and the Si substrate 10 also becomes gentle. Therefore, the occurrence of disconnection of the wiring material such as Al is favorably reduced, the reliability of the device is improved, and the submicron contact can be dealt with.
〈第２実施例〉 次に、第２図を参照しながら、本発明の第２実施例につ
いて説明する。なお、上述した従来例ないし第１実施例
と同様ないし相当する構成部分には、同一の符号を用い
ることとする。<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIG. The same reference numerals are used for the same or corresponding components as those of the above-mentioned conventional example or the first example.
同図において、Si基板10上には、第１実施例と同様に、
熱酸化などの方法でゲート酸化膜12が形成され、更にそ
の上に、BPSG膜16の堆積が行なわれる（同図(A)参
照）。そして、上述したRIEによってBPSG膜16の一部の
エッチングが行なわれ、コンタクトホール18の形成が行
なわれる（同図(B)参照）。In the figure, on the Si substrate 10, as in the first embodiment,
A gate oxide film 12 is formed by a method such as thermal oxidation, and a BPSG film 16 is further deposited on the gate oxide film 12 (see FIG. 3A). Then, a part of the BPSG film 16 is etched by the above-mentioned RIE to form the contact hole 18 (see FIG. 7B).
次に、後述するリフロー処理時におけるBPSG膜16からの
リンやボロンの拡散を防止するために、Si基板10のコン
タクトホール表面に数100Åの熱酸化膜40が形成される
（同図(C)参照）。そして、更に、Si基板10の主面全体
に2000Å程度のBPSG膜42の堆積が行なわれる（同図(D)
参照）。Next, a thermal oxide film 40 of several hundred Å is formed on the contact hole surface of the Si substrate 10 in order to prevent the diffusion of phosphorus and boron from the BPSG film 16 at the time of reflow processing described later (FIG. (C)). reference). Then, a BPSG film 42 of about 2000 Å is further deposited on the entire main surface of the Si substrate 10 (FIG. (D)).
reference).
この状態において、上述したリフロー処理が行なわれ
る。すなわち、水蒸気，酸素，又は窒素雰囲気中で、Si
基板10の主面の熱処理が行なわれる。これによって、BP
SG膜42の表面が熔融することとなる。In this state, the reflow process described above is performed. That is, in an atmosphere of water vapor, oxygen, or nitrogen, Si
The heat treatment of the main surface of the substrate 10 is performed. This allows BP
The surface of the SG film 42 will melt.
この第２実施例においても、上述した第１実施例と同様
に、Si基板10の主面全体がBPSG膜42によって覆われてい
るので、上述した従来技術よりも濡れ性がよい。このた
め、同図(E)に矢印FE,FFで示す両方向、すなわち山側の
みならず谷側にもフローするようになる。従って、良好
な丸み形状を有するエッジ部分44が形成されることとな
る。In the second embodiment as well, similar to the first embodiment described above, the entire main surface of the Si substrate 10 is covered with the BPSG film 42, so that the wettability is better than that of the conventional technique described above. Therefore, the flow will flow in both directions shown by arrows FE and FF in FIG. 6E, that is, not only on the mountain side but also on the valley side. Therefore, the edge portion 44 having a good rounded shape is formed.
以上のリフロー処理の後、同図(F)に矢印FGで示すよう
に、主体全面に対してRIEが行なわれ、コンタクトホー
ル部分のBPSG膜42,熱酸化膜40が各々除去されて、コン
タクトホール18が完全に形成される。After the above reflow treatment, as shown by an arrow FG in FIG. 7F, RIE is performed on the entire main body surface to remove the BPSG film 42 and the thermal oxide film 40 in the contact hole portion, respectively. 18 is completely formed.
このように、第２実施例によれば、次のような効果があ
る。As described above, according to the second embodiment, there are the following effects.
(1)従来よりも低温，短時間で良好なリフロー効果が得
られる。(1) A good reflow effect can be obtained at a lower temperature and in a shorter time than before.
(2)層間絶縁膜とSi基板10との境界面もなだらかにな
る。従って、Al等の配線材料の断線の発生が良好に低減
され、デバイスの信頼性が向上してサブミクロンコンタ
クトへの対応が可能となる。(2) The interface between the interlayer insulating film and the Si substrate 10 also becomes gentle. Therefore, the occurrence of disconnection of the wiring material such as Al is favorably reduced, the reliability of the device is improved, and the submicron contact can be dealt with.
なお、上記実施例は、MOSトランジスタにおけるコンタ
クトホール形成に対して本発明を適用すた場合である
が、これに限定されるものではない。また、リフロー処
理の対象となるものも、BPSG膜に限定されるわけではな
い。In addition, although the present invention is applied to the contact hole formation in the MOS transistor in the above-mentioned embodiment, the present invention is not limited to this. Further, the target of the reflow treatment is not limited to the BPSG film.
また、前記第２実施例では、エッジ部分を有するBPSG膜
16上に更にBPSG膜42を形成したが、BPSG膜と同一不純物
を一種類以上含むものであれば、ほかのものであっても
よい。In addition, in the second embodiment, the BPSG film having the edge portion is used.
Although the BPSG film 42 is further formed on the layer 16, another film may be used as long as it contains one or more kinds of the same impurities as the BPSG film.
更に、何れの実施例にいおても、絶縁膜に対するリフロ
ー処理を行なったが、そのほかの膜体であってもよい。Furthermore, although the reflow process is performed on the insulating film in any of the examples, other film bodies may be used.
［発明の効果］ 以上説明したように、本発明によれば、比較的低温，短
時間の熱処理で一層効果的なリフロー処理を行なって、
ステップカバレージの向上を図ることができ、これによ
って信頼性の高い半導体装置を製造できるという効果が
ある。[Effects of the Invention] As described above, according to the present invention, a more effective reflow treatment is performed by heat treatment at a relatively low temperature for a short time,
There is an effect that the step coverage can be improved, and thus a highly reliable semiconductor device can be manufactured.
第１図は本発明の第１実施例を示すプロセス説明図、第
２図は本発明の第２実施例を示すプロセス説明図、第３
図は従来技術を示す説明図、第４図は従来技術の問題点
を示す説明図である。 10……Si基板、12……ゲート酸化膜、14……ゲート電
極、16,42……BPSG膜、18……コンタクトホール、20,2
2,30,44……エッジ部分、24……膨らみ、40……熱酸化
膜。1 is a process explanatory view showing a first embodiment of the present invention, FIG. 2 is a process explanatory view showing a second embodiment of the present invention, and FIG.
FIG. 4 is an explanatory diagram showing a conventional technique, and FIG. 4 is an explanatory diagram showing problems of the conventional technique. 10 …… Si substrate, 12 …… Gate oxide film, 14 …… Gate electrode, 16,42 …… BPSG film, 18 …… Contact hole, 20,2
2,30,44 …… Edge part, 24 …… Swelling, 40 …… Thermal oxide film.
Claims (2)
る膜体に対し、そのエッジ部分に丸み形状を形成するリ
フロー処理が行なわれる半導体装置の製造方法におい
て、 前記エッジ部分の形成時に、除去すべき膜体の一部を残
す工程を含み、この工程の後に前記リフロー処理を行な
うことを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device, wherein a film body having an edge portion formed on a main surface of a substrate is subjected to a reflow process for forming a rounded shape at the edge portion, the method comprising: A method of manufacturing a semiconductor device, comprising a step of leaving a part of a film body to be removed, and performing the reflow treatment after this step.
る第１の膜体に対し、そのエッジ部分に丸み形状を形成
するリフロー処理が行なわれる半導体装置の製造方法に
おいて、 前記基板の表面のうち，前記エッジ部分の形成時に前記
第１の膜体が除去された部分に酸化膜を形成する工程
と、この工程後の基板主面上に、前記第１の膜体に含ま
れる不純物と同一不純物を一種類以上含む第２の膜体を
形成する工程とを各々含み、これらの工程の後に前記リ
フロー処理を行なうことを特徴とする半導体装置の製造
方法。2. A method of manufacturing a semiconductor device, wherein a first film body having an edge portion formed on a main surface of a substrate is subjected to a reflow process for forming a rounded shape at the edge portion, the surface of the substrate being formed. Among these, a step of forming an oxide film in a portion where the first film body is removed at the time of forming the edge portion, and an impurity contained in the first film body on the main surface of the substrate after this step. And a step of forming a second film body containing one or more kinds of the same impurities, and the reflow treatment is performed after these steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28986588A JPH0670990B2 (en) | 1988-11-16 | 1988-11-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28986588A JPH0670990B2 (en) | 1988-11-16 | 1988-11-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02135733A JPH02135733A (en) | 1990-05-24 |
| JPH0670990B2 true JPH0670990B2 (en) | 1994-09-07 |
Family
ID=17748761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28986588A Expired - Lifetime JPH0670990B2 (en) | 1988-11-16 | 1988-11-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0670990B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6544379B2 (en) | 1993-09-16 | 2003-04-08 | Hitachi, Ltd. | Method of holding substrate and substrate holding system |
-
1988
- 1988-11-16 JP JP28986588A patent/JPH0670990B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02135733A (en) | 1990-05-24 |
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