JPH0682818B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a plasma coupled device (Plasma Coupled Device).
Hereinafter referred to as PCD. ) Semiconductor photodetector according to
In particular, it is configured on a semiconductor substrate, and an imaging device, a position detection device,
Alternatively, it relates to an integrated solid-state imaging device used in an optical character reading device.

(Prior Art) Conventionally, there is known a solid-state imaging device configured by integrating a plurality of photoelectric conversion elements and a scanning circuit by PCD on a semiconductor substrate.

For example, FIG. 3 is a structural diagram showing an example of a substrate structure of a PCD according to the prior art. In FIG. 3, 101 is an N-type silicon semiconductor substrate, 102 is a base made of an N ^{+ -type} semiconductor layer, and 103.
Is an emitter made of a P-type semiconductor layer, 104 is a P-type semiconductor layer forming an intermediate P layer of the npnp transistor, 105 is an N ^{+ type} semiconductor layer forming a collector of the npnp transistor, and 106 is N ^+.
Common region forming an elongated base with shaped semiconductor layers, 10
7 is a DC power source for applying a DC voltage to the bases 102 and 106, and 108 to 110 are clocks φ ₁ to φ to the emitter 103, respectively.
It is a resistor for giving ₃ .

In FIG. 3, a common elongated base 106, an island-shaped emitter 103, and a collector 105 with a hook constitute a unit cell. FIG. 4 is an explanatory diagram showing an equivalent circuit of the unit element of the PCD shown in FIG. In FIG. 4, 111 is a P-type semiconductor layer 103, an N-type semiconductor substrate 101,
An nnp transistor composed of a P-type semiconductor layer 104, 112 is an N-type semiconductor substrate 101, a P-type semiconductor layer 104, and an N-type semiconductor substrate 104.
It is an npn transistor constituted by the ^{+ type} semiconductor layer 105.

The unit cell described above is a lateral type of single-junction transistor having a hook structure. In the state where a constant voltage source Vbc is connected between the base and collector, the cell between the emitter 103 and the collector 105 is shown in FIG. The negative resistance characteristic as shown appears. The voltage at the point where the negative resistance starts is called the peak point voltage Vp. In the ON state of the negative resistance, that is, in the low resistance state, plasma due to many electron-hole pairs exists between the emitter 103 and the collector 105. As in this case, the plasma is accumulated around the collector electrode and spreads around the collector electrode when the collector area is sufficiently small.

Now, a voltage larger than Vp is applied to the emitter 103 of the first element connected to the signal source of clock φ ₁ to turn it on, and the current of the second element connected to the signal source of clock φ ₂ is turned on. The peak point voltage Vp
Decreases as indicated by Vp 'in FIG. this is,
This is due to the conductivity modulation of the electron-hole pair plasma formed in the first element and is called the plasma coupling effect.

Therefore, if the second element is biased in advance so that it is larger than Vp ′ and smaller than Vp, what was originally in the off state is turned on by turning on the first element. Can be made. In this state, if the voltage of the first element is lowered and turned off, the on state is consequently shifted from the first state to the second state.

As shown in FIG. 3, three-phase shift pulse voltages φ _{1 to} φ ₃
Is added to each cell, the on state is sequentially transferred from the left element to the right element.

The above is the operation of the three-phase shift register which is the basis of PCD. FIG. 6 is a perspective view of a solid-state imaging device configured using such a PCD shift register.

In FIG. 6, the same elements as those in FIG. 3 have the same reference numerals. In FIG. 6, 113 is an N ^{+ type} semiconductor layer, and 115 is P.
-Type semiconductor layer, 116 is an N ^{+ -type} semiconductor layer, 117 is an N ^{+ -type} semiconductor layer,
118 is a P-type semiconductor layer. N ^{+ type} semiconductor layer 116, and P
The address switch 11 is configured by the semiconductor layers 115 and 118. The photodiode 12 is formed by the N-type semiconductor substrate 101 and the P-type semiconductor layer 118.
The output of 12 is output via the address switch 11.

The structure of the PCD shift register 10 shown in FIG. 6 is substantially the same as that shown in FIG. However, when used as a solid-state imaging device, the scan output is
The N ^{+ type} semiconductor layer 113 formed near the
It is extracted as a potential change near 105. When the unit device cell is in the OFF state, the DC bias voltage between the base 106 and the collector 105 is applied between the hook for providing the reverse bias and the collector 105, so that the N ^{+ type} semiconductor layer 113 is formed.
The potential of is almost equal to the potential of the base 106 (or the semiconductor substrate 101). When the unit element is turned on, the collector 10
Due to the conductivity modulation in the vicinity of 5, the potential of the N ^{+ type} semiconductor layer 113 is lowered and is reduced to the potential of the collector 105.

This change in potential can be transmitted to the photodetector as an address signal to turn on the address switch.

As described above, each pixel of the solid-state image pickup device corresponds to one photodiode, one switch, and one-stage scanning circuit, respectively. As is clear from the sectional structure of FIG. The PCD type solid-state image pickup device has a P on the N type semiconductor substrate 101.
-Type and N-type impurity regions are only formed,
It does not require complex manufacturing processes such as isolation and buried regions like other bipolar devices.

(Problems to be Solved by the Invention) According to the above-mentioned conventional technique, the shift register using the PCD basically operates according to the plasma coupling result. Therefore, there is an advantage that the degree of integration can be improved or the process can be facilitated because no isolation region or buried region is required. On the other hand, since there is no separation between the elements, PC
When any one stage of the shift register by D is turned on and the potential of the scan electrode at that stage is lowered,
As a result of electrical crosstalk due to the plasma coupling effect, the potentials of the scanning electrodes on both sides of the electrical crosstalk also decrease,
Eventually, several address switches are turned on at the same time, and the signal purity is reduced.

At this time, if the separation region is formed in the PCD shift register in order to prevent crosstalk, the plasma formation effect becomes insufficient and the transfer operation cannot be performed smoothly.

Further, according to the above-mentioned conventional technique, in the PCD shift register, the size and arrangement of the emitter, the collector, and the base are strongly determined by the pitch at which the unit element cells are arranged. Even if the above is directly connected to the address switch of the photodetector, there is a drawback that the driving ability for opening and closing the address switch is insufficient and the switching operation is not performed efficiently.

An object of the present invention is to eliminate the above-mentioned drawback by providing a switch means by a single transistor integrated and integrated between a shift register by a PCD and an address switch, and by adopting the switch means, it occurs between unit element cells. It is an object of the present invention to provide a solid-state imaging device configured to reduce unnecessary coupling and ensure switching operation.

(Means for Solving the Problems) A solid-state imaging device according to the present invention is formed by a second conductivity type on a semiconductor substrate having a first conductivity type, and receives light for accumulating signal charges generated by incident light. And a scanning circuit using a plasma coupling device for arranging photoelectric conversion elements each including one part and an address switch for reading out a signal charge in a one-dimensional or two-dimensional manner and selecting the address switches in time sequence. It is an improvement of the one configured in preparation.

That is, the solid-state imaging device according to the present invention is formed of the second conductivity type on the semiconductor substrate having the first conductivity type, and the photoelectric conversion element group for accumulating the signal charge generated by the incident light and the photoelectric conversion element. A light receiving unit including an address switch group for reading out each signal charge of the element group, a scanning circuit including a plasma coupling shift register for time-sequentially selecting the address switch, and a stage after each stage of the scanning circuit. A switch means including a vertical transistor group having a base connected to a single transistor switch group, a collector connected to the address switch so that an output of the switch can be connected to the address switch of the light receiving unit, and an emitter grounded. It consists of and.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a block diagram showing an embodiment of a main part of a solid-state image pickup device according to the present invention.

In FIG. 1, elements having the same functions as those in FIGS. 3 to 6 are given the same numbers. In FIG. 1, 1 is a P-type semiconductor layer, 2 is an N ^{+ -type} semiconductor layer, 3 is a P-type semiconductor layer, and 4 is N ^+.
The semiconductor layer, 7 is a terminal, 10 is a shift register, 11 is an address switch, and 13 is a switch means characterizing the present invention.

FIG. 2 shows the register 10 and the switch means shown in FIG.
FIG. 14 is an explanatory diagram showing an equivalent circuit of 13. In FIG. 2, the transistors 111 and 112 operate similarly to the transistors 111 and 112 shown in FIG. 4, respectively. npn transistor 9 is
The internal region of the semiconductor substrate 101 electrically connected to the N ^{+ type} semiconductor layer 5 in FIG.
It is formed by the ^{+ type} semiconductor layer 4.

In FIG. 1, an npn transistor 9 is arranged downstream of the shift register 10 in a vertical transistor structure.

The emitter 105 of the shift register 10 is connected to the base of the npn transistor 9. As a result, the shift register 10 by the PCD can control ON / OFF of the npn transistor 9, so that the potential change around the collector 106 is N ^+.
Shaped semiconductor layer 5 and the address switch 11
Added to.

In the embodiment shown in FIG. 1, the vertical npn transistor 9 provided at the subsequent stage of the shift register 10 can separate the element cells. In addition, the shift register 10
By arranging the npn transistor 9 and the npn transistor 9 as shown in FIG. 1, the npn transistor 9 is on / off controlled with a certain threshold value, so that the purity of the address signal can be remarkably increased.

In the structural arrangement shown in FIG. 1, since the address signal is reproduced, the driving capability of the address switch 11 is extremely high, and the on / off control can be performed very efficiently.

(Effects of the Invention) As described above, according to the present invention, by providing the switch means by the single transistor integrated and integrated between the shift register by the PCD and the address switch, the unit element cell is adopted by adopting the switch means. Since it is possible to reduce unnecessary coupling that occurs between them and ensure the switching operation, it is possible to significantly improve the resolution of the obtained optical signal and to significantly reduce the level of unnecessary noise components.

[Brief description of drawings]

FIG. 1 is a structural view partially showing an embodiment of a solid-state image pickup device according to the present invention. FIG. 2 is an explanatory diagram showing an equivalent circuit of the shift register and the switch means of the solid-state imaging device shown in FIG. FIG. 3 shows a semiconductor plasma coupling device (PC
It is a structural diagram showing an example of D). FIG. 4 is an explanatory diagram showing an equivalent circuit of the PCD shown in FIG. FIG. 5 is an explanatory diagram showing an example of current-voltage characteristics of the basic elements of the PCD shown in FIG. FIG. 6 is a perspective view showing an example of a solid-state image pickup device using a PCD constructed by the conventional technique. 1,3,103,104,115,118 …… P-type semiconductor layer 2,4,5,101,102,105,106,113,116,117 …… N-type semiconductor layer 7 …… Terminal 10 …… Shift register 11 …… Address switch 12 …… Photodiode 13 …… Switch means 107 …… Power supply 108-110 ...... Resistor 111,112 …… Transistor

Claims (1)

[Claims] 1. A second substrate on a semiconductor substrate having a first conductivity type.
A photoelectric conversion element group for accumulating signal charges generated by incident light and an address switch group for reading each signal charge of the photoelectric conversion element group, and the address switch. A scanning circuit including a plasma-coupled shift register for time-sequential selection, and a single transistor switch group whose base is connected to a rear stage of each stage of the scanning circuit, the output of the switch being the address switch of the light receiving unit. A solid-state image pickup device comprising: a switch means comprising a vertical transistor group having a collector connected to the address switch and an emitter grounded so as to be connected to the address switch.