JPH0683372B2 - Facsimile waveform shaping circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile waveform shaping circuit for shaping a facsimile image signal obtained by line-sequential scanning to obtain a more desirable image signal.

[Conventional technology]

In a facsimile machine that obtains an image signal by scanning an original, when the original is scanned, the obtained image signal is the original because of the scanning aperture, the influence of the movement of the original, the blurring of the optical system, the frequency characteristics of the analog image signal amplifier, etc. The waveform does not correspond to the reflectance of the surface as it is, but becomes distorted. Conventionally, a method of seeding has been devised and used in order to equalize and shape the image signal having this distorted waveform so as to approximate the waveform corresponding to the original document surface reflectance.

Among these conventional waveform shaping circuits, the latest one forms a two-dimensional equalizing filter by using a digital filter technique as shown in FIG. 7, for example.

The waveform shaping circuit of FIG. 7 converts the analog image signal 100 obtained by scanning into a multi-bit digital image signal 101 of several bits (signal value is x) by the A / D converter 1 and pixel delay Delayed by elements 2 and 3, as shown by the symbols 4,5,6,7, ax + (1-2a) Z ^-1 x + az ^-2 x (1) is applied to the second digital image signal. Get 102. Here, Z ⁻¹ is an operator indicating a delay of one pixel.

Further, the digital image signal 102 (signal value is y) is delayed by delay elements 8 and 9 for one scanning line,
As indicated by the symbol, by + (1-2b) L ^- 1y + bL ^- 2y (2) is performed to finally obtain the waveform-shaped digital image signal 103. Here, L ⁻¹ is an operator indicating a delay of one scanning line.

The above-mentioned conventional waveform shaping circuit has the characteristics of the edge enhancement filter when the coefficients a and b in the equations (1) and (2) are negative numbers, and reduces the distortion generated in the scanning system. It is well known that an image signal closer to the signal corresponding to the reflectance of the original can be obtained.

[Problems to be solved by the invention]

However, in the scanning system, due to the deviation of the reflection direction of the light generated by the unevenness of the original surface, the noise mixed in the electric system such as the analog image signal amplifier, etc., the obtained image signal includes information other than the document information. The noise signal is weak but included. Generally, these noise components contain a lot of high frequency components, and the two-dimensional filter of the previous example (coefficient a,
Since it is a high-frequency emphasis filter when b is negative, it equalizes the blunting of the signal in the scanning system and at the same time emphasizes and amplifies these noise components. For this reason, there are drawbacks such that extra recording other than the text information is generated in the received image obtained by recording and decompressing, the received image quality is deteriorated, and the compression effect is disturbed in the data compression processing such as redundancy compression encoding. was there.

An object of the present invention is to eliminate the above-mentioned drawback by adaptively selecting the values of the coefficients a and b in the above equations (1) and (2), and to amplify noise components other than the text information. It is another object of the present invention to provide a waveform shaping circuit that can equalize and correct the dullness of the image signal due to the scanning system and obtain a good image signal.

[Means for solving problems]

According to the present invention, in the facsimile waveform shaping circuit, a first scanning line delay circuit for outputting a fifth multilevel digital image signal obtained by delaying the fourth multilevel digital image signal by one scanning line, 1 for the fifth multi-valued digital image signal
A second scanning line delay circuit for outputting a sixth multi-valued digital image signal delayed by scanning lines, and the fourth multi-valued digital image signal for receiving the fourth, fifth and sixth multi-valued digital image signals Image signal value b _{0 of} the digital image signal, image signal value b _{1 of} the fifth multi-valued digital image signal, image signal value b of the sixth multi-valued digital image signal
To _2, provided that the seventh multilevel digital image signal represented by the following formula _{(1-2k) b 1 + k (} b 0 + b 2), 1) b 0, b 1, maximum and minimum b ₂ When the difference between the values is smaller than a predetermined number m, k is a predetermined positive number k ₃
2) When the difference between the maximum value and the minimum value of b ₀ , b ₁ , b ₂ is greater than or equal to a predetermined number m, k takes a predetermined negative number k ₄ .

And a second logic circuit for outputting By using the seventh multi-level digital image signal as the output image signal, it is possible to more effectively achieve the above object.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. First
Referring to the figure, reference numeral 20 is a document to be scanned.
Is transported for sub-scanning in the direction S indicated by the arrow in the figure by a sub-scanning paper feed mechanism (not shown). 21 is manuscript 20
Is a light source lamp for irradiating. The light source lamp 21 illuminates the original document 20, and the light reflected according to the reflectance of the document information drawn on the surface of the original document enters the photoelectric conversion element 22 and has an analog electric power having a signal level corresponding to the light amount. Converted to a signal. Reference numeral 23 is a scanning electric circuit section. Scanning electric circuit section 23
Includes an analog amplifier that amplifies an analog image signal from the photoelectric conversion element 22, and the photoelectric conversion element 22 may be, for example, CC.
When the D image sensor is used, it includes a circuit for driving the CCD image sensor by an appropriate method and sequentially reading the image signal on the scanning line pixel by pixel to enable main scanning. The configurations of these scanning systems are well known and will not be described in detail.

Thus, the analog image signal 201 line-sequentially scanned by the well-known method is input to the A / D converter 24, A / D converted and output as a 4-bit digital image signal 202 in this example.
The digital image signal 202 is input to the first logic circuit 27 and also to the 1-pixel delay circuit 25. The digital image signal 202 is delayed by one pixel by the one-pixel delay circuit 25 and output as a digital image signal 203. This digital image signal 203 is also input to the first logic circuit 27, is further input to the 1-pixel delay circuit 26, and is output as the digital image signal 204 from the 1-pixel delay circuit 26. The digital image signal 204 is input to the first logic circuit 27. The first logic circuit 27 uses digital image signals 202, 203, 20
4 is input, and a 4-bit digital signal 205 having the value of the following expression (3) is output with respect to the signal values a ₀ , a ₁ and a _{2 of} 202, 203 and 204.

(1−2k) a ₁ + k (a ₀ + a ₂ ) (3) However, when the difference between the maximum value and the minimum value of i) a ₀ , a ₁ , a ₂ is smaller than 3, k = 0.3, ii) When the difference between the maximum value and the minimum value of a ₀ , a ₁ , and a ₂ is greater than or equal to 3, k = −0.2.

The digital signal 205 is input to the second logic circuit 30 and the scanning line delay circuit 28. The digital signal 205 is delayed by one scanning line by the scanning line delay circuit 28 and output as a digital image signal 206. The digital image signal 206 is input to the second logic circuit 30 and the scanning line delay circuit 29. Digital image signal 20
6 is further delayed by one scanning line and output as a digital image signal 207. The digital image signal 207 is input to the second logic circuit 30. The second logic circuit 30 receives the three digital image signals 205, 206, 207 as inputs and outputs 205, 206, 20
A 4-bit digital signal 208 having a value of the following expression (4) is output for the signal values b ₀ , b ₁ , b _{2 of} 7.

(1−2k) b ₁ + k (b ₀ + b ₂ ) (4) However, when the difference between the maximum value and the minimum value of i) b ₀ , b ₁ , b ₂ is less than 3, k = 0.3, ii) When the difference between the maximum value and the minimum value of b ₀ , b ₁ and b ₂ is greater than or equal to 3, k = −0.5.

The digital image signal 208 is supplied to the next-stage circuit as the final output of this waveform shaping circuit.

Next, referring to FIG. 2, FIG. 2 is a circuit diagram showing details of the pixel delay circuit 25. Four
The bit digital image signal 202 has four signal lines 2021 to 202
Entered in 4. These signals 2021 to 2024 are latched in the D flip-flop 25 in synchronization with the clock pulse signal 301 output from the scanning electric circuit unit at each scanning timing for one pixel, and the signal lines 2031 to 2034 until the next pixel timing.
Held in. At the same time, since the signal corresponding to the new pixel is output to 202 from the scanning unit, the digital signal 203 is delayed by one pixel with respect to 202. Second
Although the figure shows the pixel delay circuit 25, the pixel delay circuit 26 is also realized by exactly the same circuit only by changing the digital signal 202 to 203 and 203 to 204.

Next, FIG. 3 is a circuit configuration diagram showing details of the one-scan line delay circuit 28. The digital image signal 205 composed of four signal lines is input to the tri-state buffer 41 and written in the RAM 42 in the low level section of the clock pulse signal 301 for each pixel. The address counter 43, which gives the address 402 to the RAM 42, is cleared for each scanning line by the scanning line synchronization signal 401 output from the scanning electric section at each start of one scanning line, so that the image written in the RAM 42 is written. The signal is latched in the D flip-flop 44 just before a new signal is written from the RAM 42 at the transition point of the pixel clock 301 from the high level to the low level after one scanning line. Therefore, the digital signal 206 is output with a delay of just one scanning with respect to 205, and a delay of one scanning line is realized. Third
Although the figure shows the delay circuit 28, the scanning line delay circuit 29 is also 20
It is clear that just changing 5 to 206 and 206 to 207 will do exactly the same.

FIG. 4 is a circuit diagram showing details of the first logic circuit 27.
In this embodiment, since the digital image signal has a 4-bit structure, the ROM 27 having a 4k × 4 bit structure having 12 address inputs is used.
The desired arithmetic logic is realized by using the contents written in ROM. FIG. 5 illustrates part of the contents of the ROM 27 in this embodiment. Obviously, the desired calculation result can be obtained by such a ROM. It is also apparent that the second logic circuit 30 can be similarly realized only by changing the ROM writing content according to the arithmetic expression.

Next, an example in which the waveform shaping circuit of this embodiment is applied to an image signal will be described with reference to FIG. In the embodiment, the circuit by pixel delay (25, 26, 27 in FIG. 1) performs the processing in the main scanning direction and the circuit by scanning line delay (28, 29, 30 in FIG. 1) performs the processing in the sub-scanning direction. However, only the processing in the main scanning direction will be described here. FIG. 6a) is an example showing the density distribution of the document image information written on the document. An analog image signal obtained when the document of FIG. 6 a) is scanned is shown in b). In FIG. 6 b), the portion A is a noise component generated by the unevenness of the document surface, and its amplitude is small. As a result of scanning a thin line on the document at the portion B, the signal becomes dull due to the characteristics of the scanning system, the peak level is lowered, and the signal level is smaller than the signal level corresponding to the original document reflectance (density). FIG. 6 (c) shows a digital signal obtained by A / D conversion and sampling of b). When the waveform shaping circuit consisting of blocks 25, 26, and 27 of FIG. 1 is applied to the digital image signal of FIG. 6c), the difference between the maximum value and the minimum value of adjacent three pixels is 3 in the section A. Is smaller, the coefficient k is
Since it is 0.3 (a positive number), the image signal is smoothed and has a waveform as shown in FIG. On the other hand, in the B part, the difference between the maximum value and the minimum value of the three adjacent pixels is 3 or more, so the coefficient k becomes -0.2 (negative number) and has the edge enhancement characteristic, as shown in FIG. 6d). As described above, the peak value of the stroke information in the portion B approaches the original level. 28,29,30 in Fig. 1
The portion consisting of the respective blocks performs the same processing by using three pixels adjacent in the sub-scanning direction instead of the three pixels adjacent in the main-scanning direction just described by the delay of one scanning line. It is obvious that the improvement effect of the signal can be obtained.

〔The invention's effect〕

As described above, the present invention performs the waveform shaping by performing the calculation of (1−2k) a ₁ + k (a ₀ + a ₂ ) on the values a ₀ , a ₁ , and a _{2 of} the three pixels adjacent to each other. In a waveform shaping circuit that obtains a signal, when the level difference between a ₀ , a ₁ , and a ₂ is small, k is adaptively switched to a positive value, and when the level difference is large, k is switched to a negative value. A noise signal with a small amplitude is not emphasized, but a high-frequency emphasis characteristic is given to the stroke information having an amplitude above a certain level, so that the stroke information can be reproduced more faithfully and good image quality can be obtained. Has the effect of

[Brief description of drawings]

FIG. 1 is a block diagram showing a waveform shaping circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the 1-pixel delay circuit 25 shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a circuit diagram showing details of the one-scan line delay circuit 28 shown in FIG. 4, FIG. 4 is a circuit diagram showing the first logic circuit 27 shown in FIG. 1, and FIG. FIG. 6 is a diagram showing a part of FIG. 6, FIG. 6 is a diagram showing signal waveforms of respective portions of FIG. 1, and FIG. 7 is a block diagram showing a conventional waveform shaping circuit. 24 ... A / D converter, 25 and 26 ... 1 pixel delay circuit, 27 ... 1st logic circuit, 28 and 29 ... Scan line delay circuit, 30 ... 2nd logic circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-90461 (JP, A) JP-A-58-175364 (JP, A) JP-A-58-88969 (JP, A) JP-A-60- 236580 (JP, A) Shunji Mori “Electronics Bunko 25 Image Processing Basics (Electronic Magazine Electronics December 1983 copy appendix)” page 17 December 1, 1983 Published by Ohmsha

Claims (1)

[Claims] 1. An A / D converter for quantizing a line-sequentially scanned analog image signal to convert it into a first multilevel digital image signal, and delaying the first multilevel digital image signal by one pixel. A first pixel delay circuit for outputting a second multi-valued digital image signal, and a second pixel delay circuit for outputting a third multi-valued digital image signal obtained by delaying the second multi-valued digital image signal by one pixel. The pixel delay circuit receives the first, second and third multi-valued digital image signals, receives the image signal value a _{0 of} the first multi-valued digital image signal, and the image signal value of the second multi-valued digital image signal. Signal value
a ₁ and the image signal value a ₂ of the third multi-valued digital image signal, the fourth multi-valued digital image signal (1-2k) a ₁ + k (a ₀ + a ₂ ) expressed by the following equation. However, 1) when the difference between the maximum value and the minimum value of a ₀ , a ₁ , a ₂ is smaller than a predetermined number n, k takes a predetermined positive number k ₁ and 2) a ₀ When the difference between the maximum value and the minimum value of, a ₁ and a ₂ is greater than or equal to a predetermined number n, k is a predetermined negative number.
Take k ₂ . And a first scanning line delay circuit that outputs a fifth multilevel digital image signal obtained by delaying the fourth multilevel digital image signal by one scanning line, and the fifth logic circuit The second scanning line delay circuit for outputting a sixth multi-valued digital image signal obtained by delaying the multi-valued digital image signal of 1 by one scanning line, and the fourth, fifth and sixth multi-valued digital image signals receiving, the image signal value b ₀ of the multi-level digital image signal of the fourth, the image signal value b ₁ of the multi-level digital image signal of the fifth, the image signal value b ₂ of the multi-level digital image signal of the sixth contrast, however seventh multilevel digital image signal represented by the following formula _{(1-2k) b 1 + k (} b 0 + b 2), 1) b 0, b 1, b the maximum value and the minimum value of ₂ when the difference is smaller than the number m of predetermined, k takes a positive number k ₃ a _{predetermined, 2) b 0, b 1} , the difference between the maximum value and the minimum value of b ₂ is predetermined et al Number When m is greater than or equal to, k is a negative predetermined number were
Take k ₄ . Waveform shaping circuit having a second logic circuit for outputting