JPH0693609B2 - Data holding circuit - Google Patents

Description

The present invention relates to a static type data holding circuit for holding input data, and particularly to data suitable for use in a CMOS type semiconductor integrated circuit. Relating to the holding circuit.

(Prior Art) A flip-flop circuit forming a register or a counter has a basic function of holding data. 14th
FIG. 16 to FIG. 16 are diagrams each showing a configuration of a conventional data holding circuit.

The data holding circuit in FIG. 14 has two P channels each.
A clocked inverter 115 consisting of MOS transistors 111, 112 and N-channel MOS transistors 113, 114, and one P-channel MOS transistor 116 and N-channel, respectively.
An inverter 118 including a MOS transistor 117 and a clocked inverter 123 including two P-channel MOS transistors 119 and 120 and N-channel MOS transistors 121 and 122, respectively.

In this data holding circuit, the clock signal ▲ ▼ is "L"
When the clock signal CLK is "H" level at the level, the clocked inverter 115 operates and the input data IN is inverted by the clocked inverter 115 and input to the inverter 118. That is, at this time, input data IN is taken in, and inverter 118 inverts the input signal. At this time, the clocked inverter 123 does not operate. Next, when the clock signal ▲ ▼ is at "H" level and the clock signal CLK is at "L" level, the clocked inverter 123 operates and the output of the inverter 118 is inverted by this clocked inverter 123 and input to the inverter 118. Be returned to. At this time, the data is held by the inverter 118 and the clocked inverter 123. Hold data OUT
Is output from the inverter 118.

By the way, there is a problem that the number of transistors used in the conventional data holding circuit is large. In recent years, since the system scale of LSI tends to expand, if many circuits as shown in FIG. 13 are formed on one chip, the chip size increases and the manufacturing cost increases.

In order to reduce the number of transistors, the data holding circuit of FIG. 15 has an inverter 126, which is composed of one P-channel MOS transistor 124 and one N-channel MOS transistor 125, instead of the clocked inverter 123 of the circuit of FIG.
Is used. That is, in the case of this data holding circuit, the clocked inverter 115 operates,
When the input data IN is taken in, the two inverters 118 and 126 hold the data.

However, this circuit has the following problems. That is, when the levels of the data previously held by the two inverters 118 and 126 are opposite to the levels of the input data IN which is next fetched by the clocked inverter 115,
A through current flows between the power supply V _DD and the ground. For example, when data is held (OUT = “L” level) so that the output of the inverter 126 becomes “H” level, the clocked inverter 115 takes in the “H” level input data IN. Then, a current flows between the power supply V _DD and the ground via the P-channel MOS transistor 124 in the inverter 126 and the N-channel MOS transistors 113 and 114 in the clocked inverter 115. On the contrary, when data is held (OUT = “H” level) so that the output of the inverter 126 becomes “L” level, the clocked inverter 115 inputs the “L” level input data IN. Is taken in, a current flows between the power supply V _DD and the ground through the P-channel MOS transistors 111 and 112 in the clocked inverter 115 and the N-channel MOS transistor 125 in the inverter 126. Therefore, in order to transmit the data accurately to OUT, the inverter 118
P-channel MOS transistors 111, 112, 124 and N-channel MOS transistors 113, 11 so as to satisfy the circuit threshold voltage of
4,125 dimensions must be designed. On the other hand, the operating speed of this circuit is that P-channel MOS transistors 111, 112, 1
16 and the N-channel MOS transistors 113, 114, 117 have smaller on-resistance values, and the P-channel MOS transistors 124 and N
The larger the on-resistance value of the channel MOS transistor 125,
Get faster In addition, the magnitude of the current flowing between the power source V _DD and the ground as described above depends on both transistors 1 in the inverter 126.
Depends on 24,125 ON resistance. Therefore, the on-resistance values of both transistors 124 and 125 are
By sufficiently increasing the on-resistance values of 13,114, accurate data transmission becomes possible and the current flowing between the power supply V _DD and the ground can be suppressed small. That is, as a result, the on-resistance values of the transistors 124 and 125 are increased, and this can be realized by reducing the channel width W and increasing the channel length L of both transistors. However, reducing the channel width W has a limit in manufacturing an integrated circuit, and increasing the channel length L leads to an increase in chip area. Further, in general, it is impossible to construct a circuit as shown in FIG. 15 with an integrated circuit such as a gate array which is composed of all transistors of the same size.

The data holding circuit of FIG. 16 has a P-channel MOS transistor 127 instead of the clocked inverter 115 in order to reduce the number of transistors as compared with the circuit of FIG.
And a N-channel MOS transistor 128 are connected in parallel to each other to use a transfer gate 129. However, also in the case of this circuit, it is necessary to increase the on-resistance values of the transistors 124 and 125 as in the circuit of FIG.

On the other hand, FIGS. 17 and 18 show the above-mentioned FIG. 14 and FIG.
15 is a diagram showing a configuration of a conventional set / reset type delayed flip-flop circuit in which two data holding circuits as shown in FIG. 15 are used and output data can be uniquely set based on a reset signal or a set signal. is there.

The flip-flop circuit shown in FIG. 17 has a reset priority, and it has two P-channel MOS transistors 131 and 1 respectively.
32, a clocked inverter 135 composed of N-channel MOS transistors 133, 134 for inverting the input data IN in synchronization with clock signals ▲ ▼, CLK1, P-channel MOS transistors 136, 137, 138 and N-channel MOS transistors 139,
The output of the clocked inverter 135, which consists of 140 and 141,
A reset priority type logic circuit 142 to which a reset signal Reset and a set signal ▲ ▼ are supplied, and two P
Clock signal CLK1, ▲ composed of channel MOS transistors 143 and 144 and N channel MOS transistors 145 and 146
In synchronization with ▼, the output of the logic circuit 142 is inverted and the logic circuit 1
A clocked inverter 147 that feeds back to the input side of 42, two P-channel MOS transistors 148 and 149, and two N-channel MOS transistors 150 and 151, respectively.
, A clocked inverter 152 for inverting the output of the logic circuit 42 in synchronization with CLK2, P-channel MOS transistors 153, 154, 155 and N-channel MOS transistors 156, 15
7,158, a reset-priority type logic circuit 159 to which the output of the clocked inverter 152, the reset signal Reset and the set signal ▲ ▼ are supplied, and two P-channel MOS transistors 160 and 161, N-channel MOS transistors 162 and 163, respectively. CLK2, ▲ ▼
The output of the logic circuit 159 is inverted in synchronization with
Of the clocked inverter 164 that feeds back to the input side of.

The flip-flop circuit shown in FIG. 18 is a P-channel MOS instead of the reset priority type logic circuit 142 in the circuit shown in FIG.
A set priority type logic circuit 171 comprising transistors 165, 166, 167 and N channel MOS transistors 168, 169, 170 and supplied with the output of the clocked inverter 138, a reset signal Reset and a set signal ▲ ▼ is provided, and a reset priority type circuit in FIG. Of the clocked inverter 152 or 164, and a reset signal Re, in place of the logic circuit 159 of FIG. 1 of P-channel MOS transistors 172, 173, 174 and N-channel MOS transistors 175, 176, 177.
A set-priority type logic circuit 178 to which the set and the set signal ▲ ▼ are supplied is provided.

In the conventional circuit of FIG. 17, the output data OUT obtained at the node E is supplied as an input to the next stage circuit when the flip-flop circuit is built in the integrated circuit.
Therefore, the node E has an input capacitance of the next stage circuit and a stray capacitance due to the wiring. Then, this stray capacitance slows down the switching speed. For example, OUT
Consider the operation when the reset signal Reset changes to "H" when = "H", CLK2 = "L", and ▲ ▼ = "L".
When the reset signal Reset goes high, the logic circuit 159
Since the N-channel MOS transistor 158 therein is turned on, the signal at the node E tends to change from "H" level to "L" level. At this time, if the stray capacitance of the node E is large, its fall time is delayed. Further, since the clocked inverter 164 transmits the output of the node E to set the node D to the “H” level,
The longer the fall time of the output data OUT of the node E, the longer it takes to set the level of the node D. As a result, the level setting of the output data OUT will be delayed. Also, when the reset signal Reset changes from “H” level to “L” level,
The same applies when ▼ changes. To solve these problems, the channel width W of each transistor in the logic circuit 159 is
May be increased, or a buffer may be inserted into the node D or the node E. However, since these transistors are connected in series in the logic circuit 159,
With the method of increasing the channel width W of each transistor, the effect of improving the rising and falling of the output data OUT is halved, so the channel width W must be set larger. On the other hand, in the method of inserting the buffer in the node D or the node E, the number of elements increases accordingly. Therefore, these methods bring about an increase in manufacturing cost when integrated into an integrated circuit. The same applies to the set / reset type delayed flip-flop circuit of FIG.

(Problems to be Solved by the Invention) As described above, in the conventional data holding circuit, in order to prevent the through current from flowing between the power supply and the ground, many transistors are provided, and the value of the above through current is set. It is necessary to increase the on-resistance value of the transistor in order to reduce the power consumption, which increases the chip area when integrated into a circuit, and it is not possible to configure it on an integrated circuit such as a gate array. is there.

Further, in the conventional data holding circuit having the set / reset function, the number of elements and the element size are increased in order to perform the set or reset operation at high speed, and the manufacturing cost is increased when integrated into an integrated circuit. There is.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce a value of a through current flowing between a power supply and a ground and to increase a chip area when integrated into an integrated circuit. Another object of the present invention is to provide a data holding circuit which can prevent the above-mentioned problem and can be easily configured on an integrated circuit such as a gate array.

A further object of the present invention is to provide a data holding circuit having a set / reset function that does not increase the manufacturing cost when integrated into an integrated circuit.

[Configuration of the Invention] (Means for Solving the Problem) The data holding circuit of the first invention captures input data.
A CMOS type input data capturing circuit, a CMOS type first inverting circuit to which the data captured by the input data capturing circuit is input, and a CMOS for returning the output of the first inverting circuit to its input A second inverting circuit of a mold and a resistance element inserted between the output of the second inverting circuit and the input of the first inverting circuit, the input data capturing circuit comprising:
The P-channel first and second P-channels are connected in series between the first node and the second node, which are output nodes, and the gates are supplied with the input data and the first clock signal, respectively.
A MOS transistor, a P-channel third MOS transistor connected between the first node and the second node, and having a gate supplied with the first control signal; a second node; A P-channel fourth MOS transistor connected to the first power supply and having a gate supplied with the second control signal, and connected in series between the first node and the second power supply. Input data, a second clock signal having a complementary relationship to the first clock signal, and the fifth control signal of the N channel, to which the first control signal is supplied,
6th and 7th MOS transistors. The second node is connected between the first node and the second power source, and the gate is connected to the second node.
And an N-channel eighth MOS transistor to which the control signal is supplied.

The data holding circuit according to the second aspect of the invention takes in input data.
A CMOS type input data capturing circuit, a CMOS type first inverting circuit to which the data captured by the input data capturing circuit is input, and a CMOS for returning the output of the first inverting circuit to its input A second inverting circuit of a mold and a resistance element inserted between the output of the second inverting circuit and the input of the first inverting circuit, the input data capturing circuit comprising:
First and second P-channels connected in series between the first power supply and the first node which is an output node, and having the gate supplied with the first control signal, the first clock signal and the input data, respectively. And a third MOS transistor, a P-channel fourth MOS transistor connected between the first power supply and the first node and having a gate supplied with a second control signal, and the first MOS transistor. Fifth and sixth N-channels connected in series between the second node and the second node, and supplied to the gate with input data and a second clock signal having a complementary relationship with the first clock signal, respectively. MOS transistor, an N-channel seventh MOS transistor connected between the first node and the second node and having the gate supplied with the first control signal, and the second node Between the second power supply and It is continued, the gate second
And an N-channel eighth MOS transistor to which the control signal is supplied.

A data holding circuit of a third invention is connected in series between a first power supply and a first node, and has a gate having a first control signal,
P-channel first, second and third MOS transistors, to which the first clock signal and the input data are respectively supplied, are connected between the first power supply and the first node,
The fourth P-channel whose gate is supplied with the second control signal
N MOS transistors connected in series between the first node and the second node, and supplied to the gate with the data and the second clock signal having a complementary relationship with the first clock signal, respectively. Channel 5th and 6th MO
An S-transistor, an N-channel seventh MOS transistor connected between the first node and the second node and having the gate supplied with the first control signal, the second transistor
Connected to a second power supply and having a gate to which the second control signal is supplied, the logic circuit including an N-channel eighth MOS transistor, and the first node to which an input node is connected. A first CMOS inverting circuit having an output node connected to the data output node, and a second CMOS inverting circuit having an input node connected to the data output node and an output node connected to the first node Is provided.

A data holding circuit according to a fourth invention is a P-channel first MOS transistor connected between a first power supply and a first node and having a gate supplied with a first control signal.
Second and third MOS transistors of P-channel, which are connected in series between the first node and the second node, and whose gates are supplied with the first clock signal and the input data, respectively. The fourth MO of the P-channel connected to the node of the P-channel and having the gate supplied with the second control signal.
S-transistor, serially connected between the second node and the second power supply, and having a gate, the input data, a second clock signal having a complementary relationship with the first clock signal, and the second control N-channel fifth, sixth and seventh MOS transistors, to which signals are respectively supplied, are connected between the second node and the second power supply, and the gate is supplied with the first control signal. Input to the data output node, and a first CMOS inversion circuit having an N-channel eighth MOS transistor, an input node connected to the second node, and an output node connected to the data output node. A second CMOS inversion circuit in which a node is connected and an output node is connected to the second node.

(Operation) When the levels of the data captured by the input data capturing circuit and the output data of the second inverting circuit are opposite, the power source and the ground are connected via the input data capturing circuit and the second inverting circuit. The value of the through current flowing therebetween is reduced by inserting the resistance element. Therefore, the MOS transistors forming the input data fetch circuit and the first and second inversion circuits can all have the same size.

Also, in the data holding circuit with set / reset function,
The output node of the first CMOS inversion circuit is connected to the data output node, and the logic circuit to which the first and second control signals corresponding to the set / reset signal are supplied is provided in the preceding stage. Therefore, the output data can be set at a high speed at the time of setting and resetting without increasing the element sizes of the P-channel and N-channel MOS transistors forming the first CMOS inversion circuit.

(Examples) Hereinafter, the present invention will be described by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a data holding circuit according to a first embodiment of the present invention. The data holding circuit according to this embodiment has two P-channel MOS transistors 1 each.
Clocked inverter 15 consisting of 1, 12 and N-channel MOS transistors 13, 14 and one P-channel MOS each
An inverter 18 including a transistor 16 and an N-channel MOS transistor 17, a clocked inverter 21 including a P-channel MOS transistor 19 and an N-channel MOS transistor 20, respectively, and a resistor 22.

A clock signal ▲ ▼ is applied to the gate of the P-channel MOS transistor 11 of the clocked inverter 15 and the P-channel MOS transistor 12 and the N-channel MOS transistor
Input data IN is supplied to each gate of 13 and a clock signal CLK is supplied to the gate of the N-channel MOS transistor 14. The signal of the output node A of the clocked inverter 15 is supplied to the gates of the P-channel MOS transistor 16 and the N-channel MOS transistor 17 of the inverter 18. The signal of the output node B of the inverter 18 is supplied to the gates of the P-channel MOS transistor 19 and the N-channel MOS transistor 20 of the inverter 21. The signal at the output node B of the inverter 18 is output as the holding data OUT, and the signal at the output node C of the inverter 21 is fed back to the input of the inverter 18 via the resistor 22.

In the circuit of this embodiment, when the clock signal ▲ ▼ is at "L" level and the clock signal CLK is at "H" level, the clocked inverter 15 operates and the input data IN is inverted by the clocked inverter 15 and the inverter 18 Entered in.
At this time, the input data IN is taken in, and the inverter 18 inverts the input signal. Further, the output of the inverter 18 is inverted by the inverter 21, is positively fed back to the input of the inverter 18 via the resistor 22, and the held data OUT is output from the inverter 18.

That is, in this data holding circuit, like the conventional circuit of FIG. 14, when the clocked inverter 15 operates and the input data IN is taken in, two inverters 1 are provided.
Data is held by 8,21.

Then, for example, when the signal at the output node C of the inverter 21 is at the "H" level, the clocked inverter 15 operates, the input data IN is taken in, and the output node A of the clocked inverter 15 becomes "L". The potential V _A1 of the node A when the level data is output is
When the ON resistances of 9,13,14 are Rp19, Rn13, Rn14 and the resistance value of the resistor 22 is R22, it is given by the following equation.

Here, if the value R22 of the resistor 22 is set to be sufficiently larger than Rn13 + Rn14, the potential V _A1 can be made approximately 0 V which is the ground potential. For example, R22 = 1MΩ, Rn13 = R
If n14 = 1KΩ, Rp19 = 10KΩ, and V _DD = 5V, V _A1 becomes about 0.01V as shown by the following equation.

When the levels of the data previously held by the two inverters 18 and 21 are opposite to the levels of the input data IN which is next fetched by the clocked inverter 15, the power supply V _DD and the ground are connected next to each other. A through current I ₁ as given by the formula flows.

I ₁ = V _DD / (Rp19 + R22 + Rn13 + Rn14) 3 By substituting the above values into the above three equations, the through current I ₁ becomes an extremely small value of approximately 0.0049 mA. Further, this shoot-through current stops flowing at that time because the output node C of the inverter 21 becomes "L" level when the output node B of the inverter 18 becomes "H" level.

On the other hand, when the signal at the output node C of the inverter 21 is at the "L" level, the clocked inverter 15 operates and the input data IN is fetched and the clocked inverter 15 is fetched.
The potential V _A2 of the node A when the “H” level data is output to the output node A of the above is given by the following equation, where the ON resistances of the transistors 11, 12, 20 are Rp11, Rp21, Rn20.

V _A2 = (P22 + Rn20) · V _DD / Rp11 + Rp12 + R22 + Rn20 ... 4 Here, if the value R22 of the resistor 22 is set to be sufficiently larger than Rp11 + Rp12 as in the above, the potential V _A2 will be approximately the power supply potential V _DD. Can be For example, R22 = 1M
Ω, Rp11 = Rp12 = 1KΩ, Rn20 = 10KΩ, and V _DD = 5V, V _A2 becomes 4.99V as shown in the following equation.

At this time, a through current I ₂ given by the following equation flows between the power supply V _DD and the ground.

I ₂ = V _DD / (Rp11 + Rp12 + R22 + Rn20) ... 6 By substituting the above values into the above 6 equation, this through current I ₂ becomes
As in the case of I ₁ , it becomes an extremely small value of approximately 0.0049 mA, and if the output node B of the inverter 18 becomes the “L” level, this shoot-through current becomes the “H” level of the output node C of the inverter 21. At that point it will stop flowing.

By thus inserting the resistor 22 between the output of the inverter 21 and the input of the inverter 18, the number of transistors can be reduced by two compared with the conventional circuit shown in FIG. It is necessary to provide one extra resistor 22 in the circuit of this embodiment, but generally in an integrated circuit, when comparing the occupied area of the resistor and the MOS transistor, the resistor should be equal to or less than that of the MOS transistor. it can. Therefore, the chip size of the integrated circuit provided with a large number of data holding circuits can be made smaller than that of the conventional one.

Further, in the circuit of the above embodiment, since the through current flowing between the power supply and the ground is reduced by providing the resistor 22, all transistors may be designed to have the same size. Therefore, unlike the conventional circuit shown in FIG. 15 or FIG. 16, there is no need to change the size of a specific transistor in order to reduce the shoot-through current. Therefore, also by this, the chip size can be reduced, and the circuit of this embodiment can be formed on an integrated circuit such as a gate array formed of transistors of the same size.

FIG. 2 is a circuit diagram showing the configuration of the data holding circuit according to the second embodiment of the present invention. In the data holding circuit according to this embodiment, a P-channel MOS transistor 23 having a gate supplied with a clock signal CLK and a gate supplied with a clock signal CLK instead of the clocked inverter 15 in the embodiment circuit shown in FIG. N-channel MOS transistor
CMOS with 24 sources and drains connected in parallel
The transfer gate 25 of the mold is used.

As described above, in the data holding circuit using the transfer gate 25 as the input data IN receiving circuit, the data held in advance by the two inverters 18 and 21 and the input data to be subsequently taken in by the transfer gate 25 are input. When the level of IN is opposite, a through current as described above flows between the power supply V _DD and the ground between the circuit generating the input data IN and the inverter 21. However, even in this case, since the resistor 22 is provided, the transistors 19, 20
The value of the through current flowing between the power supply V _DD and the ground can be reduced without increasing the on-resistance of.

FIG. 3 is a circuit diagram showing the configuration of the data holding circuit according to the third embodiment of the present invention. The data holding circuit according to this embodiment is a CMOS type logic circuit for setting the held data OUT to "H" level based on the set signal Set instead of the clocked inverter 15 in the embodiment circuit shown in FIG. 30 is provided. This logic circuit 30
Has three P-channel MOS transistors 31, 32 whose source and drain are connected in series between the power supply V _DD and the output node A, and the set signal Set, clock signal ▲ ▼ and input data IN are supplied to each gate. , 33, the source and drain are connected in series between the output node A and the ground, and the input data IN and the clock signal CLK are supplied to each gate 2
N-channel MOS transistors 34 and 35 and output node A
It is composed of an N-channel MOS transistor 36 whose source and drain are connected between the gate and ground and whose gate is supplied with the set signal Set.

In the circuit of this embodiment, when the set signal Set is at the "H" level, the P channel MOS transistor 31 in the logic circuit 30 is turned off and the N channel MOS transistor 36 is turned on.
Is turned on, the output node A is set to the "L" level regardless of the input data IN. Therefore, the signal of the output node B of the inverter 18, that is, the held data OUT is set to "H" level.

On the other hand, when the set signal Set is at "L" level, the P-channel MOS transistor 31 turns on and the N-channel MOS transistor
Since the transistor 36 is turned off, this logic circuit 30 is
Like the clocked inverter 15 in the figure, the clock signal ▲
▼, The input data IN is inverted in synchronization with CLK.

Also in the case of this embodiment, the value R22 of the resistor 22 is sufficient compared with the sum (Rn34 + Rn35) of the on-resistance values of the N-channel MOS transistors 34 and 35 in the logic circuit 30 and the on-resistance Rn36 of the N-channel MOS transistor 35. If it is set to be large, the potential of the node A is set to approximately 0V of the ground potential when the “H” level input data IN is supplied and when the set signal Set is set to the “H” level. be able to. Further, the value R22 of the resistor 22 is set to the P channel M in the logic circuit 30.
If it is set to be sufficiently larger than the sum of the on-resistance values of the OS transistors 31, 32, 33 (Rp31 + Rp32 + Rp33), the potential of the node A when the "L" level input data IN is supplied. Can be almost at the power supply potential V _DD .

FIG. 4 is a circuit diagram showing the configuration of the data holding circuit according to the fourth embodiment of the present invention. The data holding circuit according to this embodiment is a CMOS type logic circuit for setting the held data OUT to "L" level based on a reset signal Reset instead of the clocked inverter 15 in the embodiment circuit shown in FIG. 40 is provided. In this logic circuit 40, the source and drain are connected in series between the power supply V _DD and the output node A, and the clock signal ▲ is supplied to each gate.
▼ and two P-channel MOSs supplied with input data IN
Between the transistors 41 and 42, the P-channel MOS transistor 43 whose source and drain are connected between the power supply V _DD and the output node A, and the reset signal ▲ ▼ is supplied to the gate, and between the output node A and the ground. The source and drain are connected to and the input data IN and clock signal C are input to each gate.
It is composed of three N-channel MOS transistors 4, 45 and 46 to which the LK and the reset signal () are supplied.

In the circuit of this embodiment, the reset signal ▲ ▼
Is at the "L" level, the P-channel MOS transistor 43 in the logic circuit 40 is turned on and the N-channel MOS transistor 46 is turned off, so that the output node A receives the input data.
Set to "H" level regardless of IN. Therefore, the signal of the output node B of the inverter 18, that is, the held data OU
T is set to "L" level.

On the other hand, when the reset signal ▲ ▼ is at "H" level, the P-channel MOS transistor 43 turns off,
Since the N-channel MOS transistor 46 is turned on, the logic circuit 40 inverts the input data IN in synchronization with the clock signals {circle around ()} and CLK, like the clocked inverter 15 in FIG.

Even in the case of this embodiment, the value R22 of the resistor 22 should be set to be sufficiently larger than the sum (Rn44 + Rn45 + Rn46) of the on-resistance values of the N-channel MOS transistors 44, 45 and 46 in the logic circuit 40. For example, “H” level input data IN
Is supplied, the potential of the node A is almost grounded to 0V.
Can be set to. Further, the value R22 of the resistor 22 is set to be sufficiently larger than the sum (Rp41 + Rp42) of the on-resistance values of the P-channel MOS transistors 41 and 42 in the logic circuit 40 and the on-resistance Rp43 of the P-channel MOS transistor 43. In this case, the potential of the node A can be made approximately the power supply potential V _DD when the “L” level input data IN is supplied and when the reset signal ▲ ▼ is set to the “L” level.

FIG. 5 is a circuit diagram showing the configuration of the data holding circuit according to the fifth embodiment of the present invention. The data holding circuit according to this embodiment is. Instead of the clocked inverter 15 in the embodiment circuit shown in FIG. 1, a set priority type CMOS logic circuit 50 having a set / reset function is provided. That is, in the logic circuit 50, the source and drain are connected between the power supply V _DD and the node D, and the P-channel MOS transistor 51 having the gate supplied with the set signal Set, the node D and the output node A. Source between
Drains are connected in series, and clock signal is supplied to each gate.
And the two P-channel MOS transistors 52 and 53 to which the input data IN is supplied, the source and drain are connected between the node D and the output node A, and the reset signal ▲ is supplied to the gate. P-channel MOS
The source / drain is connected in series between the transistor 54, the output node A and the ground, and the input data I is input to each gate.
Three N-channel MOS transistors 55, 56, 57 to which N, clock signal CLK and reset signal ▲ ▼ are supplied
And an N-channel MOS transistor 58 whose source and drain are connected between the output node A and ground and whose gate is supplied with the set signal Set.

In the circuit of this embodiment, when the set signal Set is at "H" level, the N-channel MOS transistor 58 in the logic circuit 50 is turned on, so that the output node A becomes "L" regardless of the input data IN. Set to level. Therefore, the signal at the output node B of the inverter 18, that is, the held data OUT is set to "H" level.

On the other hand, the P-channel MOS transistors 51 and 54 in the logic circuit 50 are turned on by setting the reset signal ▲ ▼ to the “L” level when the set signal Set is at the “L” level. At this time, the output node A is set to the "H" level regardless of the input data IN. Therefore, the signal of the output node B of the inverter 18, that is, the held data OUT is set to "L" level.

Also in the case of this embodiment, the value R22 of the resistor 22 should be set to be sufficiently larger than the sum (Rn55 + Rn56 + Rn57) of the on-resistance values of the N-channel MOS transistors 55, 56 and 57 in the logic circuit 50. For example, “H” level input data IN
Is supplied, the potential of the node A is almost grounded to 0V.
Can be set to. Furthermore, if the value R22 of the resistor 22 is set to be sufficiently larger than the sum (Rp51 + Rp54) of the on-resistance values of the P-channel MOS transistors 51 and 54 in the logic circuit 50, the set signal Set becomes "L". When the "L" level reset signal Reset is supplied at the time of the level, the potential of the node A can be made approximately the power supply potential V _DD . Further, the value R22 of the resistor 22 is set to N in the logic circuit 50.
If the setting is made to be sufficiently larger than the on-resistance Rn58 of the channel MOS transistor 58, the potential of the node A becomes approximately 0V of the ground potential when the "H" level set signal Set is supplied. You can

FIG. 6 is a circuit diagram showing a structure of a data holding circuit according to a sixth embodiment of the present invention. In the data holding circuit according to this embodiment, a reset priority type CMOS logic circuit 60 having a set / reset function is provided in place of the clocked inverter 15 in the embodiment circuit shown in FIG. . That is, in the logic circuit 60, the source and drain are connected in series between the power supply V _DD and the output node A, and the set signal Set and the clock signal ▲ ▼ are connected to each gate.
And the three P-channel MOS transistors 61, 62 and 63 to which the input data IN is supplied, the source and drain are connected between the power supply V _DD and the output node A, and the reset signal ▲ ▼ is supplied to the gate. A P-channel MOS transistor 64, and two N-channel MOS transistors 65 whose source and drain are connected in series between the output node A and the node E and whose gates are supplied with the input data IN and the clock signal CLK. A source / drain is connected between 66 and the node E and the ground, and a reset signal is supplied to the gate.
N-channel MOS transistor 67 supplied with ▼
And an N-channel MOS transistor 68 whose source and drain are connected between the output node A and the node E and whose gate is supplied with the set signal Set.

In the circuit of this embodiment, the reset signal ▲ ▼
Is set to the "L" level, the P-channel MOS transistor 64 in the logic circuit 60 is turned on, so that the output node A is set to the "H" level regardless of the input data IN. Therefore, the signal at the output node B of the inverter 18,
That is, the held data OUT is set to the “L” level.

On the other hand, the N-channel MOS transistors 67 and 68 in the logic circuit 60 are turned on by setting the set signal Set to the “H” level when the reset signal ▲ ▼ is at the “H” level. At this time, output node A is set to "L" level regardless of input data IN. Therefore, the signal at the output node B of the inverter 18, that is, the held data OUT is set to "H" level.

Also in the case of this embodiment, the value R22 of the resistor 22 should be set to be sufficiently larger than the sum (Rn65 + Rn66 + Rn67) of the on-resistance values of the N-channel MOS transistors 65, 66 and 67 in the logic circuit 60. For example, “H” level input data IN
Is supplied, the potential of the node A is almost grounded to 0V.
Can be set to. Furthermore, if the value R22 of the resistor 22 is set to be sufficiently larger than the sum (Rp61 + Rp62 + Rp63) of the on-resistance values of the P-channel MOS transistors 61, 62 and 63 in the logic circuit 60, the "L" level When the input data IN of is supplied, the potential of the node A can be made approximately the current potential V _DD .

FIG. 7 is a pattern plan view showing an example of an integrated circuit in which the data holding circuit according to the present invention is constructed. This integrated circuit is a so-called full-faced gate array in which a large number of MOS transistors of the same size are laid all over the surface, 81 is an internal element and wiring region, and 82 is a pad arranged in the periphery.

FIG. 8 is an enlarged pattern plan view showing internal elements and wiring regions 81 in the integrated circuit shown in FIG.
In the figure, 81p is an internal element and a wiring region in which a large number of P-channel MOS transistors 83 are formed.
The transistor 83 is composed of a pair of p-type diffusion regions 84 serving as a source / drain and a gate electrode 85 arranged in the center thereof and formed of, for example, a polycrystalline silicon layer.
On the other hand, 81n is an internal element and wiring region in which a large number of N-channel MOS transistors 86 are formed, and each N-channel MOS transistor
The transistor 86 is composed of a pair of n-type diffusion regions 87 serving as a source / drain and a gate electrode 88 arranged in the center thereof and composed of, for example, a polycrystalline silicon layer or the like. In addition, in FIG. 9, the A of one N-channel MOS transistor 86 is shown.
An example of a cross-sectional structure taken along the line -A 'is shown. In the figure, 89 is a gate insulating film and 90 is an interlayer insulating film.

In the case where the data holding circuit as described above is formed in the integrated circuit of such a full-faced gate type gate array,
The resistor 22 is used by selectively increasing the resistance of the gate electrode material of the N-channel or P-channel MOS transistor at a position not used as a MOS transistor. That is, normally, when used as a gate electrode of a MOS transistor, an impurity is implanted into the polycrystalline silicon layer which is the material of the gate electrode to reduce the resistance. However, when it is used as the resistor 22, impurities are not implanted, or the implantation amount (implantation amount) is limited to obtain a high resistance state.

FIG. 10 is a pattern plan view showing an example of an integrated circuit in which the data holding circuit according to the present invention is constructed. This integrated circuit is of a gate array that is not a full-faced type, and 91 is an internal element region, 92 is a wiring region, and 93 is a pad arranged in the periphery.

FIG. 11 is an enlarged pattern plan view showing the internal element region 91 and the wiring region 92 in the integrated circuit shown in FIG. A P channel MOS is provided in each internal element region 91.
The transistor 94 and the N-channel MOS transistor 95 are formed in a mixed manner.

When the data holding circuit as described above is configured by an integrated circuit in which the internal element region and the wiring region are formed separately, such as a gate array, a standard cell or a full custom, which is not a full-faced type, The resistor 22
Are formed in the wiring regions 92 arranged between the internal element regions.

Further, when the data holding circuit according to the present invention is constructed in an integrated circuit having a built-in MOS static random access memory, the resistor 22 is constructed by using the same material as the high resistance load element used in the memory cell. do it.

12 and 13 are circuit diagrams showing configurations according to seventh and eighth embodiments of the present invention in which the present invention is applied to a data holding circuit having a set / reset function for output data.

FIG. 12 shows the structure of a reset priority type data holding circuit having a set / reset function for output data.
This data holding circuit comprises P-transistors 61, 62, 63, 64 and N-transistors 65, 66, 67, 68, like the reset-priority CMOS type logic circuit 60 in the embodiment circuit of FIG. Set signal Set, reset signal ▲
▼, input data IN and clock signal ▲ ▼, CLK1
And a logic circuit 60-1 to which the output of the logic circuit 60-1 is supplied and which is composed of a P-transistor 16 and an N-transistor 17 like the inverter 18 in the embodiment circuit of FIG. -1, and a P-transistor 19 and an N-transistor 20 similar to the inverter 21 in the embodiment circuit of FIG. 6, which inverts the output of the inverter 18-1 to the input side of the logic circuit 60-1. A data storage unit 201 at the previous stage, which is composed of a feedback inverter 21-1, is provided. Further, the data holding circuit is supplied with a reset-priority CMOS type logic circuit 60-2, which is supplied with ▲ ▼, CLK2 different from the above as a clock signal, and an output of the logic circuit 60-2. An inverter 18-2,
The output of this inverter 18-2 is inverted and the logic circuit 60
-2 is provided with a rear-stage data holding unit 202 including an inverter 21-2 that feeds back to the input side.

The data holding circuit having such a configuration is a reset-type delayed flip-flop with a set / reset function in which the preceding data holding unit 201 is a master side flip-flop circuit and the subsequent data holding unit 202 is a slave side flip-flop circuit. Acts as a pre-stage data holder
The truth table for 201 is as shown in Table I below.

In the circuit of the above embodiment, the data holding unit 201 in the preceding stage and the data holding unit 202 in the succeeding stage differ only in the clock signal, and since the other configurations are the same, both circuits perform the same operation. Therefore, in the following,
Only the operation of the data holding unit 20
The operation of 2 is similar to this.

Now, the set signal Set is at the “L” level and the reset signal ▲
When ▼ is at "H" level (Reset = "L"), the P transistor 61 is turned on, the P transistor 64 is turned on, the N transistor 67 is turned on, and the N transistor 68 is turned off in the logic circuit 60-1. At this time, the clock signal ▲
When ▼ changes to "L" level and CLK1 changes to "H" level, the P-transistor 62 and N-transistor 66 turn on, and this logic circuit 60-1 operates as an inverter for the input data IN supplied. , The inverted data of the input data IN is output to the output node A. For example, an inverter
When the output of 18-1 is "L" level, the input data IN is "L"
When the level changes to "H" level, the P transistor 63 in the logic circuit 60-1 turns off and the N transistor 65 turns on, so that the output node B of this logic circuit 60-1 tries to go to "L" level. To do. At this time, the node B has been previously set to "H" level by the output of the inverter 21-1.
Therefore, at this time, the P transistor 19 in the inverter 21-1 and the three N transistors 65, 6 in the logic circuit 60-1
A current flows between the power supply voltage V _DD and the ground voltage via 6,67. Then, the potential V _B (L) of the node B at this time is
The ON resistances of the P-transistor 19 and the N-transistors 65, 66, 67 are given by the following equations, which are Rp19, Rn65, Rn66, Rn67.

In order for the inverter 18-1 to detect the potential V _B (L) of the node B as the “L” level, this inverter 18-1
The circuit threshold voltage V _TH 18 of −1 needs to satisfy V _B (L) <V _TH 18. Therefore, in order to satisfy the relationship of V _B <V _TH 18, the following conditions should be satisfied.

Rp19 >> Rn65 + Rn66 + Rn67 ... 8 In order to further reduce the value of the current flowing at this time, it is sufficient to make ON Rp19 of the P-transistor 19 sufficiently large, which does not contradict the condition of the above expression 8.
Then, the node C is set to "H" by the output of the inverter 18-1.
When the voltage is set to the level, the P-transistor 19 in the inverter 21-1 is turned off, so that the current flowing between the power supply voltage V _DD and the ground voltage via the P-transistor 19 and the three N-transistors 65, 66, 67. Does not flow.

On the other hand, when IN = “L” level and node C = “H” level, clock signal ▲ ▼ becomes “L” level and CLK1 becomes “H” level.
Consider the case where each level changes. In this case, since the P-transistors 61, 62, 63 and the N-transistor 20 are turned on, the power supply voltage V
_A current flows between _DD and the ground voltage. The potential V _B (H) of the node B at this time is the same as the P transistors 61, 6
Set the on resistance of each of 2,63 and N transistor 20 to Rp61, R
Given p62, Rp63, and Rn20, they are given by the following equation.

The potential of the node B at this time is the inverter 18-1.
In order to detect V _B (H) as "H" level, the circuit threshold voltage V _TH 18 of the inverter 18-1 needs to satisfy V _B (H)> V _TH 18. Therefore, in order to satisfy the relationship of V _B (H)> V _TH 18, the following equation should be satisfied.

Rn20 >> Rp61 + Rp62 + Rp63 ... 10 In order to further reduce the value of the current that flows at this time, the on-resistance Rn20 of the N-transistor 20 should be made sufficiently large, which does not contradict the condition of the above formula 10. . When the node C is brought to the "L" level by the output of the inverter 18-1, the N transistor 20 in the inverter 21-1 is turned off, so that the three P transistors 61, 62,
The current flowing between the power supply potential V _DD and the contact voltage through 63 and the N-transistor 20 stops flowing.

When Set = Reset = “L” level and CLK1 = “L” level, the logic circuit 60-1 does not operate. And two inverters
18-1 and 21-1 function to hold the signals of the nodes B and C.

When Set = "L" level and Reset = "H" level, since the P transistors 61 and 64 are on and the N transistors 67 and 68 are off, the node B is at "H" level regardless of the level of the clock signal CLK1. Is set to. However, at this time, when the level of the node C is set to the “H” level in advance and the N transistor 20 in the inverter 21-1 is turned on, the power is supplied via the P transistor 64 and the N transistor 20. A current flows between the potential V _DD and the ground voltage. At this time, the potential V _{B of the} node B is the same as that of the P transistor 64 and N
When the on resistance of each transistor 20 is Rp64 and Rn20, it is given by the following equation.

In order for the inverter 18-1 to detect the potential V _{B of the} node B as "H" level, the inverter 18-1
The circuit threshold voltage V _TH 18 of −1 needs to satisfy V _B > V _TH 18. Therefore, in order to satisfy the relationship of V _B > V _TH 18, the following conditions should be satisfied.

Rn20 >> Rp64 ... 12 Further, in order to reduce the value of the current flowing at this time, Rn20 may be sufficiently increased in the same manner as described above, and this does not contradict the condition of the above expression 12. And node C
Is brought to the "L" level by the output of the inverter 18-1, the N transistor 20 in the inverter 21-1 is turned off, so that the current flowing between the current voltage V _DD and the ground voltage _stops flowing.

When Set = "H" level and Reset = "L" level, the P-transistors 61 and 64 are off and the N-transistors 67 and 68 are on. Therefore, the node B is irrespective of the levels of the clock signal CLK1 and the input data IN. Set to “L” level. However, at this time, the level of the node C is previously set to the “L” level, and the P transistor 19 in the inverter 21-1 is
When is on, a current flows between the power supply voltage V _DD and the ground voltage through the P transistor 19 and the two N transistors 68 and 67. At this time, the potential V _{B of the} node B is given by the following equation, where the ON resistances of the N transistors 67, 68 and the P transistor 19 are Rn67, Rn68, Rp19.

In order for the inverter 18-1 to detect the potential V _{B of the} node B as the "L" level, the inverter 18-1
The circuit threshold voltage V _TH 18 of −1 needs to satisfy V _B <V _TH 18. Therefore, in order to satisfy the relationship of V _B <V _TH 18, the following conditions should be satisfied.

Rp19 >> Rn67 + Rn68 ... 14 Further, in order to reduce the value of the current flowing at this time, Rp19 should be made sufficiently large as described above, which does not contradict the condition of the above-mentioned formula 14. And node C
Is brought to the "H" level by the output of the inverter 18-1, the P transistor 19 in the inverter 21-1 is turned off, so that the current flowing between the power supply voltage V _DD and the ground voltage _stops flowing.

That is, in the circuit of this embodiment, the on-resistance Rp19 of the P-transistor 19 is sufficiently larger than the on-resistance Rn63 of the N-transistor 63, the on-resistance Rn67 of the N-transistor 67, and the on-resistance Rn68 of the N-transistor 68. Similarly, if the on-resistance Rn20 of the N-transistor 20 is a sufficiently large value as compared with the on-resistance Rp62 of the P-transistor 62, the on-resistance Rp63 of the P-transistor 63, and the on-resistance Rp64 of the P-transistor 64, it is a delayed flip-flop. It works stably.

By the way, a major feature of the circuit of this embodiment is that the circuit for driving the node E for obtaining the output data OUT is a simple inverter 18-2 composed of a P-transistor and an N-transistor. This node E
When a large load capacitance of an external circuit is connected to the circuit, increasing the channel width W of the P-transistor 16 and the N-transistor 17 to enable high speed operation is performed in series in the conventional circuit shown in FIG. This is easier than the case of increasing the channel width of a large number of transistors. For this reason, even when the chip area is reduced when integrated into a circuit as compared with the conventional case, high speed operation becomes possible.

In the conventional circuit shown in FIG. 17, for example, node D
Is determined based on the reset signal Reset, the potential of the node C passes through the clocked inverter 152 when the clock signal CLK2 is "H" level, and the node C when the clock signal CLK2 is "L" level. The potential of E is applied through the clocked inverter 164. Therefore, in order to perform the reset operation at high speed, it is necessary to increase the channel width W of each transistor forming the clocked inverter 164. However, in the case of this embodiment circuit, it is always determined by the same path.
That is, it is the logic circuit 60-that determines the potential of the node D.
2. It is the inverter 18-2 that determines the potential of the node E, and the inverter 21-2 has nothing to do with the potential setting at this time. Therefore, the transistors forming the inverter 21-2 can have a small channel width, and the chip area can be reduced when integrated into an integrated circuit. Further, since the chip area is reduced, the manufacturing cost does not increase when integrated into a circuit.

FIG. 13 shows the configuration of a set priority type data holding circuit having a set / reset function for output data. This data holding circuit comprises P-transistors 51, 52, 53, 54 and N-transistors 55, 56, 57, 58 as in the set-priority CMOS logic circuit 50 in the embodiment circuit of FIG. The logic circuit 50-1 to which the set signal Set, the reset signal ▲ ▼, the input data IN and the clock signal ▲ ▼, CLK1 are supplied, and the P-transistor 16 and N like the inverter 18 in the embodiment circuit of FIG. An inverter 18-3 which is composed of a transistor 17 and which is supplied with the output of the logic circuit 50-2, and a P transistor 19 and an N transistor 20 which are similar to the inverter 21 in the embodiment circuit of FIG. Inverter 21- for inverting the output of 18-3 and feeding back to the input side of the logic circuit 50-1
The data holding unit 211 of the preceding stage constituted by 3 and 3 is provided. Further, this data holding circuit is provided with a reset-priority CMOS type logic circuit 50-2, which is supplied with ▲ ▼, CLK2 different from the above as a clock signal, and this logic circuit.
Data of the latter stage composed of an inverter 18-4 to which the output of 50-2 is supplied and an inverter 21-4 which inverts the output of this inverter 18-4 and feeds back to the input side of the logic circuit 50-2. A holding part 212 is provided.

The data holding circuit having such a configuration is different only in that the logic circuits 50-1 and 50-2 at the front stage and the rear stage are of the set priority type, and are similar to those of the embodiment circuit of FIG. 12 described above. , A circuit for driving the node E for obtaining the output data OUT is a simple inverter 18-4 composed of a P-transistor and an N-transistor. For this reason, increasing the channel width W of the P-transistor 16 and the N-transistor 17 for high-speed operation is more effective than increasing the channel width of a large number of transistors connected in series in the conventional circuit shown in FIG. It will be easier. For this reason, even when the chip area is reduced when integrated into a circuit as compared with the conventional case, high speed operation becomes possible. Further, it is the logic circuit 50-2 that determines the potential of the node D and the inverter 18-4 that determines the potential of the node E, and the inverter 21-4 has nothing to do with the potential setting at this time. Therefore, the transistors forming the inverter 21-4 can have a small channel width, and the chip area can be reduced when integrated into an integrated circuit.

It is needless to say that the present invention is not limited to the above embodiments and various modifications can be made. For example, in the circuit of the embodiment shown in FIG. 5, when the source and drain of the P-channel MOS transistor 51 whose set signal Set is supplied to the gate are connected between the power supply V _DD and the node D in the logic circuit 50. However, instead of connecting the source of the P-channel MOS transistor 54 to the node D, another P-channel MOS transistor whose gate is supplied with the set signal Set is provided in addition to the transistor 51. The P-channel MOS transistor supplied with the set signal Set may be connected to the power supply V _DD via the source and drain.

Similarly, in the circuit of the embodiment of FIG. 6, in the logic circuit 60, between the ground and the node E, the source and drain of the N-channel MOS transistor 67 whose gate is supplied with the reset signal ▲ ▼ are connected. As described above, this is an N-channel MOS transistor whose gate is supplied with the reset signal ▲ ▼.
In addition to 7, the source of the N-channel MOS transistor 68 is connected to the node E, and grounded through the drain and source of the N-channel MOS transistor whose gate is supplied with the reset signal ▲ ▼. It may be configured as follows. Further, also in the embodiment circuits shown in FIGS. 12 and 13, two transistors to which the set signal or the reset signal is supplied may be provided similarly.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the value of the through current flowing between the power supply and the ground, and to prevent the chip area from increasing when integrated into a circuit. You can
Further, it is possible to provide a data holding circuit which can be easily configured on an integrated circuit such as a gate array.

Further, according to the present invention, it is possible to provide a data holding circuit having a set / reset function which does not cause an increase in manufacturing cost when integrated into a circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the data holding circuit of the present invention, FIGS. 2 to 6 are circuit diagrams showing a configuration according to another embodiment of the present invention, and FIG. FIG. 8 is a pattern plan view showing an example of an integrated circuit in which the data holding circuit according to the present invention is configured, FIG. 8 is an enlarged pattern plan view showing a part of the integrated circuit of FIG. 7, and FIG. One transistor sectional view, FIG. 10 is a pattern plan view showing an example of an integrated circuit in which a data holding circuit according to the present invention is constructed, and FIG. 11 is an enlarged view of a part of the integrated circuit shown in FIG. FIG. 12 is a plan view showing a pattern, FIG. 12 and FIG. 13 are circuit diagrams showing a configuration according to another embodiment of the present invention, respectively.
14 to 18 are conventional circuit diagrams. 15 ... Clocked inverter, 18,18-1,18-2,18-3,1
8-4, 21, 21-1, 21-2, 21-3, 21-4 ... Inverter, 22
...... Resistance, 25 ...... Transfer gate, 30,40,50,60,50
-1,50-2,60,60-1,60-2 ... Logic circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shoji Kawauchi, 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture, Toshiba Microcomputer Engineering Co., Ltd. (72) Kazuya Yamaguchi, 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Microcomputer Engineering Co., Ltd. (56) Reference JP-A-60-150314 (JP, A) JP-A-61-53814 (JP, A) JP-A-60-70817 (JP, A)

Claims (10)

[Claims] 1. A CMOS type input data capturing circuit for capturing input data, a CMOS type first inverting circuit to which data captured by the input data capturing circuit is input, and the first inverting circuit. A second CMOS inverting circuit that feeds back the output of the first inverting circuit to its input, and a resistance element inserted between the output of the second inverting circuit and the input of the first inverting circuit, The input data acquisition circuit is connected in series between a first node and a second node, which are output nodes, and has first and second P-channels whose input data and first clock signal are supplied to the gates, respectively. 2's
A MOS transistor, a P-channel third MOS transistor connected between the first node and the second node, and having a gate supplied with the first control signal; and the second node and the second node. The fourth MO of the P channel connected to the power supply of No. 1 and having the gate supplied with the second control signal.
And an S-transistor connected in series between the first node and the second power supply,
N-th channel fifth, sixth, and seventh channels to which input data, a second clock signal complementary to the first clock signal, and the first control signal are supplied to the gate, respectively.
Connected between the first MOS transistor and the first node and the second power source,
A data holding circuit comprising an N-channel eighth MOS transistor whose gate is supplied with the second control signal. 2. The data holding circuit according to claim 1, wherein a conductor layer forming a gate electrode of a MOS transistor is used as the resistance element. 3. The data holding circuit according to claim 1, wherein the resistance element is formed in a wiring region of a semiconductor integrated circuit having an element region and a wiring region. 4. The data holding circuit according to claim 1, wherein the resistance element is made of the same material as a load element used in a memory cell of a CMOS static random access memory device. 5. A CMOS type input data capturing circuit for capturing input data, a CMOS type first inverting circuit to which the data captured by the input data capturing circuit is input, and the first inverting circuit. A second CMOS inverting circuit that feeds back the output of the first inverting circuit to its input, and a resistance element inserted between the output of the second inverting circuit and the input of the first inverting circuit, The input data receiving circuit is connected in series between the first power supply and the first node which is an output node, and the gate is supplied with the first control signal, the first clock signal and the input data, respectively. Connected to the first, second and third MOS transistors of the channel, between the first power supply and the first node,
The fourth P-channel whose gate is supplied with the second control signal
Of the MOS transistor and the first node and the second node are connected in series, and the gate is supplied with the input data and the second clock signal having a complementary relationship with the first clock signal. An N-channel seventh MOS transistor connected between the N-channel fifth and sixth MOS transistors and the first node and the second node and having the gate supplied with the first control signal. An N-channel eighth transistor connected between the transistor and the second node and the second power supply, and having the gate supplied with the second control signal.
A data holding circuit comprising: 6. The data holding circuit according to claim 5, wherein a conductor layer forming a gate electrode of the MOS transistor used as the resistance element is used. 7. The data holding circuit according to claim 5, wherein the resistance element is formed in a wiring region of a semiconductor integrated circuit having an element region and a wiring region. 8. The data holding circuit according to claim 5, wherein the resistance element is made of the same material as a load element used in a memory cell of a CMOS static random access memory device. 9. A P-channel first and a first P-channel connected in series between a first power source and a first node and having a gate supplied with a first control signal, a first clock signal and input data, respectively. 2 and a third MOS transistor, a P-channel fourth MO connected between the first power supply and the first node and having a gate supplied with the second control signal.
An S-transistor, which is connected in series between the first node and the second node and is supplied to the gate with the input data and the second clock signal having a complementary relationship with the first clock signal, respectively. Channel fifth and sixth MOS transistors, an N-channel seventh MOS transistor connected between the first node and the second node and having the gate supplied with the first control signal, An eighth N-channel connected between the second node and a second power supply and having the gate supplied with the second control signal.
, A first CMOS inversion circuit having an input node connected to the first node and an output node connected to a data output node, and an input node connected to the data output node, A second CMOS inverting circuit having an output node connected to the first node, and a data holding circuit. 10. A P-channel first MOS transistor connected between a first power supply and a first node, and having a gate supplied with a first control signal, said first node and second node. P-channel second and third MOS transistors connected in series with the node and supplied with the first clock signal and the input data at the gates, respectively, and between the first node and the second node. A fourth P-channel connected to the gate of which the second control signal is supplied.
A MOS transistor, connected in series between the second node and the second power supply,
N-channel fifth, sixth and seventh MOS transistors whose gates are supplied with the input data, a second clock signal having a complementary relationship with the first clock signal and the second control signal, respectively. An eighth N-channel connected between the second node and a second power supply and having the gate supplied with the first control signal.
, A first CMOS inversion circuit having an input node connected to the second node and an output node connected to a data output node, and an input node connected to the data output node, And a second CMOS inversion circuit having an output node connected to the second node.