JPH0697442B2 - Micro computer - Google Patents

Description

The present invention relates to a microcomputer having an electrically erasable and writable read-only memory (referred to as EEPROM).

[Conventional technology]

FIG. 4 shows an example of a conventional microcomputer having a built-in EEPROM. The EEPROM contained in a conventional microcomputer (hereinafter referred to as a microcomputer) is composed of an EEPROM cell 1, a Y address selector 2-a, a write / read control circuit 2-b, X.
Address decoder 3, write / read data switching circuit 4, address latch 5, address input buffer 6, EEPROM data input / output buffer 7, EEPROM control buffer 8, EEPROM control circuit 9
It is composed of. 38 writes to and reads from EEPROM cells,
An erasing control signal input terminal, 36 is an EEPROM address input terminal, and 37 is an EEPROM data input / output terminal.

When any of the erase signal, the write signal or the read signal is valid input to the terminal 38, the EEPROM control circuit 9 controls the input circuit of the address latch 5 and the write / read data switching circuit 4, and the central processing unit 10 (Hereinafter referred to as CPU)
Invalidate the address signal and data from. Further, at this time, the signal from the address input terminal 36 is input to the X address decoder via the address input buffer 6 and the address latch, while the EEPROM connected to the input / output terminal 37.
The signal from the data input / output buffer 7 is input as a valid signal to the Y address selector 2-a and the write / read control circuit 2-b via the data switching circuit, and the EEPROM cell 1
The erasing, writing, or reading operation is controlled.

[Problems to be solved by the invention]

The above-mentioned conventional microcomputer with built-in EEPROM performs erase, write or read operation by the erase or write or read control signal and address signal input from the external terminal, regardless of the contents of the data stored in the EEPROM. be able to. Therefore, in the conventional microcomputer, the instruction that commands the execution of the CPU and the constants necessary for executing the instruction are EEPR
Since there is no means to confirm the existence of data even when it is stored in the OM, when the microcomputer user writes or erases in the EEPROM which already stores the necessary information, It has a drawback that the information written in the EEPROM is destroyed or erased.

[Means for solving problems]

A microcomputer of the present invention includes a writable read-only memory cell provided in a specific address space of an electrically erasable and writable read-only memory, and a control gate group connected to the read-only memory cell, A circuit for inhibiting erasing and programming of an electrically erasable and writable read-only memory whose control gate group is mapped in an address space other than the specific address space, and
And a control circuit having a circuit for releasing the control for prohibiting the erasing and writing.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the microcomputer according to the present invention. The characteristic of this microcomputer is that it has an EEPROM 21 mapped in a specific address space, a specific address selection decoder 20 and a control circuit 22 for controlling the EEPROM by the EEPROM 21. FIG. 2 shows a concrete logic circuit of the control circuit 22, and the operation of this embodiment will be described.
After the data is written to the EEPROM cell 1 by the same means as the conventional example described above, when the written data is protected, the first specific address signal is input from the external address input terminal 36 and the specific address selection decoder 20 is used. By inputting a write signal from the EEPROM control terminal 38 that selects one of the EEPROM cells 51 to 54 mapped in a specific address space, writing is performed to any of the EEPROM cells 51 to 54 by the same means as in the conventional case.

In the example shown in FIG. 2, the data written in any of the EEPROM cells 51 to 54 receives the output of the EEPROM cells 51 to 54 as an input, and the exclusive OR circuits 61, 62 and 63 constitute an even parity generation circuit. The control circuit 22 inputs the signal to the circuit 22 and generates the CST signal for inhibiting the operation of the X address decoder 3. Therefore, after that, even if a control signal for erasing, writing, or reading to / from the EEPROM cell 1 is input through the terminals 36, 37, 38, the X address decoder 3 for selecting the EEPROM cell 1 does not function. Cannot be erased, written, or read.

Further, when the protection function of the data of the EEPROM cell 1 is activated by the above-mentioned operation, when canceling the protection function, the second specific address signal is input from the address input terminal 36 and mapped in the specific address space. EEPROM cell 51
54 to 54 are selected, and the write signal from the terminal 38 is used to write data in cells other than the EEPROM cell that realizes the protection function. In the case of FIG. 2, since the outputs of the EEPROM cells 51 to 54 are connected to the control circuit 22 as an even parity circuit, the outputs of the two EEPROM cells are "1" and the other two EEPROMs by the above operation.
The output of the OM cell becomes "0", the CST signal for inhibiting the operation of the X address decoder becomes "0", and the inhibition function of the X address decoder is released. Therefore, from now on, terminals 36, 37,
38 makes it possible to control erasing, writing and reading to the EEPROM cell 1. These series of operations are mapped to a specific address space (EEPROM cell 51 in the embodiment of FIG. 2).
It is effective to repeat as many as 54 to 54) EEPROM cells.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The first embodiment is an EEPR mapped in a specific address space.
The OM protected or erased all erase, write, and read of the EEPROM cell 1, but FIG. 3 shows that the EEPROM cell 1 is mapped by the outputs of the EEPROM cells 51 to 54 and the EEPROM control terminal 38 in FIG. It is input to the logic output circuit 33 that obtains the logic output of the EEPROM external access mode signal to be accessed, and the individual cell outputs of the EEPROM cells 51 to 54 are EE.
It shows that the output of each NOR circuit of the address decoder circuit outputs X _{0 to} Xm for selecting the address line of the PROM cell 1 is prohibited.

Explaining FIG. 3 in more detail, the EEPROM cell 51 is the EEPROM
The address decoder circuit outputs X ₀ and X ₁ for selecting the address line of the OM cell 1 and the EEPROM cell 52 the address decoder circuit outputs X _{2 to} Xl for selecting the address line of the EEPROM cell 1 are EEPROM.
The OM cell 53 has the address decoder circuit outputs Xl _{+1 to} Xm _-4 for selecting the address line of the EEPROM cell 1, and the EEPROM cell 54 has the EEPR.
It is possible to prevent the address decoder circuit outputs Xm _{-3 to} Xm that select the address line of the OM cell 1 from becoming active, so that the data protection of the EEPROM cell 1 can be realized as in the first embodiment.

Note that the EEPROM cell 51 mapped to a specific address space
I explained the case where the data was written to ~ 54 by the control signal from terminals 36 to 38, but the CPU does not read / write the EEPROM by inputting the control signal from the external terminal, It is also possible to read or write the data input / output from the CPU by the read / write signal generated. CP instead of terminals 36-38
Obviously, U10 can provide similar control to EEPROM cells 51-54, and similar effects can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the EEPR is stored in the specific address space.
OM21 is provided, and the output of that cell is
By providing a circuit to control the EEPROM cell 1
There is an effect that the data written in the EEPROM cell 1 can be electrically protected.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of FIG. 1, FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. Is a block diagram of a conventional example. 1 ... EEPROM cell, 2-a ... Y address selector,
2-b ... Write / read control circuit, 3 ... X address decoder, 4 ... Write / read data switching circuit, 5 ... Address latch, 6 ... Address input buffer, 7 ... EE
PROM data input / output buffer, 8 ... EEPROM control buffer, 9 ... EEPROM control circuit, 10 ... CPU, 20 ... Specific address selection decoder, 21 ... EE in specific address space
PROM, 22 ... EEPROM control circuit in specific address space, 36 ... address input terminal, 37 ... EEPROM data input / output terminal, 38 ... EEPROM control terminal, 51 to 54 ... EEPROM in specific address space Cell, 61 to 63 ... Exclusive OR circuit, CST ... Signal to prohibit output of X address decoder.

Claims (1)

[Claims] 1. Addressing is possible directly from an external terminal,
An electrically erasable and writable first read-only memory accessible by a built-in central processing unit;
Address decoder connected to the read-only memory of
A selector circuit, an electrically writable second read-only memory having an address space different from that of the first read-only memory, and output data of the second read-only memory are inputted to the address decoder / selector. A control circuit having means for stopping the selection function of the circuit and means for canceling the stop of the selection function is provided, and the control circuit comprises the second circuit.
Has a logic for controlling either the means for stopping the selection function of the address decoder / selector circuit or the means for canceling the stop of the selection function according to the result of the parity operation of the data written in the read-only memory. , Prohibiting the erasing / writing of data in the first read-only memory by means for stopping the selection function of the address decoder / selector circuit, and releasing the stop of the selection function of the address decoder / selector circuit. A microcomputer capable of canceling prohibition of erasing / writing of data in the first read-only memory.