JPH0698380A - Digital data receiver - Google Patents

Abstract

PURPOSE:To transmit plural types of binary signals via a single transmission line and to separate these binary signals from each other at the receiver side. CONSTITUTION:A 1st transmitter part 1 fetches the binary signal through a signal terminal T connected to a transmission line and turns on and off a transistor TR Q2 with the binary signal. Therefore the TR Q2 outputs a binary signal obtained by inverting the logical value of the binary signal inputted from the terminal T through a collector. A 2nd receiver part 2 detects the rise of the binary signal S1 outputted from the collector of the TR Q2 through a capacitor C2 and outputs a binary signal S2 serving as a pulse signal of a short time at the rise of the signal S1. The binary signal using the pulse width as the information is taken out of the collector of the TR Q2, and the binary signal using the element except the pulse width as the information can be taken out through the capacitor C2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data receiving apparatus which is connected to a transmission line for transmitting digital data by a plurality of types of binary signals and which receives each type of binary signal separately. .

[0002]

2. Description of the Related Art Conventionally, a binary signal is transmitted in a time division multiplex manner between a central control unit and a plurality of terminals via a transmission line to transmit and receive digital data, and is also provided in the terminals. There is provided a data transmission system that determines a basic operation of a terminal according to the contents of a rewritable function setting memory. In this type of system, a normal mode for exchanging data between the central controller and the terminal,
A repair mode for handling the contents of the function setting memory is provided. If the repair mode is mistakenly entered into the repair mode during operation in the normal mode, the system cannot operate normally. Therefore, signals with different modulation formats and formats are used in the normal mode and the repair mode.

Since it is necessary for such a terminal device to receive two kinds of binary signals, generally, as shown in FIG. 10, two sets of signals are inputted to which each binary signal is input separately. A configuration including terminals T ₁ and T ₂ is considered. That is, in the circuit configuration of FIG. 10, the signal terminal T ₁ is connected to a transmission path for normal data transmission, and the signal terminal T ₂ is connected to a repair device as needed. In the transmission line,
The pulse width modulated bipolar (± 2
4V) binary signal is transmitted, and a unipolar (+ 24V) binary signal with pulse amplitude modulation as shown in FIG. 3A is input from the repair device.

As shown in FIG. 10, a binary signal input from a signal terminal T ₁ connected to a transmission line is passed through a full-wave rectifier RE consisting of a diode bridge to a transistor Q.
₁ , a Zener diode ZD, resistors R ₁ and R ₂ , and a smoothing capacitor C ₁ are input to a constant voltage circuit 10,
From the binary signal, a DC voltage of 5V can be obtained. With this constant voltage circuit 10, a power supply for operating the terminal can be obtained.

On the other hand, _one of the signal terminals T ₁ connected to the transmission line is connected to the base of a switching transistor Q ₂ via a base resistor R _3, and the emitter and collector of the transistor Q ₂ are connected to the resistor R _4. Are connected in series, and this series circuit is connected between the output terminals of the constant voltage circuit 10. Therefore, when the binary signal shown in FIG. 2 to the signal terminal T ₁ (a) is input, as shown in FIG. 2 (b), from the collector of the transistor Q _2, is input to the signal terminal T ₁ Two
When the value signal is + 24V, it becomes 0V, and when it is -24V, the binary signal S ₁ which becomes 5V is outputted. By inputting this binary signal S ₁ to the signal processing unit (not shown) of the terminal device including a microcomputer or the like, the terminal device can receive the data.

The base of a switching transistor Q ₃ is connected to one of the signal terminals T ₂ via a base resistor R ₅ , and a resistor R ₆ is connected in series to the emitter-collector of the transistor Q _3. The series circuit is connected between the output terminals of the constant voltage circuit 10. Therefore, FIG.
When a binary signal as shown in FIG. 3A is input, as shown in FIG. 3B, when the binary signal input to the signal terminal T ₂ is 24V, it is 0V from the collector of the transistor Q _3. ,
A binary signal S ₂ of 5V when 0V is output. The binary signal S ₂ is input to the signal processing unit and used for setting, correcting, confirming the contents of the function setting memory.

In the above-mentioned structure, since two signal terminals T ₁ and T ₂ are required, there is a problem that the number of parts is large and the cost reduction is hindered. Moreover, when the terminal device is downsized, there is a problem. There is a problem that the terminals T ₁ and T ₂ are bulky and hinder the miniaturization. In order to solve such a problem, the present inventor proposed in Japanese Patent Application No. 1-95535 a terminal device in which a repair mode is set for a certain time when the system is started, and a normal mode is set after the certain time has elapsed. .

[0008]

However, in the above configuration, the contents of the function setting memory can be handled for a fixed time when the system is started up. The contents of the function setting memory cannot be set, modified or confirmed. In other words, if you try to change or check the function of the terminal after the system is started,
There is a problem that the system is restarted and the usability is poor.

An object of the present invention is to solve the above-mentioned problems, and it is a digital data that can transmit two kinds of binary signals using one transmission path and receive both signals at a desired time. It is intended to provide a receiving device.

[0010]

In order to achieve the above object, the invention of claim 1 is connected to a transmission line through which a plurality of different types of binary signals are transmitted, and receives each type of binary signal. In the digital data receiving device that is separated by
The binary signal transmitted through the transmission path is of two types, a first binary signal for identifying a digital value by a pulse width and a second binary signal for identifying a digital value by another attribute of a pulse. A first receiving unit that outputs a binary signal corresponding to the first binary signal and a second receiving unit that outputs a pulse signal corresponding to the changing point of the second binary signal are provided, and the transmission line is provided. The input terminals of the first receiving section and the second receiving section are commonly connected to the signal terminal connected to.

According to the second aspect of the invention, the second receiving section receives the binary signal from the signal terminal via the capacitor. According to the invention of claim 3, in a digital data receiving apparatus which is connected to a transmission line for transmitting a plurality of different types of binary signals and receives and separates each type of binary signal, the transmission is performed through the transmission line. A selection unit that makes the amplitude voltages of the value signals different from each other, detects the amplitude voltage of each binary signal and outputs a selection signal according to the amplitude voltage, and selects a binary signal of each amplitude voltage in response to the selection signal. A plurality of gate portions that can pass through in one pass are provided, and the input terminals of the respective gate portions are commonly connected to the signal terminals connected to the transmission path.

In a fourth aspect of the present invention, a digital data receiving apparatus connected to a transmission line for transmitting a plurality of different types of binary signals and receiving and separating each type of binary signal is transmitted through the transmission line. A plurality of comparing units for separating the binary signal of each amplitude voltage by making the amplitude voltage of the binary signal different from each other and comparing the amplitude voltage of the binary signal with the reference voltage are connected to the transmission line. The input terminal of each comparison unit is commonly connected to the signal terminal.

According to a fifth aspect of the present invention, a digital data receiving apparatus which is connected to a transmission line for transmitting a plurality of different types of binary signals and receives and separates each type of binary signal is transmitted through the transmission line. There are two types of binary signals that are unipolar and have different polarities.
Two receiving sections for outputting a binary signal corresponding to the value signal are provided, and the input terminals of both receiving sections are commonly connected to the signal terminals connected to the transmission path.

[0014]

According to the structure of the first aspect, there are two kinds of binary signals, a first binary signal for identifying a digital value by a pulse width and a second binary signal for identifying a digital value by another attribute of a pulse. The binary signal is transmitted to the transmission line, the binary signal corresponding to the first binary signal is output from the first receiving unit, and the pulse signal corresponding to the change point of the second binary signal is transmitted to the second signal. Since it is output from the receiving unit and the input ends of the first receiving unit and the second receiving unit are commonly connected to the signal terminal, a binary signal with pulse width modulation, pulse amplitude modulation, pulse Phase modulation,
A binary signal of another modulation method such as pulse number modulation can be separated by the outputs of the first receiving unit and the second receiving unit. In this case, the binary signal corresponding to the second binary signal is also obtained as the output of the first receiving unit, and the pulse signal corresponding to the change point of the first binary signal is obtained by the second receiving unit. Although it can be obtained as an output, there is no problem because it can be discriminated by the presence or absence of carriers or the difference in format. Further, since the two types of signals are separated by the first receiving section and the second receiving section, and the input ends of both receiving sections are commonly connected to the signal terminal, two types of signals can be provided on one transmission line. Can be transmitted. In this way, as a result of separating two types of signals transmitted on one transmission line,
Both signals can be transmitted at any time, and even if the contents of the function setting memory of the terminal device are set, corrected, or confirmed as described in the related art, the system Work can be performed at any point during operation, improving usability.

The structure of claim 2 is a preferred embodiment of the structure of claim 1. According to the configuration of claim 3, a plurality of types of binary signals having different amplitude voltages are transmitted to the transmission line, and the plurality of gate sections are selected according to the selection signal output from the selection section for each amplitude voltage. Since it is opened, the binary signal of each amplitude voltage can be taken out only from the corresponding gate section. That is, since the input end of the gate section is commonly connected to the signal terminal, it is possible to separate the plural kinds of binary signals transmitted through one transmission line by the selecting section and the gate section.

According to the structure of claim 4, plural kinds of binary signals having different amplitude voltages are transmitted to the transmission line, and the amplitude voltages of the binary signals are respectively compared with the reference voltage by the plurality of comparators. Since the binary signal of the amplitude voltage is separated, the binary signal of each amplitude voltage can be taken out only from the corresponding comparing unit. Further, since the input ends of the respective comparison units are commonly connected to the signal terminals, it is possible to separate a plurality of types of binary signals transmitted through one transmission line by the comparison units.

According to the structure of claim 5, two kinds of binary signals each having a single pole are transmitted to the transmission path, and each binary signal is inputted as an opposite polarity. Since two receiving units that output a binary signal corresponding to the value signal are provided, it is possible to output a binary signal corresponding to a binary signal of each polarity for each receiving unit, resulting in two types. The signal can be separated as the output of each receiver. That is, the two types of binary signals transmitted on one transmission line can be separated by the receiving unit.

[0018]

(Embodiment 1) In this embodiment, a pulse width modulated bipolar first binary signal as shown in FIG.
An example in which the pulse-amplitude-modulated unipolar second binary signal as in (a) is transmitted to the transmission line is shown. Here, about 35 kHz is selected as the carrier of the second binary signal. As shown in FIG. 1, the first binary signal extracting first
The configuration of the receiving unit 1 is the same as the conventional configuration shown in FIG. That is, through the base resistor R ₃ is the base of the transistor Q ₂ is connected to one signal terminal T which is connected to the transmission line, the emitter of the transistor Q ₂ - the collector resistor R ₄ is connected in series, the series circuit Is a constant voltage circuit 10
It is connected between the output terminals of. The constant voltage circuit 10 is
It has the same configuration as the conventional technique.

By the way, the emitter of the transistor Q ₂
A series circuit of a capacitor C ₂ and a resistor R ₀ is connected in parallel to the collector, and a full-wave rectifier RE is connected to the resistor R _0.
A diode D ₁ having an anode connected to the negative electrode of is connected in parallel. The capacitor C ₂ , the resistor R ₀ , and the diode D _{1 form} the second receiving unit 2. First
The output of the receiving section 1 of the above, that is, the output of the collector of the transistor Q ₂ becomes a binary signal S ₁ obtained by inverting the logical value of both binary signals of FIG. 2A and FIG. 3A. That is, when a ± 24V bipolar signal as shown in FIG. 2A is input to the signal terminal T, the transistor Q ₂ is turned on when the signal terminal T is + 24V, and as shown in FIG. 2B. Further, the collector potential of the transistor Q ₂ becomes 0V, and when the signal terminal T is -24V, the transistor Q ₂ is turned off and the collector potential becomes 5V. In this way, the binary signal S ₁ is output from the collector of the transistor Q ₂ . Similarly, in the case of a 24 V unipolar binary signal as shown in FIG. 3A, when the signal terminal T is 24 V, the transistor Q ₂
Is turned on, the potential of the collector of the transistor Q ₂ becomes 0V, and when the signal terminal T is 0V, the potential of the collector of the transistor Q ₂ becomes 5V.

On the other hand, the second receiving section 2 outputs pulse signals as shown in FIGS. 2 (c) and 3 (c) for each binary signal. That is, for the binary signal of FIG. 2A, when the signal terminal T is + 24V, the transistor Q ₂ is turned on and the capacitor C ₂ is turned on.
Discharges through ₂ and a diode D _1, the cathode potential at this time diode D ₁ becomes almost to 0V because not higher than the net direction voltage of the diode D _1. Also,
Because if the signal terminal T from + 24V to -24V transistor Q ₂ is turned off, the capacitor C ₂ is the resistor R _4,
A voltage corresponding to the voltage across the resistor R ₀ is generated at the cathode of the diode D ₁ while being charged through R ₀ and the charging current is flowing. However, the period during which the charging current flows is determined by the output voltage of the constant voltage circuit 10, the resistors R ₄ and R ₀ , and the capacitor C ₂ , and is generally set to a very short time. That is, a change point at which the binary signal to the signal terminal T falls is detected, and a pulse signal for a short time is output corresponding to the change point.

On the other hand, for the binary signal shown in FIG. 3A, when the signal terminal T is at 24V, the capacitor C ₂ is discharged and the cathode potential of the diode D ₁ is almost 0.
It becomes V. Further, when the signal terminal T changes from 24V to 0V, a short-time charging current flows in the capacitor C _2, and
As shown in (c), a short-time pulse signal is generated at the cathode of the diode D ₁ during this period. That is, a change point at which the binary signal to the signal terminal T falls is detected, and a pulse signal for a short time is output corresponding to the change point. That is, the binary signal S ₂ is output from the cathode of the diode D ₁ .

As described above, two kinds of binary signals S ₁ ,
Although S ₂ is separated as the output of the first receiving unit 1 and the output of the second receiving unit 2, respectively, it is input to the signal terminal T.
The pulse signal corresponding to the change point of the first binary signal as shown in (a) is also output from the second receiving unit 2, and the second binary signal is also output from the first receiving unit 1. . in this way,
The outputs of the first receiving unit 1 and the second receiving unit 2 cannot completely separate the two types of binary signals, but the first binary signal does not include a carrier component. Alternatively, by utilizing the fact that the first binary signal and the second binary signal have different formats, it is possible to easily remove the unnecessary binary signal.

If the above configuration is applied to the terminal connected to the central controller as described in the prior art, the data of the normal mode and the repair mode can be received by one signal terminal T, and the terminal T can be received. In addition to being able to reduce the number of components in the conventional configuration and transmitting a binary signal in the repair mode at an arbitrary point in time, usability is improved. It should be noted that the amplitude voltage of each binary signal described above is not intended to be limited, and the signal may be either unipolar or bipolar. Further, as for the circuit configuration, as long as it is a combination of a configuration that outputs a binary signal corresponding to a binary signal and a configuration that outputs a pulse signal corresponding to a change point of the binary signal, the configuration shown in FIG. It is not limited.

(Embodiment 2) In this embodiment, two kinds of binary signals having different amplitude voltages are transmitted to a transmission line, and two kinds of binary signals are made into amplitude voltages by a circuit configuration as shown in FIG. An example of separation based on the above will be shown. That is, the binary signal input from the signal terminal T passes through the resistor R ₇ and the diode D ₂
Is rectified by and is averaged by the parallel circuit of the capacitor C ₃ and the resistor R ₈ . The voltage across the capacitor C ₃ is applied to the comparator CP ₁ together with the reference voltage obtained by dividing the output voltage of the constant voltage circuit 10 by the resistors R ₉ and R _10.
When the voltage across the capacitor C ₃ becomes lower than the reference voltage, the output of the comparator CP ₁ is connected to the H level. A pull-up resistor R ₁₁ is connected to the output terminal of the comparator CP ₁ . That is, the resistance R ₇ to R _11, the diode D _2, a capacitor C _3, the selection unit 3 composed of a comparator CP _1.

The output of the comparator CP ₁ is input to the logic gate circuits G ₁ and G ₂ which form the gate sections 4 and 5, respectively. One logic gate circuit G ₁ inverts _one of the two inputs and outputs a logical product with the other. The other logic gate circuit G ₂ outputs a logical product of 2 inputs. The comparator CP ₁ is provided at the input end for inverting the input in the logic gate circuit G ₁ and at one input end of the logic gate circuit G _2.
Of the logic gate circuits G ₁ and G ₂ is connected to the collector of the transistor Q ₂ . The configuration of the other parts is similar to that of the first embodiment.

On the other hand, on the transmission line, a unipolar binary signal having an amplitude voltage of 24 V as shown in FIG. 5 and a unipolar binary signal having an amplitude voltage of 12 V as shown in FIG. Two types of binary signals shall be transmitted. Here, the reference voltage input to the comparator CP ₁ is the constant voltage circuit 10
The output voltage of 5V is obtained by dividing the output voltage of 5V by the resistors R ₉ and R ₁₀ and is 5V or less, but the voltage across the capacitor C ₃ is divided by the resistors R ₇ and R ₈ . Therefore, if the values of the resistors R _{7 to} R ₁₀ are adjusted, the output of the comparator CP ₁ becomes the L level for the binary signal having the amplitude voltage of 24V, and the binary signal having the amplitude voltage of 12V is obtained. It is possible to set the comparator CP _{2 to} be at the H level. That is, the reference voltage may be set so as to correspond to the case where the amplitude voltage is 18V, for example.

With this setting, the amplitude voltage is 24V.
For binary signal is a logic output of the gate circuit G ₂ is always L level, the logic gate circuit G ₁ outputs L level when the ON transistor Q _2, the transistor Q ₂
Goes to H level when turned off. That is, as shown in FIG. 5B, the amplitude voltage is 5 V from the logic gate circuit G ₁ .
Therefore, the binary signal S ₁ whose logical value is inverted with respect to the binary signal input from the signal terminal T is output.

For a binary signal having an amplitude voltage of 12 V, the output of the logic gate circuit G ₁ is always at L level, the output of the logic gate circuit G ₂ is at L level when the transistor Q ₂ is on, It goes high when the transistor Q ₂ is off. That is, from the logic gate circuit G ₂ to FIG.
As shown in (b), a binary signal having an amplitude voltage of 5 V and a logical value inverted from that of the binary signal input from the signal terminal T is output.

In the above configuration, the binary signals S ₁ and S ₂ corresponding to the two types of binary signals having different amplitude voltages can be output from the respective logic gate circuits G ₁ and G ₂ , and the two types of binary signals can be output. The value signals can be separated. With this configuration, there is no need to distinguish between the two signals due to the presence or absence of carriers or the difference in the format on the subsequent stage, and it has the advantage that they can be separated if only the amplitude voltage is different regardless of the signal format. There is. Moreover, it can be used regardless of whether it is monopolar or bipolar. Also, the gate parts 4, 5
Although the example using the logic gate circuits G ₁ and G ₂ has been shown as an example, a relay or a switching element such as another FET can be used instead of the logic gate circuits G ₁ and G ₂ . Further, not only two kinds of binary signals but also three or more kinds of binary signals can be separated by setting the reference voltage in multiple steps and providing the gate parts 4 and 5 which are opened selectively in each step. You can also

(Embodiment 3) In the present embodiment, as in the case of Embodiment 2, when two kinds of binary signals having different amplitude voltages are transmitted to the transmission line, these binary signals can be separated. The configuration is shown below. In this embodiment, as shown in FIG. 7, the binary signal input to the signal terminal T is supplied to the resistors R ₁₂ , R without turning on / off the transistor Q ₂ by the binary signal.
_The voltage is divided by ₁₃ , and the reference voltage and the voltage at the connection point of both resistors R ₁₂ , R ₁₃ are compared by _two comparators CP ₂ , CP ₃ provided as comparators 6, 7. A reference voltage obtained by dividing the output voltage of the constant voltage circuit 10 by the resistors R ₁₄ , R ₁₅ , and R ₁₆ is input to each of the comparators CP ₁ and CP ₂ , and each reference voltage is set to a different value. There is.
Each of the comparators CP ₂ and CP ₃ sets the output to the H level when the voltage at the connection point of the resistors R ₁₂ and R ₁₃ is less than or equal to the set reference voltage, and sets the output to the L level when the voltage exceeds the reference voltage. Further, pull-up resistors R ₁₇ and R ₁₈ are connected to the output terminals of the comparators CP ₂ and CP ₃ , respectively.

Similar to the second embodiment, the amplitude voltage is 24 V and 1
Assuming that a unipolar binary signal of 2V is transmitted,
The reference voltage of the comparator CP ₂ is set so that the input voltage to the signal terminal T corresponds to a voltage between 12 V and 24 V (for example, 20 V), and the reference voltage of the comparator CP ₃ is the input voltage to the signal terminal T. It is set to correspond to a voltage lower than 12V (for example, 6V). Therefore, when a binary signal having an amplitude voltage of 24V is input, the outputs of both comparators CP ₂ and CP ₃ both become L level while the binary signal is at H level.
During the period when the value signal is at L level, both comparators C
The outputs of P ₂ and CP ₃ both become H level. On the other hand, in the case of a binary signal having an amplitude voltage of 12V, the output of the comparator CP ₂ is always at H level, and the comparator C 2
The output of P ₃ becomes L level while the binary signal is at H level, and becomes H level while the binary signal is at L level. Eventually, the comparator CP ₂ outputs the binary signal S _{1 which} is the inverted logical value of both binary signals, and the comparator CP ₃ inverts the logical value of only the binary signal whose amplitude voltage is 12V. The value signal S ₂ will be output.

Although both binary signals are output from the comparator CP ₂ , unnecessary binary signals can be removed depending on the presence or absence of carriers and the format as in the first embodiment. It is also possible to provide a logic circuit after the comparators CP ₂ and CP ₃ to separate the two signals. Other configurations are similar to those of the first embodiment. (Embodiment 4) In the present embodiment, a case will be described in which two types of binary signals, each having a single pole and opposite polarities, are input to the signal terminal T. In the present embodiment, as shown in FIG. 8, in the conventional configuration shown in FIG. 10, the signal terminal T ₂ is omitted, and one end of the base resistor R ₅ connected to the base of the transistor Q ₃ is connected to the full-wave rectifier RE. It is connected to one input terminal. That is, one terminal t ₁ of the signal terminal T is connected to one end of the base resistor R ₃ connected to the base of the transistor Q ₂ , and the other terminal t of the signal terminal T is connected.
₂ is connected to one end of a base resistor R ₅ connected to the base of the transistor Q ₃ . The transistor Q ₂ , the base resistor R ₃ , and the resistor R ₄ constitute the receiving unit 8,
The transistor Q ₃ , the base resistor R ₅ , and the resistor R _{6 form} the receiving unit 9.

[0033] In this configuration, the transistor Q ₂ is turned on when the terminal t ₁ is the positive terminal t ₂ as a reference, the transistor Q ₃ is turned on when the terminal t ₂ is the positive terminal t ₁ as a reference . In other states, both transistors Q ₂ and Q ₃ are off. Therefore, as shown in FIG. 9A, when two kinds of binary signals having opposite polarities are input to the signal terminal T, a binary signal having a positive polarity as shown in the left half of FIG. Is a binary signal S ₁ whose logic value is inverted as shown in FIG.
It is output from the collector of No. ₂ , and at this time, the collector of the transistor Q ₃ is maintained at the H level as shown in FIG. 9 (c). Further, as shown in FIG. 9B, the collector of the transistor Q ₂ is kept at H level for a binary signal of negative polarity as shown in the right half of FIG. 9A.
As shown in (c), the binary signal S ₂ whose logical value is inverted is output from the collector of the transistor Q ₃ . Therefore, two kinds of binary signals can be separated and taken out by the transistors Q ₂ and Q ₃ .

By the way, in the above configuration, since the binary signals input to the signal terminal T can be separated if they have opposite polarities, the binary signal for the transmission line can be separated only when transmitting the binary signals that need to be separated. The connection on the transmitting side or the receiving side may have opposite polarities. Such a configuration is realized, for example, by providing the transmitting side with a switch for switching the polarity. With such a configuration, when the normal mode and the repair mode are provided as in the conventional example, the connection relation to the transmission path is set to the opposite polarity only in the repair mode in which the opportunity is small. Thus, the signals transmitted in the normal mode and the repair mode can be completely separated, and malfunctions can be prevented. Other configurations are similar to those of the first embodiment.

[0035]

As described above, according to the first aspect of the invention, the first binary signal for identifying the digital value by the pulse width and the second binary signal for identifying the digital value by the other attribute of the pulse are provided. Of the two binary signals of
The binary signal corresponding to the value signal is output from the first receiving unit,
A pulse signal corresponding to the change point of the second binary signal is output from the second receiving unit, and the input terminals of the first receiving unit and the second receiving unit are commonly connected to the signal terminal. Because
A pulse width modulated binary signal and a binary signal of another modulation method such as pulse amplitude modulation, pulse phase modulation and pulse number modulation are separated by the outputs of the first receiving section and the second receiving section. The effect is that you can. In this case, the second
The binary signal corresponding to the binary signal of is also obtained as the output of the first receiving section, and the pulse signal corresponding to the change point of the first binary signal is also obtained as the output of the second receiving section. But,
Since it is possible to discriminate based on the presence / absence of a carrier or the difference in format, no problem occurs. In addition, since the two types of signals are separated by the first receiving section and the second receiving section and the input ends of both receiving sections are commonly connected to the signal terminal,
There is an advantage that two types of signals can be transmitted to one transmission line. As described above, as a result of being able to separate the two types of signals transmitted to one transmission line, both signals can be transmitted at any time, and, for example, the function setting of the terminal device as described in the related art is explained. Even when setting, correcting, and confirming the contents of the memory for use, the work can be performed at any time during the operation of the system, and there is an advantage that the usability is improved.

According to a third aspect of the present invention, a plurality of types of binary signals having different amplitude voltages are transmitted to the transmission line, and a plurality of gate sections are selected according to the selection signal output from the selection section for each amplitude voltage. Since they are opened once, the binary signal of each amplitude voltage can be taken out only from the corresponding gate section. That is, since the input end of the gate section is commonly connected to the signal terminal, there is an advantage that a plurality of types of binary signals transmitted on one transmission path can be separated by the selection section and the gate section.

According to a fourth aspect of the present invention, a plurality of types of binary signals having different amplitude voltages are transmitted to a transmission line, and the amplitude voltages of the binary signals are respectively compared with a reference voltage by a plurality of comparators, whereby each amplitude voltage is compared. Since the binary signal of 2 is separated, there is an advantage that the binary signal of each amplitude voltage can be taken out only from the corresponding comparing section. Further, since the input ends of the comparison units are commonly connected to the signal terminals, there is an advantage that a plurality of types of binary signals transmitted on one transmission path can be separated by the comparison unit.

According to the fifth aspect of the present invention, each is a single pole.
Two types of binary signals are transmitted to the transmission line, and each binary signal is input as an opposite polarity, and two receiving units for outputting binary signals corresponding to the binary signals of each polarity are provided. Therefore, the binary signal corresponding to the binary signal of each polarity can be output for each receiving unit, and as a result, two types of signals can be separated as the output of each receiving unit. That is, there is an advantage that the two kinds of binary signals transmitted on one transmission path can be separated by the receiving unit.

[Brief description of drawings]

FIG. 1 is a main part circuit diagram showing a first embodiment.

FIG. 2 is an operation explanatory diagram of the first embodiment.

FIG. 3 is an operation explanatory diagram of the first embodiment.

FIG. 4 is a main part circuit diagram showing a second embodiment.

FIG. 5 is an operation explanatory diagram of the second embodiment.

FIG. 6 is an operation explanatory diagram of the second embodiment.

FIG. 7 is a main part circuit diagram showing a third embodiment.

FIG. 8 is a main part circuit diagram showing a fourth embodiment.

FIG. 9 is an operation explanatory diagram of the fourth embodiment.

FIG. 10 is a main part circuit diagram showing a conventional example.

[Explanation of symbols]

1 1st receiving part 2 2nd receiving part 3 Selection part 4 Gate part 5 Gate part 6 Comparison part 7 Comparison part 8 Reception part 9 Reception part C ₂ Capacitor T Signal terminal t ₁ terminal t ₂ terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Koyama 1048 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Co., Ltd.

Claims (5)

[Claims] 1. A binary data signal transmitted through a transmission line in a digital data receiving apparatus which is connected to a transmission line through which different types of binary signals are transmitted and which receives and separates each type of binary signal. Is a first binary signal for identifying a digital value by a pulse width and a second binary signal for identifying a digital value by another attribute of a pulse.
And a second receiving unit for outputting a pulse signal corresponding to a change point of the second binary signal, and a second receiving unit for outputting a binary signal corresponding to the binary signal A digital data receiving apparatus, characterized in that the input terminals of the first receiving section and the second receiving section are commonly connected to the signal terminal. 2. The digital data receiving apparatus according to claim 1, wherein the second receiving unit receives a binary signal from a signal terminal via a capacitor. 3. A binary signal transmitted through a transmission line in a digital data receiving device which is connected to a transmission line through which different types of binary signals are transmitted and which receives and separates each type of binary signal. Of the binary signals having different amplitude voltages, detecting the amplitude voltage of each binary signal and outputting a selection signal according to the amplitude voltage, and selectively selecting the binary signal of each amplitude voltage in response to the selection signal. A digital data receiving device, characterized in that a plurality of gate portions that can pass through are provided, and input terminals of the respective gate portions are commonly connected to signal terminals connected to a transmission path. 4. A binary signal transmitted through a transmission line in a digital data receiving device which is connected to a transmission line through which different types of binary signals are transmitted and which receives and separates each type of binary signal. A plurality of comparing units for separating the binary signals of the respective amplitude voltages by differentiating the amplitude voltages of the respective signals from each other and comparing the amplitude voltage of the binary signal with the reference voltage, and to each of the signal terminals connected to the transmission line. A digital data receiving device, characterized in that the input ends of the comparison units are commonly connected. 5. A binary signal transmitted through a transmission line in a digital data receiving apparatus which is connected to a transmission line through which a plurality of different types of binary signals are transmitted and which receives and separates each type of binary signal. Are two types of single poles and have different polarities from each other, and two receiving sections for outputting a binary signal corresponding to the binary signal for each polarity are provided, and both receiving sections are provided at the signal terminal connected to the transmission path. A digital data receiving device, characterized in that the input terminals of are connected in common.