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JPH07106717A - Laminated composite electronic component - Google Patents

Laminated composite electronic component

Info

Publication number
JPH07106717A
JPH07106717A JP5268405A JP26840593A JPH07106717A JP H07106717 A JPH07106717 A JP H07106717A JP 5268405 A JP5268405 A JP 5268405A JP 26840593 A JP26840593 A JP 26840593A JP H07106717 A JPH07106717 A JP H07106717A
Authority
JP
Japan
Prior art keywords
laminated
linear expansion
electronic component
expansion coefficient
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5268405A
Other languages
Japanese (ja)
Other versions
JP3250166B2 (en
Inventor
Kazutaka Suzuki
一高 鈴木
Masanori Tomaru
昌典 渡丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP26840593A priority Critical patent/JP3250166B2/en
Publication of JPH07106717A publication Critical patent/JPH07106717A/en
Application granted granted Critical
Publication of JP3250166B2 publication Critical patent/JP3250166B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To prevent a deterioration in chip-component characteristics, by using an outermost layer on the side of a mounted electronic circuit as a thermal stress relaxation layer having a coefficient of linear expansion smaller than that of the material of a laminated element adjoining to the outermost layer and larger than that of the chip component connected to the electronic circuit. CONSTITUTION:In a laminated composite electronic component, an electronic circuit is provided on a main face of a laminated element 2, in which at least one element out of a coil, a capacitor and a resistor is provided. In addition, at least an outermost layer 4 on the side of a mounted electronic component out of outermost layers on both sides is a thermal-stress relaxation layer having a coefficient of linear expansion smaller than that of the material of the laminated element adjoining to the outermost layer 4 and larger than that of the chip component 7 connected to the electronic circuit. Consequently, the electronic component can withstand a heat cycle test, and reliability in thermal stress can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層体素子に電子回路
を組み込み、一つの機能ブロックを形成した積層複合電
子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated composite electronic component in which an electronic circuit is incorporated in a laminated body element to form one functional block.

【0002】[0002]

【従来の技術】電子回路装置の小型化が要望され、その
要望を満たすために、電子部品の小型化と、電子部品を
近接して搭載する高密度実装技術の開発が進められてい
る。電子部品の小型化は、部品単体を小さくすること
と、その小さくした複数の電子素子を一つの積層電子部
品に組み込む、いわゆる複合化が進められ、その技術は
セラミック積層技術の発展とともに急速に進展し、その
完成部品は積層複合電子部品として他の個別部品と一緒
にプリント基板に搭載して使用されている。
2. Description of the Related Art There has been a demand for miniaturization of electronic circuit devices, and in order to meet the demand, miniaturization of electronic components and development of high-density mounting technology for mounting electronic components in close proximity have been underway. As for miniaturization of electronic parts, so-called compounding has been promoted by reducing the size of individual parts and incorporating a plurality of smaller electronic elements into a single laminated electronic part, and this technology has rapidly progressed with the development of ceramic lamination technology. However, the completed component is mounted on a printed circuit board together with other individual components as a laminated composite electronic component for use.

【0003】積層複合電子部品としては、例えば図3に
示すように、フェライト磁性体内にコイルを埋設し、外
部電極20、20を有する積層インダクタ21の主面上
に抵抗体等の受動素子を有する導体回路を形成し、この
回路の導体ランドにトランジスタ、半導体IC等の能動
素子として例えば半導体ICのベアチップ22を導電性
接着剤23により接着する、いわゆるダイボンデングを
行い、一方該ベアチップの電極と上記導体回路の電極2
4、24を金線25、25・・で接続する、いわゆるワ
イヤボンデングを行い、そしてこの主面上の回路全体を
樹脂層26により埋め込んで複数の素子の機能を複合化
し、一つの電子回路を構成した電子部品とすることが広
く行われている。また、積層インダクタの代わりに、誘
電体磁器内にコンテンサを埋設した積層コンデンサや、
さらには積層インダクタと積層コンデンサを一体化して
得た積層体素子を上記に準じて用いることも広く行われ
ている。
As a laminated composite electronic component, for example, as shown in FIG. 3, a coil is embedded in a ferrite magnetic body, and a passive element such as a resistor is provided on the main surface of a laminated inductor 21 having external electrodes 20, 20. Conductor circuit is formed, and as an active element such as a transistor or a semiconductor IC, a bare chip 22 of a semiconductor IC is adhered to the conductor land of the circuit by a conductive adhesive 23, that is, so-called die bonding is performed, while the electrode of the bare chip and the conductor are connected. Circuit electrode 2
4 and 24 are connected by gold wires 25, 25 ..., So-called wire bonding is performed, and the entire circuit on this main surface is filled with a resin layer 26 to combine the functions of a plurality of elements to form an electronic circuit. Is widely used as an electronic component. Also, instead of a laminated inductor, a laminated capacitor in which a contenter is embedded in a dielectric ceramic,
Further, it is widely used to use a laminated body element obtained by integrating a laminated inductor and a laminated capacitor in accordance with the above.

【0004】このような積層複合電子部品の信頼性を保
証する一つの目安として、ヒートサイクルテストという
加速試験方法がある。この方法は、試験対象の部品を−
55℃の温度雰囲気中に30分間放置した後、速やかに
125℃の温度雰囲気中に移行させ、その温度で30分
放置する操作を1サイクルとし、連続500サイクル繰
り返し、試験前後の特性を比較してJIS等に定める規
格以内であるかどうかをみるものであり、規格内であれ
ば信頼性が保証されたとするものである。
As one measure for guaranteeing the reliability of such a laminated composite electronic part, there is an accelerated test method called a heat cycle test. In this method, the component under test is
After being left in a 55 ° C temperature atmosphere for 30 minutes, immediately shifting to a 125 ° C temperature atmosphere and left at that temperature for 30 minutes was defined as one cycle. Repeated 500 cycles, and compared the characteristics before and after the test. It is to check whether or not it is within the standard defined by JIS etc., and if it is within the standard, the reliability is guaranteed.

【0005】[0005]

【発明が解決しようとする課題】半導体ベアチップを搭
載した積層複合電子部品に上記ヒートサイクルテストを
行うと、半導体ベアチップにクラックが入り、その特性
が低下することがあるという課題があった。
When the above-mentioned heat cycle test is performed on the laminated composite electronic component on which the semiconductor bare chip is mounted, there is a problem that the semiconductor bare chip may be cracked and its characteristics may be deteriorated.

【0006】本発明の目的は、ヒートサイクルテストを
行ってもチップ部品の特性を低下させることのない積層
複合電子部品を提供することにある。
An object of the present invention is to provide a laminated composite electronic component which does not deteriorate the characteristics of the chip component even when a heat cycle test is performed.

【0007】[0007]

【課題を解決するための手段】本発明は、上記課題を解
決するために、コイル、コンデンサ及び抵抗体の少なく
とも一つの素子を内部に有する積層体素子の主面に電子
回路を有する積層複合電子部品において、該積層体素子
の両主面を構成する最外層の内少なくとも電子回路を搭
載する側の最外層は該最外層に隣接する該積層体素子の
素地の線膨脹係数より小さく、該電子回路に接続される
チップ部品の線膨脹係数より大きい線膨脹係数を有する
熱応力緩和層である積層複合電子部品を提供するもので
ある。この際、積層体素子の両主面を構成する両方の最
外層が当該それぞれの最外層に隣接する該積層体素子の
素地の線膨脹係数より小さく、該電子回路に接続される
チップ部品の線膨脹係数より大きい線膨脹係数を有する
熱応力緩和層であること、この熱応力緩和層の線膨脹係
数が2〜7×10-6/℃であること、この熱応力緩和層
と積層体素子の素地との間に両者の成分が拡散した拡散
層を有することが好ましい。
In order to solve the above-mentioned problems, the present invention provides a laminated composite electronic device having an electronic circuit on the main surface of a laminated device having at least one of a coil, a capacitor and a resistor inside. In the component, at least the outermost layer of the outermost layers forming both main surfaces of the laminate element on the side on which the electronic circuit is mounted is smaller than the linear expansion coefficient of the substrate of the laminate element adjacent to the outermost layer, Provided is a laminated composite electronic component which is a thermal stress relaxation layer having a linear expansion coefficient larger than that of a chip component connected to a circuit. At this time, both outermost layers forming both main surfaces of the laminated element are smaller than the linear expansion coefficient of the base material of the laminated element adjacent to the respective outermost layers, and the wire of the chip component connected to the electronic circuit. The thermal stress relaxation layer has a linear expansion coefficient larger than the expansion coefficient, the linear expansion coefficient of the thermal stress relaxation layer is 2 to 7 × 10 −6 / ° C., and the thermal stress relaxation layer and the laminated element are It is preferable to have a diffusion layer in which both components are diffused between the base material and the base material.

【0008】本発明において、熱応力緩和層は、その隣
接する積層体素子の素地の線膨脹係数より小さく、電子
回路に接続されるチップ部品の線膨脹係数より大きい線
膨脹係数を有するが、積層体素子の素地は、例えばフェ
ライト磁性体層の線膨脹係数が10〜11×10-6
℃、セラミック誘電体層の線膨脹係数が9〜10×10
-6/℃であり、一方チップ部品、例えは半導体ベアチッ
プの線膨脹係数はシリコーン基板が用いられるので2〜
3×10-6/℃であるから、積層体素子の素地の線膨脹
係数と半導体ベアチップの線膨脹係数の中間の線膨脹係
数である、2〜7×10-6/℃の線膨脹係数を有するこ
とが好ましい。熱応力緩和層の線膨脹係数が2×10-6
/℃より小さいと、熱応力緩和層と積層体素子の素地と
の間にクラックが入り易く、7×10-6/℃より大きい
とチップ部品にクラックが入り易い。熱応力緩和層と積
層体素子に搭載されるチップ部品との線膨脹係数の比が
3程度であれば、チップ部品にクラックの入ることが少
なく、5を越えるとクラックの入る割合が多くなり、不
良率が大きくなる。フェライト磁性体層にベアチップを
搭載した際の不良率は、セラミック誘電体層にベアチッ
プを搭載した際の不良率より高い。シリコーンを基板と
する他のチップ部品やその他のチップ部品についても上
記のことに準じて考えられる。熱応力緩和層としての材
料としては、アルミナ粉末その他の無機粉末、ホウケイ
酸鉛ガラスその他のガラス粉末、これらの混合物その他
のセラミック粉末が挙げられる。
In the present invention, the thermal stress relaxation layer has a coefficient of linear expansion smaller than that of the base material of the adjoining laminated body element and larger than that of the chip part connected to the electronic circuit. The base material of the body element has, for example, a coefficient of linear expansion of the ferrite magnetic layer of 10 to 11 × 10 −6 /
C, the coefficient of linear expansion of the ceramic dielectric layer is 9 to 10 × 10
-6 / ° C. On the other hand, the coefficient of linear expansion of chip parts, for example, bare semiconductor chips, is 2 because the silicon substrate is used.
Since it is 3 × 10 −6 / ° C., a linear expansion coefficient of 2 to 7 × 10 −6 / ° C., which is an intermediate linear expansion coefficient between the linear expansion coefficient of the substrate of the laminated device and the linear expansion coefficient of the bare semiconductor chip, is set. It is preferable to have. The linear expansion coefficient of the thermal stress relaxation layer is 2 × 10 -6
If it is lower than / ° C, cracks are likely to occur between the thermal stress relaxation layer and the base material of the laminated body element, and if it is higher than 7 × 10 -6 / ° C, cracks are likely to occur in the chip parts. If the ratio of the coefficient of linear expansion between the thermal stress relaxation layer and the chip component mounted on the laminated body element is about 3, cracks are less likely to occur in the chip component, and if it exceeds 5, the rate of cracking increases. The defective rate increases. The defective rate when the bare chip is mounted on the ferrite magnetic layer is higher than the defective rate when the bare chip is mounted on the ceramic dielectric layer. Other chip parts using silicone as a substrate and other chip parts can be considered according to the above. Examples of the material for the thermal stress relaxation layer include alumina powder and other inorganic powders, lead borosilicate glass and other glass powders, mixtures thereof, and other ceramic powders.

【0009】[0009]

【作用】積層体素子の素地とチップ部品の線膨脹係数が
異なり、熱による伸縮の割合が大きく異なってもその応
力をその中間の線膨脹係数を有する熱応力緩和層により
緩和できる。特にこの中間の線膨脹係数を有する熱応力
緩和層は、これと接する積層体素子の素地と互いに各成
分が拡散しあい、両者の中間の線膨脹係数を有する拡散
層が形成され、熱応力緩和層と積層体素子の素地のそれ
ぞれとの応力を緩和する効果がある。
When the base material of the laminated element and the chip component have different linear expansion coefficients and the rate of expansion and contraction due to heat is greatly different, the stress can be relaxed by the thermal stress relaxation layer having an intermediate linear expansion coefficient. In particular, in the thermal stress relaxation layer having an intermediate linear expansion coefficient, each component diffuses into the base material of the laminated element in contact with the thermal stress relaxation layer, and a diffusion layer having an intermediate linear expansion coefficient between the two is formed. It has the effect of relieving the stress on each of the bases of the laminated body element.

【0010】[0010]

【実施例】次に本発明の実施例を説明する。 実施例1 Ni−Znを主成分とする厚さ80μmの多数のフェラ
イト磁性体グリーンシートを作成し、その何枚かにスル
ホールを形成するとともに導電ペーストのAg─Pdペ
ーストをスクリーン印刷することにより、それぞれに全
体としてコイルを形成するようにそのコイルの一部を形
成するコイル導体バターン塗膜を形成し、それらをコイ
ル導体バターン塗膜がコイルを形成するように重ね合わ
せ、さらにカバーシートとして上記フェライト磁性体グ
リーンシーの複数枚をその両端に重ね合わせ、積層イン
ダクタ未焼成体を作成する。なお、コイルの両端に当た
るコイル導体バターン塗膜はフェライト磁性体グリーン
シートの端部まで引き出され、後に外部電極と接続され
る。一方、Al2 3 とホウケイ酸鉛ガラスを主成分と
する厚さ100μmの絶縁体グリーンシートを作成す
る。次に、上記積層インダクタ未焼成体の両主面のそれ
ぞれに上記絶縁体グリーンシートを重ね、ついで圧着
し、積層インダクタ未焼成圧着体を作成する。実際には
上記積層インダクタ未焼成圧着体は個々に作成されるの
ではなく、1単位のシート重ね体にその多数が形成さ
れ、圧着後個々の積層インダクタ未焼成圧着体に切断さ
れる。
EXAMPLES Examples of the present invention will be described below. Example 1 A large number of ferrite magnetic green sheets having a thickness of 80 μm containing Ni—Zn as a main component were formed, through holes were formed in several of them, and the Ag—Pd paste of a conductive paste was screen-printed. Form a coil conductor pattern film forming a part of the coil so as to form a coil as a whole on each, and superimpose them so that the coil conductor pattern film forms a coil, and further use the above ferrite as a cover sheet. A plurality of magnetic green sheets are superposed on both ends thereof to form a laminated inductor unfired body. The coating film of the coil conductor pattern which hits both ends of the coil is pulled out to the end of the ferrite magnetic green sheet, and is later connected to the external electrode. On the other hand, a 100 μm thick insulator green sheet containing Al 2 O 3 and lead borosilicate glass as main components is prepared. Next, the above-mentioned insulator green sheets are stacked on both main surfaces of the above-mentioned laminated inductor unfired body, and then pressure-bonded to form a laminated inductor unfired pressure-bonded body. Actually, the multilayer inductor unfired crimped body is not individually manufactured, but a large number of the laminated inductors are formed in one sheet stack, and after the crimping, they are cut into individual laminated inductor unfired crimped bodies.

【0011】この個々の積層インダクタ未焼成圧着体を
900℃、60分焼成し、図1に示す複合用積層インダ
クタ1を得る。この複合用積層インダクタ1について、
各部分を削り取って線膨脹係数を測定したところ、積層
インダクタ本体2と、それぞれ50μmの拡散層3、3
と、 それぞれ75μmのセラミック絶縁体層4、4に
分かれることがわかった。すなわち、積層インダクタ本
体2はその素地の線膨脹係数が11×10-6/℃であ
り、セラミック絶縁体層4、4の線膨脹係数は5×10
-6/℃であり、拡散層3、3の線膨脹係数は8×10-6
/℃であった。なお、後述の半導体ベアチップの線膨脹
係数は2.4×10-6/℃であった。
The individual laminated inductor unfired crimped body is fired at 900 ° C. for 60 minutes to obtain the composite laminated inductor 1 shown in FIG. Regarding this composite laminated inductor 1,
When the linear expansion coefficient was measured by scraping off each part, the laminated inductor body 2 and the diffusion layers 3 and 3 of 50 μm respectively were measured.
It was found that the ceramic insulating layers 4 and 4 each had a thickness of 75 μm. That is, in the laminated inductor body 2, the linear expansion coefficient of the substrate is 11 × 10 −6 / ° C., and the linear expansion coefficient of the ceramic insulator layers 4 and 5 is 5 × 10.
-6 / ° C, and the coefficient of linear expansion of the diffusion layers 3 and 3 is 8 × 10 -6
/ ° C. The coefficient of linear expansion of the semiconductor bare chip described later was 2.4 × 10 −6 / ° C.

【0012】この複合用積層インダクタ1の一方の主面
に導体ランド塗膜を有する厚膜導体塗膜、厚膜抵抗体塗
膜をスクリーン印刷により形成し、焼き付け、それぞれ
導体ランドを有する配線導体と抵抗体を有する厚膜回路
を形成する。ついで、コイル導体塗膜の焼成体からなる
コイル導体が導出されている積層インダクタ本体2の外
側面及び上記拡散層3、3、セラミック絶縁体層4、4
の対応する外側面にそのコイル導体の端部に接続する外
部電極塗膜をスクリーン印刷法により形成して焼付け、
外部電極5、5・・を形成する。
A thick conductor coating film having a conductor land coating film and a thick film resistor coating film are formed on one main surface of the composite laminated inductor 1 by screen printing and baked to form a wiring conductor having conductor lands. A thick film circuit having a resistor is formed. Then, the outer surface of the laminated inductor body 2 from which the coil conductor made of the fired body of the coil conductor coating film is drawn out, the diffusion layers 3 and 3, the ceramic insulator layers 4 and 4.
The external electrode coating film to be connected to the end of the coil conductor is formed on the corresponding outer surface of the by screen printing method and baked,
External electrodes 5, 5 ... Are formed.

【0013】このように外部電極を形成した複合用積層
インダクタ1のセラミック絶縁体層4、4の一方の主面
に形成した導体ランド6に半導体ベアチップ7を導電性
エポキシ樹脂接着剤8でダイボンデングし、この半導体
ベアチップ7の他の電極と配線導体の電極9、9とを金
線10、10・・でワイヤボンデングする。そしてその
主面内に形成された半導体ベアチップ7を含む電子回路
全体を樹脂層11により埋め込む。このようにして、複
合用積層インダクタ1の一方の主面に電子回路を設け、
フェライト磁性体内のインダクタと接続した積層複合電
子部品ができあがる。
The semiconductor bare chip 7 is die-bonded with the conductive epoxy resin adhesive 8 to the conductor lands 6 formed on one main surface of the ceramic insulator layers 4 and 4 of the composite laminated inductor 1 having the external electrodes thus formed. The other electrodes of the semiconductor bare chip 7 and the electrodes 9, 9 of the wiring conductor are wire-bonded with the gold wires 10, 10 ,. Then, the entire electronic circuit including the semiconductor bare chip 7 formed in the main surface is embedded with the resin layer 11. In this way, an electronic circuit is provided on one main surface of the composite laminated inductor 1,
A laminated composite electronic component connected to an inductor in a ferrite magnet is completed.

【0014】このような積層複合電子部品としてDC−
DCコンバータを50個作成し、その出力特性を測定し
たところ、いずれも規格を満足していた。また、上述の
ヒートサイクルテストを行ない、連続して500サイク
ル繰り返した後、DC−DCコンバータの出力特性を測
定した結果、規格を越えて異常と判断されるものは皆無
であった。
As such a laminated composite electronic component, DC-
When 50 DC converters were created and their output characteristics were measured, all of them satisfied the standard. In addition, as a result of performing the above-mentioned heat cycle test and continuously repeating 500 cycles and then measuring the output characteristics of the DC-DC converter, none of them was judged to be abnormal beyond the standard.

【0015】実施例2 図2に示すように、実施例1と同様に複合用積層インダ
クタ1を作成し、その一方の主面に実施例1と同様の方
法で異なる導体回路を形成し、その電極12、12に面
実装型半導体ICチップ13のバンプ14、14をはん
だ付けにより接続し、その主面周縁にこのチップを含む
全体の電子回路を囲う枠体15を設ける。
Example 2 As shown in FIG. 2, a composite laminated inductor 1 was prepared in the same manner as in Example 1, and a different conductor circuit was formed on one of its main surfaces by the same method as in Example 1, and The bumps 14 and 14 of the surface-mounted semiconductor IC chip 13 are connected to the electrodes 12 and 12 by soldering, and a frame 15 that surrounds the entire electronic circuit including this chip is provided on the periphery of the main surface.

【0016】実施例3 実施例1において、セラミック絶縁体層の線膨脹係数を
5×10-6/℃とするように、Al2 3 とホウケイ酸
鉛ガラスの比率を変えた絶縁体グリーンシートを用いた
以外は同様にしてDC−DCコンバータを50個作成
し、これらについても実施例1と同様に試験したとこ
ろ、異常と判断されるものは皆無であった。
Example 3 Insulator green sheet in which the ratio of Al 2 O 3 and lead borosilicate glass was changed so that the linear expansion coefficient of the ceramic insulator layer was 5 × 10 −6 / ° C. in Example 1. 50 DC-DC converters were prepared in the same manner except that the above was used, and these were also tested in the same manner as in Example 1. As a result, none were judged to be abnormal.

【0017】実施例4 チタン酸バリウムを主成分とする誘電体グリーンシート
を多数作成し、その何枚かにスクリーン印刷法により導
電ベーストからなる内部電極塗膜を印刷し、それらをそ
れぞれの誘電体グリーンシートを介して内部電極塗膜が
対向するように重ね、さらにその重ね体の上下両端にカ
バーシートとして複数の上記誘電体グリーンシートを重
ね、積層コンデンサ未焼成体を作成する。なお、両端の
内部電極塗膜はシートの端部まで引き出し、後述の外部
電極と接続できるようにする。そして、この積層コンデ
ンサ未焼成体と実施例1で作成したと同様の積層インダ
クタ未焼成体とを重ね、さらにその両端にそれぞれ実施
例1で用いた絶縁体グリーンシートを重ね、圧着して積
層LC未焼成圧着体を作成する。実際には、積層LC未
焼成圧着体は個々に作成するのではなく、1単位のシー
ト重ね体にその多数が形成され、圧着後個々の積層LC
未焼成圧着体に切断される。この積層LC未焼成圧着体
を焼成し、積層インダクタと積層コンデンサからなる複
合用積層LC体を作成した。実施例1と同様に、この複
合用積層LC体に積層インダクタの両端のコイル導体、
積層コンデンサの両端の内部電極に接続する外部電極を
形成するとともに、その一方の主面に導体回路を形成し
て半導体ベアチップを接続し、積層複合電子部品を作成
した。このような積層複合電子部品としてドルビ─ノイ
ズリダクションをを50個作成し、そのレスポンス特性
を測定したところ、異常と判断されるものは皆無であっ
た。
Example 4 A large number of dielectric green sheets containing barium titanate as a main component were prepared, and an internal electrode coating film made of a conductive base was printed on some of the sheets by a screen printing method, and these were coated with respective dielectric layers. The internal electrode coating films are laminated so as to face each other via the green sheet, and a plurality of the above-mentioned dielectric green sheets are laminated as cover sheets on the upper and lower ends of the laminated body to prepare a multilayer capacitor unfired body. The internal electrode coating film on both ends is pulled out to the end portion of the sheet so that it can be connected to external electrodes described later. Then, the unbaked body of the multilayer capacitor and the unbaked body of the multilayer inductor similar to those prepared in Example 1 are stacked, and the green sheets of the insulator used in Example 1 are stacked on both ends of the stacked body and pressure-bonded to form a laminated LC. Create a green compact. Actually, the laminated LC unsintered pressure-bonded bodies are not individually prepared, but a large number of them are formed in a sheet stack of one unit.
Cut into unfired crimps. This laminated LC unfired pressure-bonded body was fired to prepare a composite laminated LC body including a laminated inductor and a laminated capacitor. In the same manner as in Example 1, this composite laminated LC body was provided with coil conductors at both ends of the laminated inductor,
External electrodes connected to the internal electrodes on both ends of the multilayer capacitor were formed, and a conductor circuit was formed on one main surface of the external electrode to connect a semiconductor bare chip to produce a multilayer composite electronic component. When 50 Dolby noise reductions were prepared as such laminated composite electronic parts and the response characteristics were measured, none were judged to be abnormal.

【0018】参考例1 実施例1において、セラミック絶縁体層の線膨脹係数を
8×10-6/℃とするように、Al2 3 とホウケイ酸
鉛ガラスの比率を変えた絶縁体グリーンシートを用いた
以外は同様にしてDC−DCコンバータを50個作成
し、これらについても実施例1と同様に試験したとこ
ろ、異常と判断されるものは5個あった。
Reference Example 1 Insulator green sheet in which the ratio of Al 2 O 3 and lead borosilicate glass was changed so that the linear expansion coefficient of the ceramic insulator layer was 8 × 10 −6 / ° C. in Example 1. 50 DC-DC converters were prepared in the same manner except that No. 1 was used, and these were also tested in the same manner as in Example 1. As a result, 5 were judged to be abnormal.

【0019】参考例2 実施例1において、セラミック絶縁体層の線膨脹係数を
9×10-6/℃とするように、Al2 3 とホウケイ酸
鉛ガラスの比率を変えた絶縁体グリーンシートを用いた
以外は同様にしてDC−DCコンバータを50個作成
し、これらについても実施例1と同様に試験したとこ
ろ、異常と判断されるものは10個あった。
Reference Example 2 Insulator green sheet in which the ratio of Al 2 O 3 and lead borosilicate glass was changed so that the linear expansion coefficient of the ceramic insulator layer was 9 × 10 −6 / ° C. in Example 1. 50 DC-DC converters were prepared in the same manner except that No. was used, and these were also tested in the same manner as in Example 1. As a result, 10 were judged to be abnormal.

【0020】参考例3 実施例1において、セラミック絶縁体層の線膨脹係数を
1×10-6/℃とするように、Al2 3 、ホウケイ酸
鉛ガラス、石英ガラスの比率を変えた絶縁体グリーンシ
ートを用いた以外は同様にしてDC−DCコンバータを
50個作成し、これらについても実施例1と同様に試験
したところ、異常と判断されるものは5個あった。
Reference Example 3 Insulation in which the ratio of Al 2 O 3 , lead borosilicate glass, and quartz glass was changed so that the linear expansion coefficient of the ceramic insulator layer was 1 × 10 −6 / ° C. in Example 1. 50 DC-DC converters were prepared in the same manner except that the body green sheet was used, and these were also tested in the same manner as in Example 1. As a result, 5 were judged to be abnormal.

【0021】[0021]

【発明の効果】本発明によれば、積層体素子の素地の線
膨脹係数より小さく、積層体素子に設けられる電子回路
に接続されるチップ部品の線膨脹係数より大きい線膨脹
係数を有する熱応力緩和層を積層体素子とチップ部品の
間に設けたので、上記したヒートサイクルテストにも耐
える積層複合電子部品を提供することがてき、例えば半
導体ベアチップにクラックが入ることがなく、熱応力
(ヒートショック)に対する信頼性を向上することがで
きる。
According to the present invention, the thermal stress has a linear expansion coefficient smaller than that of the base material of the laminated body element and larger than that of the chip part connected to the electronic circuit provided in the laminated body element. Since the relaxation layer is provided between the laminated element and the chip component, it is possible to provide a laminated composite electronic component that can withstand the above-mentioned heat cycle test. For example, the semiconductor bare chip is not cracked, and thermal stress (heat Reliability against shock) can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の積層複合電子部品の縦
断面図である。
FIG. 1 is a vertical sectional view of a laminated composite electronic component according to a first embodiment of the present invention.

【図2】その第2の実施例の積層複合電子部品の縦断面
図である。
FIG. 2 is a vertical sectional view of a laminated composite electronic component according to a second embodiment.

【図3】従来の積層複合電子部品の縦断面図である。FIG. 3 is a vertical sectional view of a conventional laminated composite electronic component.

【符号の説明】[Explanation of symbols]

1 複合用積層インダクタ 2、2 積層インダクタ本体 3、3 拡散層 4、4 セラミック絶縁体層 7 ベアチップ 13 面実装型の半導体ICチップ 1 Composite Multilayer Inductor 2, 2 Multilayer Inductor Main Body 3, 3 Diffusion Layer 4, 4 Ceramic Insulator Layer 7 Bare Chip 13 Surface Mount Semiconductor IC Chip

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 コイル、コンデンサ及び抵抗体の少なく
とも一つの素子を内部に有する積層体素子の主面に電子
回路を有する積層複合電子部品において、該積層体素子
の両主面を構成する最外層の内少なくとも電子回路を搭
載する側の最外層は該最外層に隣接する該積層体素子の
素地の線膨脹係数より小さく、該電子回路に接続される
チップ部品の線膨脹係数より大きい線膨脹係数を有する
熱応力緩和層である積層複合電子部品。
1. A laminated composite electronic component having an electronic circuit on the main surface of a laminated body element having at least one element of a coil, a capacitor and a resistor therein, and outermost layers constituting both principal surfaces of the laminated body element. At least the outermost layer on the side on which the electronic circuit is mounted is smaller than the linear expansion coefficient of the base material of the laminate element adjacent to the outermost layer, and is larger than the linear expansion coefficient of the chip component connected to the electronic circuit. A laminated composite electronic component, which is a thermal stress relaxation layer having:
【請求項2】 積層体素子の両主面を構成する両方の最
外層が当該それぞれの最外層に隣接する該積層体素子の
素地の線膨脹係数より小さく、該電子回路に接続される
チップ部品の線膨脹係数より大きい線膨脹係数を有する
熱応力緩和層である請求項1記載の積層複合電子部品。
2. A chip part connected to the electronic circuit, wherein both outermost layers forming both main surfaces of the laminated element are smaller than a linear expansion coefficient of a base material of the laminated element adjacent to the respective outermost layers. The laminated composite electronic component according to claim 1, which is a thermal stress relaxation layer having a linear expansion coefficient larger than the linear expansion coefficient of.
【請求項3】 熱応力緩和層の線膨脹係数が2〜7×1
-6/℃である請求項1又は2記載の積層複合電子部
品。
3. The coefficient of linear expansion of the thermal stress relaxation layer is 2 to 7 × 1.
The laminated composite electronic component according to claim 1 or 2, which has a temperature of 0 -6 / ° C.
【請求項4】 熱応力緩和層と積層体素子の素地との間
に両者の各成分が拡散した拡散層を有する請求項1、2
又は3記載の積層複合電子部品。
4. A diffusion layer in which the respective components of both are diffused between the thermal stress relaxation layer and the substrate of the laminated body element.
Alternatively, the laminated composite electronic component described in 3 above.
JP26840593A 1993-09-30 1993-09-30 Multilayer composite electronic components Expired - Fee Related JP3250166B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26840593A JP3250166B2 (en) 1993-09-30 1993-09-30 Multilayer composite electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26840593A JP3250166B2 (en) 1993-09-30 1993-09-30 Multilayer composite electronic components

Publications (2)

Publication Number Publication Date
JPH07106717A true JPH07106717A (en) 1995-04-21
JP3250166B2 JP3250166B2 (en) 2002-01-28

Family

ID=17458024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26840593A Expired - Fee Related JP3250166B2 (en) 1993-09-30 1993-09-30 Multilayer composite electronic components

Country Status (1)

Country Link
JP (1) JP3250166B2 (en)

Also Published As

Publication number Publication date
JP3250166B2 (en) 2002-01-28

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