JPH07114340B2 - Piezoelectric thin film resonator - Google Patents
Piezoelectric thin film resonatorInfo
- Publication number
- JPH07114340B2 JPH07114340B2 JP825687A JP825687A JPH07114340B2 JP H07114340 B2 JPH07114340 B2 JP H07114340B2 JP 825687 A JP825687 A JP 825687A JP 825687 A JP825687 A JP 825687A JP H07114340 B2 JPH07114340 B2 JP H07114340B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- void layer
- piezoelectric thin
- electrode
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は、高周波発振器等に用いられる圧電薄膜共振
子に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a piezoelectric thin film resonator used in a high frequency oscillator or the like.
（従来の技術） 従来、高周波発振器の発振源等に用いる共振子として第
４図に示すような圧電薄膜共振子が考案されている。こ
の共振子は、基板１上に形成され上へ順に下部保護膜
２、下部電極６、圧電体５、上部電極７、上部保護膜３
により構成されている。そして、圧電体５が上下に振動
することにより上部電極７と下部電極６との間にその振
動周波数による電気信号が得られる。圧電体５が上下に
振動する際上部保護膜３、下部保護膜２、上部電極７、
下部電極６も同様に振動するが、下方向へ振動した時に
下部保護膜２が基板１に接触しないように、下部保護膜
２と基板１との間には空隙層８が設けられている。な
お、圧電体５が振動するのはこの空隙層８の上部におい
てであり、上記振動周波数は空隙層８上部の圧電体５、
上部保護膜３、下部保護膜２、上部電極７、下部電極６
の総和の厚みによりきまる。(Prior Art) Conventionally, a piezoelectric thin film resonator as shown in FIG. 4 has been devised as a resonator used as an oscillation source of a high frequency oscillator. This resonator is formed on the substrate 1 and is arranged in the order of the lower protective film 2, the lower electrode 6, the piezoelectric body 5, the upper electrode 7, and the upper protective film 3 in this order.
It is composed by. Then, the piezoelectric body 5 vibrates up and down, so that an electric signal based on the vibration frequency is obtained between the upper electrode 7 and the lower electrode 6. When the piezoelectric body 5 vibrates vertically, the upper protective film 3, the lower protective film 2, the upper electrode 7,
The lower electrode 6 also vibrates similarly, but a void layer 8 is provided between the lower protective film 2 and the substrate 1 so that the lower protective film 2 does not contact the substrate 1 when vibrating downward. It is to be noted that the piezoelectric body 5 vibrates only in the upper part of the void layer 8, and the vibration frequency is the piezoelectric body 5 above the void layer 8.
Upper protective film 3, lower protective film 2, upper electrode 7, lower electrode 6
It depends on the total thickness of.
このように構成された圧電薄膜共振子は任意の基板１の
上に形成できるため、集積回路が形成された半導体基板
上にも形成することができるという特徴をもっている。
このことにより、たとえば発振回路とこの圧電薄膜共振
子を同一の半導体基板上に形成して、発振器の超小形化
を図ることが可能である。Since the piezoelectric thin film resonator configured as described above can be formed on an arbitrary substrate 1, it can be formed on a semiconductor substrate on which an integrated circuit is formed.
Thus, for example, the oscillator circuit and the piezoelectric thin film resonator can be formed on the same semiconductor substrate, and the oscillator can be miniaturized.
しかし、このような圧電薄膜共振子は上記のようにその
厚みにより振動周波数がきまるため上部に異物が付着す
ると振動周波数が変化してしまう。そのため、なんらか
のケースに密封しなければならない。ところが、現在集
積回路に多用されているモールドはこのような圧電薄膜
共振子には使用できない。なぜなら、モールド材が圧電
薄膜共振子上部に充てんされると、共振子が振動できな
くなり、所定の電気的特性が得られなくなるからであ
る。However, since the vibration frequency of such a piezoelectric thin film resonator varies depending on the thickness thereof as described above, the vibration frequency changes when a foreign substance adheres to the upper portion. Therefore, it must be sealed in some case. However, the molds currently widely used for integrated circuits cannot be used for such piezoelectric thin film resonators. This is because if the molding material is filled in the upper part of the piezoelectric thin film resonator, the resonator cannot vibrate and the predetermined electrical characteristics cannot be obtained.
（発明が解決しようとする問題点） 上記のように従来の圧電薄膜共振子は上部に異物が付着
するとその振動周波数が変化してしまうことと、モール
ドできないという問題点があった。(Problems to be Solved by the Invention) As described above, the conventional piezoelectric thin film resonator has a problem that the vibration frequency thereof changes when foreign matter adheres to the upper part and that the molding cannot be performed.
この発明の目的は上記の問題点を解決し、上部に異物が
付着しても振動周波数が変化せず、さらにはモールドし
たとしても電気的特性が変化せず所定の性能が得られる
圧電薄膜共振子を提供しようとするものである。The object of the present invention is to solve the above-mentioned problems, and the vibration frequency does not change even if a foreign substance adheres to the upper part, and even if it is molded, the electrical characteristics do not change and a predetermined performance is obtained. It is about trying to provide a child.
（問題点を解決するための手段） この発明は、圧電薄膜共振子の振動部上部すなわち基板
と反対側の面に上部空隙層を設け、さらにその上に上部
空隙層保護膜を設けたものである。(Means for Solving the Problems) The present invention is one in which an upper void layer is provided on the vibrating portion upper part of the piezoelectric thin film resonator, that is, on the surface opposite to the substrate, and an upper void layer protective film is further provided thereon. is there.
（作用） この発明によれば、振動部すなわち圧電体，上部電極，
下部電極，上部保護膜，下部保護膜は新たに設けられた
上部空隙層と下部空隙層との間で振動し、その振動周波
数はこれら振動部の総和の厚みによってきまる。上部空
隙層保護膜には上部空隙層によって圧電体の振動はつた
わらず上記振動周波数には影響をあたえない。よって、
最上部にある上部空隙層保護膜に異物が付着したとして
も、圧電薄膜共振子としての電気的特性は変化しない。(Operation) According to the present invention, the vibrating portion, that is, the piezoelectric body, the upper electrode,
The lower electrode, the upper protective film, and the lower protective film vibrate between the newly provided upper void layer and lower void layer, and the vibration frequency is determined by the total thickness of these vibrating portions. The upper void layer does not affect the vibration frequency of the piezoelectric body due to the upper void layer, and does not affect the vibration frequency. Therefore,
Even if foreign matter adheres to the upper void layer protective film at the top, the electrical characteristics of the piezoelectric thin film resonator do not change.
（実施例） 以下、図面を参照してこの発明の実施例について説明す
る。Embodiments Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例に係る圧電薄膜共振子の構
成を示すものである。この共振子は、基板１上に形成さ
れ、上へ順に、下部保護膜2,下部電極6,圧電体5,上部電
極7,上部保護膜3,上部空隙層保護膜４により構成されて
いる。そして、基板１と下部保護膜２との間には下部空
隙層８が上部保護膜３と上部空隙層保護膜４との間には
上部空隙層９がそれぞれ設けられている。この空隙層８
は下部保護膜２が下へ振動した時に基板１に接触しない
厚さに、空隙層９は上部保護膜３が上へ振動した時に上
部空隙層保護膜４に接触しない厚さにそれぞれ選定され
ている。FIG. 1 shows the structure of a piezoelectric thin film resonator according to an embodiment of the present invention. This resonator is formed on a substrate 1 and is composed of a lower protective film 2, a lower electrode 6, a piezoelectric body 5, an upper electrode 7, an upper protective film 3, and an upper void layer protective film 4 in this order in the upward direction. A lower void layer 8 is provided between the substrate 1 and the lower protective film 2, and an upper void layer 9 is provided between the upper protective film 3 and the upper void layer protective film 4. This void layer 8
Is selected to have a thickness that does not contact the substrate 1 when the lower protective film 2 vibrates downward, and the void layer 9 has a thickness that does not contact the upper void layer protective film 4 when the upper protective film 3 vibrates upward. There is.
この圧電薄膜共振子は圧電体５の上部空隙層９と下部空
隙層８との間の部分が上下に振動することにより、上部
電極７と下部電極６との間にその振動周波数による電気
信号が得られるが、圧電体５が振動する際、上部電極7,
下部電極6,上部保護膜3,下部保護膜２も上部空隙層９と
下部空隙層８との間で振動する。このため上記振動周波
数はこれら振動部分すなわち上部保護膜３、上部電極7,
圧電体5,下部電極6,下部保護膜２の、上部空隙層９と下
部空隙層８との間の部分の総和の厚みによりきまる。上
部空隙層保護膜４は上部空隙層９があるため圧電体５の
振動がつたわらず振動しないため、上記振動周波数には
影響しない。In this piezoelectric thin film resonator, a portion between the upper void layer 9 and the lower void layer 8 of the piezoelectric body 5 vertically vibrates, so that an electric signal due to the vibration frequency is generated between the upper electrode 7 and the lower electrode 6. Although obtained, when the piezoelectric body 5 vibrates, the upper electrode 7,
The lower electrode 6, the upper protective film 3, and the lower protective film 2 also vibrate between the upper void layer 9 and the lower void layer 8. For this reason, the above-mentioned vibration frequencies are those vibration parts, that is, the upper protective film 3, the upper electrode 7,
It depends on the total thickness of the portions of the piezoelectric body 5, the lower electrode 6, and the lower protective film 2 between the upper void layer 9 and the lower void layer 8. Since the upper void layer protective film 4 has the upper void layer 9, the vibration of the piezoelectric body 5 does not continue and does not vibrate, and thus does not affect the vibration frequency.
次に、第１図の構成の圧電薄膜共振子を得るための工程
を第２図に示す。まず、第４図に示した従来の圧電薄膜
共振子を形成し、その上部に第２図（ｉ）に示すように
酸化亜鉛等により上部空隙層となる埋込み層10を形成す
る。さらに、その上に第２図（ii）に示すように２酸化
シリコン等による上部空隙層保護膜４を形成する。次
に、第２図（iii）に示すように上部空隙層保護膜４を
埋込み層10まで１つまたは複数の穴をエッチング等によ
りあける。この際基板１上の上部空隙層保護膜４の不要
部分を同時に取除く。そして第２図（iv）に示すように
この穴からエッチングにより埋込み層10を取除き、上部
空隙層９を形成する。以上のような工程により第１図に
示した圧電薄膜共振子が得られるわけである。このよう
な工程によれば、全ての作業が基板１の上面からおこな
えるという特徴がある。Next, FIG. 2 shows a process for obtaining the piezoelectric thin film resonator having the structure shown in FIG. First, the conventional piezoelectric thin film resonator shown in FIG. 4 is formed, and a buried layer 10 serving as an upper void layer is formed on the upper portion thereof by zinc oxide or the like as shown in FIG. 2 (i). Further, an upper void layer protective film 4 made of silicon dioxide or the like is formed thereon as shown in FIG. 2 (ii). Next, as shown in FIG. 2 (iii), one or more holes are formed in the upper void layer protective film 4 up to the buried layer 10 by etching or the like. At this time, unnecessary portions of the upper void layer protective film 4 on the substrate 1 are simultaneously removed. Then, as shown in FIG. 2 (iv), the buried layer 10 is removed from this hole by etching to form the upper void layer 9. Through the above steps, the piezoelectric thin film resonator shown in FIG. 1 can be obtained. According to such a process, all the operations can be performed from the upper surface of the substrate 1.
このようにして得られた図１に示す圧電薄膜共振子は、
上部空隙層９と下部空隙層８の間の振動部が上部空隙層
保護膜４と基板１により保護されるため、異物が付着し
ても振動周波数は変化しない。なお、上部空隙層保護膜
４には上部空隙層９を形成するための穴があいている
が、モールド材はエッチング液に比べて十分粘性が高い
ため上部空隙層９に進入することはない。よってこの圧
電薄膜共振子をモールドしても電気的特性が変化するこ
とはない。The piezoelectric thin film resonator shown in FIG. 1 thus obtained is
Since the vibrating portion between the upper void layer 9 and the lower void layer 8 is protected by the upper void layer protective film 4 and the substrate 1, the vibration frequency does not change even if foreign matter is attached. Although the upper void layer protective film 4 has holes for forming the upper void layer 9, it does not enter the upper void layer 9 because the mold material has a sufficiently high viscosity as compared with the etching liquid. Therefore, even if this piezoelectric thin film resonator is molded, the electrical characteristics do not change.
この発明は上記の実施例、工程に限定されるものではな
く、種々に変形して実施できる。The present invention is not limited to the above-described embodiments and steps, and can be variously modified and carried out.
たとえば、第３図に示す圧電薄膜共振子は、基板１を下
部から堀ることにより下部空隙層８を形成したものであ
る。この場合も、上部空隙層９は第２図に示した工程で
形成できる。この他、下部空隙層８は基板に溝を堀った
ものを使用することも可能である。For example, the piezoelectric thin film resonator shown in FIG. 3 has the lower void layer 8 formed by digging the substrate 1 from below. Also in this case, the upper void layer 9 can be formed by the process shown in FIG. In addition, the lower void layer 8 may be formed by forming a groove on the substrate.
また、第２図に示した工程では、従来と同様の圧電薄膜
共振子を形成した後、上部空隙層を形成したが、たとえ
ば、上部空隙層と下部空隙層とを同時に形成することも
可能である。その他、種々の工程により、この発明によ
る圧電薄膜共振子を得ることができる。Further, in the process shown in FIG. 2, the upper thin film resonator is formed and then the upper void layer is formed, but it is also possible to form the upper void layer and the lower void layer at the same time, for example. is there. In addition, the piezoelectric thin film resonator according to the present invention can be obtained by various processes.
さらに、上部空隙層保護膜４、埋込み層10を形成する材
料についても、上記の２酸化シリコン、酸化亜鉛に限定
されるものではなく種々の材料が使用できる。Further, the material for forming the upper void layer protective film 4 and the burying layer 10 is not limited to the above-mentioned silicon dioxide and zinc oxide, and various materials can be used.
また、必要に応じて上部保護膜３と下部保護膜２は省略
することが可能である。Further, the upper protective film 3 and the lower protective film 2 can be omitted if necessary.
そして、この発明による圧電薄膜共振子をモールドする
場合またはケースに密封する場合、エージング特性を改
善するために、上部空隙層及び下部空隙層を一度真空状
態し、その後にヘリウムやアルゴン．ガス等の不活性ガ
スを充てんする不活性ガス等による置換を行うことが可
能である。ガス充てん後、モールドまたはケースに密封
するまでの間上部空隙層保護膜の穴から上部空隙層内の
ガスが急激にもれることはないが、上記の穴にフタをす
る等ガスをもれにくくする処置を講じてももちろんかま
わない。ガスを充てんしない場合でも上記のフタをする
ことにより低粘性のモールド材が上部空隙層に進入する
のを防止することができる。When the piezoelectric thin film resonator according to the present invention is molded or sealed in a case, in order to improve the aging characteristics, the upper void layer and the lower void layer are vacuumed once, and then helium or argon. It is possible to perform replacement with an inert gas or the like filled with an inert gas such as gas. The gas in the upper void layer does not suddenly leak from the hole in the upper void layer protective film until it is sealed in the mold or case after filling with gas, but it is difficult to leak the gas by covering the hole with the above hole. Of course, it does not matter if you take the necessary measures. Even when the gas is not filled, by using the lid, it is possible to prevent the low-viscosity molding material from entering the upper void layer.
さらにまた、このような圧電薄膜共振子は、半導体集積
回路との一体化構造が考えられている。すなわち同一半
導体基板上に、この共振子と半導体集積回路とを一体化
して形成し、例えばワンチップの発振器等を構成すれ
ば、回路の小形化，簡易化が図られる。このように一体
化構造をとる場合、半導体集積回路の接続点とこの共振
子の上下電極とをアルミニウム等の金属膜による配線パ
ターンで接続することが必要になる。しかしながらこの
場合、通常圧電薄膜は２〜10μｍ程度の厚さを有するた
めこの圧電薄膜の膜厚に相当する段差により共振子の上
部電極と半導体集積回路の接続点とを接続する際配線用
金属膜がリフトオフ法や金属マスク法では十分に形成で
きず、断線などを生じやすいという問題がある（なお、
エッチング法は圧電薄膜（ZnO）がエッチング液に対し
て弱いので使用できない。）。そこでこのような問題に
対しては拡散用の金属により接続すべき電極の対向する
位置の圧電薄膜に導電性をもたせて互いに電気的に接続
するようにすることが望ましい。Furthermore, such a piezoelectric thin film resonator is considered to have an integrated structure with a semiconductor integrated circuit. That is, if the resonator and the semiconductor integrated circuit are integrally formed on the same semiconductor substrate to form, for example, a one-chip oscillator or the like, the circuit can be downsized and simplified. When such an integrated structure is adopted, it is necessary to connect the connection point of the semiconductor integrated circuit and the upper and lower electrodes of the resonator with a wiring pattern made of a metal film such as aluminum. However, in this case, since the piezoelectric thin film usually has a thickness of about 2 to 10 μm, a metal film for wiring is used when connecting the upper electrode of the resonator and the connection point of the semiconductor integrated circuit by a step corresponding to the film thickness of the piezoelectric thin film. However, there is a problem that the lift-off method or the metal mask method cannot sufficiently form it, and easily cause wire breakage (note that
The etching method cannot be used because the piezoelectric thin film (ZnO) is weak against the etching solution. ). Therefore, in order to solve such a problem, it is desirable that the piezoelectric thin films at the opposite positions of the electrodes to be connected are made electrically conductive by a diffusion metal so as to be electrically connected to each other.
第５図はこのような圧電薄膜共振子の配線構造の実施例
を示す斜視図であり第６図は第５図のＡ−Ａ′における
断面図である。あらかじめ半導体集積回路が形成された
基板41上にCVD法又はスパッタ法でSiO2膜42,43を付着さ
せ、その後裏面の所定の部分をPED液（パイロカテコー
ル，エチレンジアミン，水の混合液）等の異方性エッチ
ング液で除去し凹部44を形成して図に示すようなSi41,S
iO242からなる基底膜を形成する。この基底膜上にAu又
はAlを主成分とする金属膜により第１の電極45を形成す
る。次に半導体集積回路側の電気接続用の窓54をフォト
リングライ技術を用いて形成し配線電極51を露出させ
る。その上にスパッタ法又は蒸着法によってAl等の金属
を付着させ配線電極51を含むSiO2膜上にフォトエッチン
グ法により所定の大きさの引き出し電極46,47を形成す
る。引き出し電極47は第１の電極45と配線電極51を電気
的接続し、引き出し電極46は第２の電極49と電気的接続
するためのものである。更にその上にRFマグネトロンス
パッタ法等によりZnO圧電膜48を付着させ酢酸と水から
なるエッチング液を用いて所定の大きさに形成する。次
にZnO膜をはさんで引き出し電極46の一部と対向する位
置にTi等の拡散金属を金属マスク法又はリフトオフ法に
よって所定の大きさで形成し、更にその上にAu等の金属
膜により第２の電極49を第１の電極45と直交する方向に
所定の大きさで形成する。この場合圧電薄膜48は基板41
の凹部44に対応した位置に形成され、第１の電極45と第
２の電極49はZnO圧電薄膜48をはさんで少なくとも一部
が互いに対向して配置されている。さらに第２の電極の
他端は拡散金属ZnO圧電薄膜をはさんで引き出し電極46
と対向して配置されている。最後にオーブン等により25
0℃２時間30分以上の熱処理を施しZnO圧電薄膜48中にTi
を拡散させ、この拡散領域50の圧電薄膜に導電性をもた
せ第２の電極49と引き出し電極46を電気的接続させる。FIG. 5 is a perspective view showing an embodiment of the wiring structure of such a piezoelectric thin film resonator, and FIG. 6 is a sectional view taken along the line AA 'in FIG. The SiO 2 films 42 and 43 are adhered by the CVD method or the sputtering method on the substrate 41 on which the semiconductor integrated circuit is formed in advance, and then a predetermined portion of the back surface is covered with PED liquid (a mixture of pyrocatechol, ethylenediamine, water) or the like. Si41, S as shown in the figure by forming a recess 44 by removing with an anisotropic etchant
Form a basement membrane consisting of iO 2 42. A first electrode 45 is formed on the base film by using a metal film containing Au or Al as a main component. Next, a window 54 for electrical connection on the semiconductor integrated circuit side is formed using the photo ring technique to expose the wiring electrode 51. A metal such as Al is deposited thereon by a sputtering method or a vapor deposition method, and lead electrodes 46 and 47 of a predetermined size are formed on the SiO 2 film including the wiring electrode 51 by a photoetching method. The extraction electrode 47 is for electrically connecting the first electrode 45 and the wiring electrode 51, and the extraction electrode 46 is for electrically connecting to the second electrode 49. Further, a ZnO piezoelectric film 48 is attached thereon by an RF magnetron sputtering method or the like, and is formed to a predetermined size by using an etching solution composed of acetic acid and water. Next, a diffusion metal such as Ti is formed in a predetermined size by a metal mask method or a lift-off method at a position facing a part of the extraction electrode 46 across the ZnO film, and a metal film such as Au is further formed thereon. The second electrode 49 is formed in a predetermined size in a direction orthogonal to the first electrode 45. In this case, the piezoelectric thin film 48 is the substrate 41.
The first electrode 45 and the second electrode 49 are formed at positions corresponding to the recesses 44, and are at least partially opposed to each other with the ZnO piezoelectric thin film 48 interposed therebetween. Further, the other end of the second electrode is sandwiched by a diffusion metal ZnO piezoelectric thin film and is an extraction electrode 46.
It is arranged opposite to. Finally by the oven etc. 25
After heat treatment at 0 ℃ for 2 hours and 30 minutes or more, Ti in ZnO piezoelectric thin film 48
Is diffused, and the piezoelectric thin film in the diffusion region 50 is made conductive so that the second electrode 49 and the extraction electrode 46 are electrically connected.
更にこの上に少なくとも圧電薄膜を全て含む大きさでSi
O2膜を付着させてもよい。このSiO2膜は大気の湿気など
に弱いZnO膜の保護膜として働くだけでなく周波数温度
係数の補償用として働く。またこのような構成の場合に
はTiの拡散をSiO2スパッタ工程と兼ねることもできる。
尚圧電薄膜はZnOに限定されるものではなくAlN,Ta2O5,C
ds等の圧電薄膜であれば何を用いてもよく更に圧電膜の
下面もしくは上下面に電極を介在して配置される膜の材
料はSiO2に限られるものではなく化学的に安定な誘電膜
やSiO2にリンを数％程度ドープしたPSG膜、更にボロン
とリンをドープしたBPSGやホウケイ酸等のガラス類でも
よくそれが単層でなく異種材料の複合層であってもよ
い。更にZnO圧電薄膜中に拡散される材料はTiに限られ
るものではなく拡散定数の大きい金属例えばCr,In,Ni,S
n,Al,Mg,Li等であれば何を用いてもよい。In addition, the size of Si including at least all the piezoelectric thin films
An O 2 film may be attached. This SiO 2 film functions not only as a protective film for the ZnO film, which is weak against atmospheric humidity, but also as a compensation for the frequency temperature coefficient. Further, in the case of such a configuration, the diffusion of Ti can be combined with the SiO 2 sputtering step.
The piezoelectric thin film is not limited to ZnO, but AlN, Ta 2 O 5 , C
Any piezoelectric thin film such as ds may be used. Further, the material of the film arranged with electrodes on the lower surface or upper and lower surfaces of the piezoelectric film is not limited to SiO 2 , but a chemically stable dielectric film. Alternatively, a PSG film in which phosphorus is doped to SiO 2 by about several percent, or a glass such as BPSG or borosilicate in which boron and phosphorus are doped may be used, and it may be a composite layer of different materials instead of a single layer. Furthermore, the material diffused in the ZnO piezoelectric thin film is not limited to Ti, but metals with large diffusion constants such as Cr, In, Ni, S
Any material such as n, Al, Mg, Li may be used.
さらに他の実施例として第７図に示すように、基板凹部
を設けるかわりに空隙層52を設けることによって共振部
分を基板より離した形の圧電薄膜共振子と半導体集積回
路を組合せた構造とすることもできる。この空隙層52は
あらかじめ基板上にZnO膜等の化学的に容易に溶解でき
る数百Å〜数μｍの薄膜を所定の大きさに付着させその
上にSiO2等の膜42をスパッタリング法等で付着させ、こ
の上に第１の電極45、配線電極51の露出及び圧電薄膜4
8、第２の電極49さらに共振子側の電極と集積回路側の
配線電極との電気的接続は第６図の実施例と同様の手順
で形成し最終的にZnO圧電薄膜、引き出し電極をレジス
トで保護しSiO2膜の一部をエッチングしZnO膜がSiO2膜
で被覆された部分と被覆されない部分を形成しこれらを
HCl等の溶液につけZnO膜を除去することによって形成出
来る。なお最上層にSiO2膜を付着させてもよい。このSi
O2膜は周波数温度係数の補償用と空隙層形成の際のZnO
圧電薄膜の保護としても働く。As yet another embodiment, as shown in FIG. 7, a cavity thin film 52 is provided instead of the recessed portion of the substrate to form a structure in which a piezoelectric thin film resonator having a resonance portion separated from the substrate and a semiconductor integrated circuit are combined. You can also As the void layer 52, a thin film of several hundred Å to several μm such as a ZnO film which can be chemically and easily dissolved is attached in advance to a predetermined size on a substrate, and a film 42 such as SiO 2 is formed thereon by a sputtering method or the like. The first electrode 45, the wiring electrode 51 are exposed, and the piezoelectric thin film 4 is attached thereon.
8. Second electrode 49 Further, the electrical connection between the electrode on the resonator side and the wiring electrode on the integrated circuit side is formed by the same procedure as in the embodiment of FIG. 6, and finally the ZnO piezoelectric thin film and the lead electrode are resisted. Protected with a part of the SiO 2 film is etched to form a part of the ZnO film covered with the SiO 2 film and a part not covered with it.
It can be formed by dipping the ZnO film in a solution such as HCl. A SiO 2 film may be attached to the uppermost layer. This Si
The O 2 film is used for compensation of the frequency temperature coefficient and ZnO when forming the void layer.
It also works as a protection for the piezoelectric thin film.
このように共振子の第２の電極と引き出し電極をZnO圧
電薄膜をはさんで形成しこれらをZnO圧電薄膜の一部に
導電性をもたせて電気的接続した配線構造とすると，容
易、かつ確実な配線が可能となる。In this way, if the second electrode of the resonator and the extraction electrode are formed by sandwiching the ZnO piezoelectric thin film, and these are electrically connected by making part of the ZnO piezoelectric thin film electrically conductive, it is easy and reliable. Wiring is possible.
この発明によれば、異物が付着したとしても電気的特性
が変化しないきわめて信頼性の高い圧電薄膜共振子を得
ることができる。According to the present invention, it is possible to obtain a highly reliable piezoelectric thin film resonator in which the electrical characteristics do not change even if foreign matter adheres.
また、モールドしても電気的特性が変化しないため、こ
の発明による圧電薄膜共振子と集積回路とを同一の半導
体基板上に形成してモールドすることができる。これに
より発振回路等の超小形化が図れ、しかも従来の集積回
路と同じ形体の電気部品として提供することができる。Further, since the electrical characteristics do not change even when molded, the piezoelectric thin film resonator according to the present invention and the integrated circuit can be formed and molded on the same semiconductor substrate. This makes it possible to miniaturize the oscillator circuit and the like, and to provide it as an electric component having the same shape as the conventional integrated circuit.
第１図はこの発明の一実施例に係る圧電薄膜共振子の断
面図、第２図は第１図の圧電薄膜共振子を得る工程を説
明するための各工程における断面図、第３図はこの発明
の他の実施例に係る圧電薄膜共振子の断面図、第４図は
従来の圧電薄膜共振子の断面図、第５図乃至第７図は配
線パターンの具体例を示す図である。 １……基板、２……下部保護膜、３……上部保護膜、４
……上部空隙層保護膜、５……圧電体、６……下部電
極、７……上部電極、８……下部空隙層、９……上部空
隙層、10……埋込み層。1 is a cross-sectional view of a piezoelectric thin film resonator according to an embodiment of the present invention, FIG. 2 is a cross-sectional view in each step for explaining a step of obtaining the piezoelectric thin film resonator of FIG. 1, and FIG. FIG. 4 is a sectional view of a piezoelectric thin film resonator according to another embodiment of the present invention, FIG. 4 is a sectional view of a conventional piezoelectric thin film resonator, and FIGS. 5 to 7 are views showing specific examples of wiring patterns. 1 ... Substrate, 2 ... Lower protective film, 3 ... Upper protective film, 4
...... Upper void layer protective film, 5 ... Piezoelectric body, 6 ... Lower electrode, 7 ... Upper electrode, 8 ... Lower void layer, 9 ... Upper void layer, 10 ... Embedded layer.
Claims (3)
れ、複数の電極が接続された圧電体の、基板と反対側の
面に上部空隙層を設け、この上部空隙層を保護するため
の上部空隙層保護膜を設けたことを特徴とする圧電薄膜
共振子。1. An upper void layer is provided on a surface of a piezoelectric body, which is formed on an arbitrary substrate via a lower void layer and to which a plurality of electrodes are connected, on the side opposite to the substrate to protect the upper void layer. A piezoelectric thin film resonator, characterized in that an upper void layer protective film is provided for it.
圧電体との間、または圧電体と上部空隙層保護膜との
間、またはその両方に設けたことを特徴とする特許請求
の範囲第１項記載の圧電薄膜共振子。2. A protective film for protecting the piezoelectric body is provided between the substrate and the piezoelectric body, between the piezoelectric body and the upper void layer protective film, or both. 2. A piezoelectric thin film resonator according to claim 1.
用いたことを特徴とする特許請求の範囲第１項記載の圧
電薄膜共振子。3. The piezoelectric thin film resonator according to claim 1, wherein the lower void layer uses holes or grooves dug in the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP825687A JPH07114340B2 (en) | 1987-01-19 | 1987-01-19 | Piezoelectric thin film resonator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP825687A JPH07114340B2 (en) | 1987-01-19 | 1987-01-19 | Piezoelectric thin film resonator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63177605A JPS63177605A (en) | 1988-07-21 |
| JPH07114340B2 true JPH07114340B2 (en) | 1995-12-06 |
Family
ID=11688061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP825687A Expired - Lifetime JPH07114340B2 (en) | 1987-01-19 | 1987-01-19 | Piezoelectric thin film resonator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114340B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6496085B2 (en) * | 2001-01-02 | 2002-12-17 | Nokia Mobile Phones Ltd | Solidly mounted multi-resonator bulk acoustic wave filter with a patterned acoustic mirror |
| KR100470708B1 (en) | 2003-05-22 | 2005-03-10 | 삼성전자주식회사 | A manufacturing method of Film bulk acoustic resonator using interior stress of metalic film and a resonator thereof |
| ATE469463T1 (en) | 2003-05-26 | 2010-06-15 | Murata Manufacturing Co | PIEZOELECTRIC ELECTRONIC COMPONENT |
| US7561009B2 (en) * | 2005-11-30 | 2009-07-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonator (FBAR) devices with temperature compensation |
| DE102013102217B4 (en) | 2013-03-06 | 2015-11-12 | Epcos Ag | Microacoustic component and method of manufacture |
-
1987
- 1987-01-19 JP JP825687A patent/JPH07114340B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63177605A (en) | 1988-07-21 |
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