JPH07118488B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07118488B2 JPH07118488B2 JP25583191A JP25583191A JPH07118488B2 JP H07118488 B2 JPH07118488 B2 JP H07118488B2 JP 25583191 A JP25583191 A JP 25583191A JP 25583191 A JP25583191 A JP 25583191A JP H07118488 B2 JPH07118488 B2 JP H07118488B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating layer
- semiconductor device
- radial
- soldered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置用回路基板
に対する半導体チップあるいは端子部材の取り付けを改
良した半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which mounting of a semiconductor chip or a terminal member on a circuit board for a semiconductor device is improved.
【０００２】[0002]
【従来の技術】従来、半導体装置用回路基板としては、
金属基板１１上に絶縁層１２、電極１３を順次設け、こ
の電極１３の周囲に絶縁層１４を形成し、中央部の露出
した電極１３上に半導体チップあるいは端子部材（以
下、部材という）１５を半田付け１６した図３に断面図
として示す構造のものがある。このような回路基板にお
いて、電極１３上の絶縁層１４は図４に示すように、電
極１３の上面中央部に半田付け等によって取り付ける部
材１５の位置決めのために電極１３の周囲に用いられる
もので、電極１３上の部材１５取り付け位置をマスキン
グしたのち、該電極１３上にエポキシ樹脂のような絶縁
材を塗布して形成するか、電極１３上の全面に絶縁層を
形成したのち、部材１５の取り付け位置の絶縁層１４の
みをエッチング等にて除去して電極１３面を露出させ、
この露出した電極１３上面に部材１５が半田付けされて
いる。2. Description of the Related Art Conventionally, as a circuit board for a semiconductor device,
An insulating layer 12 and an electrode 13 are sequentially provided on a metal substrate 11, an insulating layer 14 is formed around the electrode 13, and a semiconductor chip or a terminal member (hereinafter referred to as a member) 15 is formed on the electrode 13 exposed at the center. There is a structure shown as a sectional view in FIG. In such a circuit board, as shown in FIG. 4, the insulating layer 14 on the electrode 13 is used around the electrode 13 for positioning the member 15 attached to the central portion of the upper surface of the electrode 13 by soldering or the like. After the mounting position of the member 15 on the electrode 13 is masked, an insulating material such as an epoxy resin is applied on the electrode 13 or an insulating layer is formed on the entire surface of the electrode 13 and then the member 15 is formed. Only the insulating layer 14 at the mounting position is removed by etching or the like to expose the surface of the electrode 13,
The member 15 is soldered to the exposed upper surface of the electrode 13.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記し
たような電極１３の上面に部材１５が半田付けされる構
成では、半田付け中に半田内に含有されているフラック
スがガスを発生し、半田付け後このガスが半田内に残存
したりすると、半田層に空洞が生じ、部材と電極との接
触抵抗および熱抵抗値が増加するという問題がある。ま
た、上記した従来の絶縁層１４による部材の位置決めに
おいては、電極１３上への部材の半田付け時に半田の表
面張力によって部材が傾いたりしてその取り付け位置が
所定の位置よりずれるという問題があった。However, in the structure in which the member 15 is soldered on the upper surface of the electrode 13 as described above, the flux contained in the solder generates gas during soldering, and the soldering is performed. If this gas later remains in the solder, cavities occur in the solder layer, increasing the contact resistance between the member and the electrode and the thermal resistance. Further, in the above-mentioned conventional positioning of the member by the insulating layer 14, there is a problem that the member is inclined due to the surface tension of the solder when the member is soldered on the electrode 13 and the mounting position is displaced from the predetermined position. It was
【０００４】[0004]
【課題を解決するための手段】この発明は、半導体装置
用回路基板の電極上面所定位置への半導体チップ等の取
り付け時における上記した従来の問題点を解消すべく検
討の結果、得られたものである。The present invention has been obtained as a result of a study for solving the above-mentioned conventional problems when a semiconductor chip or the like is attached to a predetermined position on the upper surface of an electrode of a circuit board for a semiconductor device. Is.
【０００５】即ち、この発明は金属基板上に絶縁層と電
極を有してなる半導体装置用回路基板の電極上面への半
導体チップあるいは端子部材の取り付けに際し、前記電
極の上面中央部に放射状の絶縁層と、さらに上面外周に
複数の凸部を有する絶縁層を設けた半導体装置を提供す
るものである。That is, according to the present invention, when a semiconductor chip or a terminal member is attached to the upper surface of an electrode of a semiconductor device circuit board having an insulating layer and an electrode on a metal substrate, a radial insulation is provided at the center of the upper surface of the electrode. Provided is a semiconductor device in which a layer and an insulating layer having a plurality of convex portions are further provided on the outer periphery of the upper surface.
【０００６】[0006]
【作用】この発明は、半導体装置用回路基板の電極の上
面中央部に放射状の絶縁層を設けることによって、部材
の電極上への半田付け時に発生するガスをこの放射状の
絶縁層を通して除去することができ、これにより電極と
部材を精度よく半田付けすることができる。また、さら
に電極の上面外周に複数の凸部を有する絶縁層を設ける
ことによって、部材の電極上への適正な位置決めを行う
ことができるのである。According to the present invention, by providing a radial insulating layer on the central portion of the upper surface of the electrode of the semiconductor device circuit board, the gas generated when soldering the member to the electrode is removed through the radial insulating layer. As a result, the electrode and the member can be soldered accurately. Further, by providing an insulating layer having a plurality of protrusions on the outer periphery of the upper surface of the electrode, it is possible to properly position the member on the electrode.
【０００７】この発明において、金属基板としてはAl、
CuあるいはFeなどの素材が用いられ、また絶縁層を形成
する絶縁材料としては、エポキシ樹脂、ポリイミド樹脂
などの耐熱性樹脂が用いられる。In the present invention, the metal substrate is Al,
A material such as Cu or Fe is used, and a heat-resistant resin such as an epoxy resin or a polyimide resin is used as an insulating material forming the insulating layer.
【０００８】[0008]
【実施例】以下、この発明をその一実施例を示す図によ
り詳細に説明する。図１は、この発明の半導体装置の断
面図であり、図２はその部分拡大平面図である。図にお
いて、１は上面に絶縁層２および電極３を設けた金属基
板である。４は電極３の上面中央部に放射状に設けた絶
縁層であり、５は電極３の上面外周に設けた内側に複数
の凸部６を有する絶縁層である。放射状の絶縁層４は電
極３の上面中央部を該放射状の形状となるようにマスク
して、その上からエポキシ樹脂等の絶縁材料を塗布し、
硬化させることにより得られる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing an embodiment thereof. 1 is a sectional view of a semiconductor device of the present invention, and FIG. 2 is a partially enlarged plan view thereof. In the figure, 1 is a metal substrate having an insulating layer 2 and an electrode 3 provided on the upper surface. Reference numeral 4 is an insulating layer radially provided on the central portion of the upper surface of the electrode 3, and 5 is an insulating layer provided on the outer periphery of the upper surface of the electrode 3 and having a plurality of convex portions 6 inside. The radial insulating layer 4 is formed by masking the central portion of the upper surface of the electrode 3 so as to have the radial shape, and applying an insulating material such as epoxy resin on the mask.
It is obtained by curing.
【０００９】次いで、複数の凸部６を有する絶縁層５
は、放射状絶縁層４を含む電極３上に該形状を得るよう
にマスクしてエポキシ樹脂を塗布することにより、電極
３の上面中央部は放射状の絶縁層を除いて電極３を露出
させ、同時に電極３の外周を囲むようにして得ることが
できる。その後、放射状絶縁層４を含めて露出した電極
３上に部材７を半田付け８することによりこの発明の半
導体装置が得られる。Next, the insulating layer 5 having a plurality of convex portions 6
Is masked so as to obtain the shape on the electrode 3 including the radial insulating layer 4 and epoxy resin is applied to expose the electrode 3 at the central portion of the upper surface of the electrode 3 except for the radial insulating layer. It can be obtained by surrounding the outer periphery of the electrode 3. After that, the semiconductor device of the present invention is obtained by soldering 8 the member 7 on the exposed electrode 3 including the radial insulating layer 4.
【００１０】なお、放射状の絶縁層４と複数の凸部６を
有する絶縁層５は、その厚みを異にし、前者はその上に
部材７を半田付けする際に、部材のズレをなくして精度
よく取り付けるためにも出来るだけ薄いことが好まし
い。また、後者、即ち複数の凸部６を有する絶縁層５
は、電極３の外周を囲むようにして電極３上への部材７
の適正な位置決めを行うものであるから、かなり厚く形
成することが必要である。The radial insulating layer 4 and the insulating layer 5 having a plurality of convex portions 6 have different thicknesses, and the former eliminates the displacement of the member 7 when soldering the member 7 on it and the accuracy is improved. It is preferable to be as thin as possible in order to attach well. The latter, that is, the insulating layer 5 having a plurality of convex portions 6
Is a member 7 on the electrode 3 so as to surround the outer periphery of the electrode 3.
Therefore, it is necessary to form a considerably thick film.
【００１１】[0011]
【発明の効果】以上説明したように、この発明は半導体
装置用回路基板の電極の上面中央部に放射状の絶縁層を
形成し、さらに複数の凸部を有する絶縁層を電極上面の
外周を囲むように形成したことにより、放射状絶縁層を
含む露出した電極上面に部材を半田付けにて取り付ける
際に、溶融した半田から発生するガスをこの放射状絶縁
層間を通して排除することが可能となり、電極と部材を
精度よく半田付けすることができるとともに、電極３上
面外周を囲むように形成した複数の凸部を有する絶縁層
によって、電極上への部材の適正な位置決めが行えるの
であり、従って品質の高い半導体装置を得ることができ
るのである。As described above, according to the present invention, a radial insulating layer is formed at the center of the upper surface of the electrode of the semiconductor device circuit board, and an insulating layer having a plurality of convex portions surrounds the outer periphery of the upper surface of the electrode. Thus, when the member is attached to the exposed electrode upper surface including the radial insulating layer by soldering, the gas generated from the melted solder can be eliminated through the radial insulating layer, and the electrode and the member can be removed. Can be accurately soldered, and an insulating layer having a plurality of convex portions formed so as to surround the outer periphery of the upper surface of the electrode 3 can properly position the member on the electrode, and therefore a high-quality semiconductor The device can be obtained.
【図１】この発明の半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.
【図２】この発明の一実施例を示す半導体装置の部分拡
大平面図である。FIG. 2 is a partially enlarged plan view of a semiconductor device showing an embodiment of the present invention.
【図３】従来の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.
【図４】従来の半導体装置における絶縁層の斜視図であ
る。FIG. 4 is a perspective view of an insulating layer in a conventional semiconductor device.
１ 金属基板 ２ 絶縁層 ３ 電極 ４ 放射状絶縁層 ５ 絶縁層 ６ 絶縁層の凸部 ７ 部材 ８ 半田 DESCRIPTION OF SYMBOLS 1 Metal substrate 2 Insulating layer 3 Electrode 4 Radial insulating layer 5 Insulating layer 6 Convex part of insulating layer 7 Member 8 Solder
Claims (1)
半導体装置用回路基板の電極上面への半導体チップある
いは端子部材の取り付けに際し、前記電極の上面中央部
に放射状の絶縁層と、さらに上面外周に複数の凸部を有
する絶縁層を設けたことを特徴とする半導体装置。1. When mounting a semiconductor chip or a terminal member on an upper surface of an electrode of a circuit board for a semiconductor device having an insulating layer and an electrode on a metal substrate, a radial insulating layer is provided at a central portion of the upper surface of the electrode, Further, the semiconductor device is characterized in that an insulating layer having a plurality of convex portions is provided on the outer periphery of the upper surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25583191A JPH07118488B2 (en) | 1991-09-06 | 1991-09-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25583191A JPH07118488B2 (en) | 1991-09-06 | 1991-09-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0567638A JPH0567638A (en) | 1993-03-19 |
| JPH07118488B2 true JPH07118488B2 (en) | 1995-12-18 |
Family
ID=17284214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25583191A Expired - Fee Related JPH07118488B2 (en) | 1991-09-06 | 1991-09-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118488B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1813254B1 (en) | 2000-12-28 | 2009-08-26 | Kao Corporation | Hair bleach composition and hair dye composition |
-
1991
- 1991-09-06 JP JP25583191A patent/JPH07118488B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0567638A (en) | 1993-03-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960604 |
|
| LAPS | Cancellation because of no payment of annual fees |