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JPH07120688B2 - Micro joint structure - Google Patents

Micro joint structure

Info

Publication number
JPH07120688B2
JPH07120688B2 JP62145068A JP14506887A JPH07120688B2 JP H07120688 B2 JPH07120688 B2 JP H07120688B2 JP 62145068 A JP62145068 A JP 62145068A JP 14506887 A JP14506887 A JP 14506887A JP H07120688 B2 JPH07120688 B2 JP H07120688B2
Authority
JP
Japan
Prior art keywords
wiring board
lsi chip
solder
connection terminal
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62145068A
Other languages
Japanese (ja)
Other versions
JPS63310127A (en
Inventor
良一 梶原
光雄 加藤
孝雄 舟本
矯 松坂
朝彦 志田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62145068A priority Critical patent/JPH07120688B2/en
Publication of JPS63310127A publication Critical patent/JPS63310127A/en
Publication of JPH07120688B2 publication Critical patent/JPH07120688B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体チツプや電子部品を配線基板の電気的
に接合する構造に係り、特に、大型LSIチツプと配線基
板の接合部が、水平方向の荷重に対して破断せず、ま
た、その疲労寿命を向上させる柔軟構造を有するマイク
ロ継手構造に関する。
Description: TECHNICAL FIELD The present invention relates to a structure for electrically bonding a semiconductor chip or an electronic component to a wiring board, and in particular, a large LSI chip and a wiring board are connected horizontally. The present invention relates to a micro joint structure having a flexible structure that does not break with respect to a directional load and improves its fatigue life.

〔従来の技術〕[Conventional technology]

最近の電子装置においては、装置の小型化や演算処理性
能の向上を図るため、LSIチツプの高集積化並びに大型
化が進んでおり、それに伴い配線基板上に実装されたLS
Iチツプの半田接合部の熱破断や熱疲労寿命が大きな問
題となつてきている。
In recent electronic devices, LSI chips are becoming highly integrated and large in size in order to miniaturize the device and improve the arithmetic processing performance. As a result, the LS mounted on the wiring board is becoming larger.
Thermal rupture and thermal fatigue life of solder joints of I-chips are becoming major problems.

一方、電子計算機などの超高性能機器では、従来の1チ
ツプパツケージ方式から複数の裸のあるいはチツプキヤ
リアに封止されたLSIチツプを1枚の多層配線基板上に
搭載するマルチチツプモジユール方式に変りつつあり、
また、LSIチツプから熱を取り去るためにチツプ直上に
水を循環させた冷却体を配置させ、冷却体とLSIチツプ
間を高熱伝達構造で結合する方式が考えられている。さ
らに、今後、LSIチツプの集積度が向上し、チツプ当り
の発熱量が40Wを超えるレベルに達するとLSIチツプの構
造素子をその動作範囲である85℃以下に冷却するため、
LSIチツプと冷却体の間を金属材料で結合し、熱伝導の
みによつて冷却する方式を採らざるを得なくなると想定
される。
On the other hand, in the case of ultra-high-performance devices such as electronic computers, the conventional 1-chip package system has been changed to the multi-chip module system in which multiple bare or chip-encapsulated LSI chips are mounted on a single multilayer wiring board. Going on,
Further, in order to remove heat from the LSI chip, a cooling body in which water is circulated is arranged directly above the chip, and a method of connecting the cooling body and the LSI chip with a high heat transfer structure is considered. Furthermore, in the future, when the integration degree of the LSI chip is improved and the heat generation amount per chip reaches a level exceeding 40 W, the structural elements of the LSI chip are cooled to the operating range of 85 ° C. or lower,
It is assumed that there will be no choice but to adopt a method in which the LSI chip and the cooling body are connected with a metal material and cooling is performed only by heat conduction.

第9図は、この想定におけるマルチチツプモジユールの
基本的な装置構成の一例を示す図である。多相配線基板
66は、その上のチツプキヤリア64と、半田からなるCCB
接合部65を介して接合され、さらにそのチツプキヤリア
64は、冷却用半田固着部63を介して、排水管61と給水管
62とを有する冷却体60と接合されている。冷却体60は金
属で構成され、多層配線基板66は有機材あるいはセラミ
ツク材で構成されているため、冷却体60と多層配線基板
66の熱膨張率を一致させることは実際上困難であるの
で、寸法が100mm角以上となるマルチチツプモジユール
などでは、半田付後の冷却に伴う熱収縮によつて冷却体
60と多層配線基板の間に数10〜数100μmもの歪が発生
する。このため、構造上強度的に最も弱いCCB接合部65
が破壊されたり、その熱疲労寿命が著しく低下し、装置
の信頼性が著しく悪くなる。上記の熱歪に起因する装置
の信頼性の低下に対しては、通常のCCB接合に改良を加
えた新しい接合構造が考案されているが、この改良案に
おいても上記の破壊や熱疲労の問題を十分に解決できて
いないのが実状である。次にその改良案を示す。
FIG. 9 is a diagram showing an example of a basic device configuration of a multi-chip module in this assumption. Multi-phase wiring board
66 is the chip carrier 64 on it and CCB made of solder
It is joined through the joint 65, and the chip carrier
The reference numeral 64 denotes a drain pipe 61 and a water supply pipe via the cooling solder fixing portion 63.
It is joined with the cooling body 60 having 62. Since the cooling body 60 is made of metal and the multilayer wiring board 66 is made of an organic material or a ceramic material, the cooling body 60 and the multilayer wiring board are
Since it is practically difficult to match the thermal expansion coefficient of 66 with each other, in a multi-chip module with a size of 100 mm square or more, the heat shrinkage due to cooling after soldering causes
A strain of several tens to several hundreds of μm occurs between the 60 and the multilayer wiring board. For this reason, the structurally weakest CCB joint 65
Is destroyed, the thermal fatigue life thereof is significantly reduced, and the reliability of the device is significantly deteriorated. In order to reduce the reliability of the device due to the above-mentioned thermal strain, a new joint structure that is an improvement of the normal CCB joint has been devised, but even in this improvement plan, the problem of the above-mentioned destruction and thermal fatigue The reality is that we have not been able to fully solve the problem. The improvement plan is shown below.

第10図は、LSIチツプの改良型半田構造を示す図であ
る。LSIチツプ67と多層配線基板71とは、LSIチツプ67に
設けられた数個の配線接合パツド68と多層配線基板71に
設けられた数個の電極接合パツド70とを各半田接合部69
で接合して、モジユールとして一体化されている。この
接合方法においては、まず、前記の配線接合パツド68及
び電極接合パツド70上に蒸着法あるいはメツキ法により
Pb及びSnが所定の組成をもつ半田の膜を形成し、次にこ
の膜を一度加熱溶融させて半円球の半田バンプに成形
し、最後に、LSIチツプ67の半田バンプと多層配線基板7
1の半田バンプが対面するように位置合せを行い、不活
性あるいは還元性雰囲気の炉中加熱によつて半田バンプ
を溶融し、半田が凝固する前にLSIチツプ67を機械的あ
るいは磁気的な力や遠心力等を用いて引き上げ、つづみ
形の半田接合部69を形成する。半田接合部を従来のたる
形からつづみ形に改良することにより、半田接合部にお
ける歪を分散できかつ応力集中を緩和できるため、この
つづみ形の半田接合部は疲労寿命でたる形のものより4
倍以上の向上が望めるとしている。
FIG. 10 is a diagram showing an improved solder structure of an LSI chip. The LSI chip 67 and the multi-layer wiring board 71 are composed of several wiring joining pads 68 provided on the LSI chip 67 and several electrode joining pads 70 provided on the multi-layer wiring board 71 at respective solder joints 69.
They are joined together and integrated as a module. In this bonding method, first, the wiring bonding pad 68 and the electrode bonding pad 70 are vapor-deposited or plated onto the wiring bonding pad 68 and the electrode bonding pad 70.
A solder film having a predetermined composition of Pb and Sn is formed, and then this film is once heated and melted to form a hemispherical solder bump, and finally, the solder bump of the LSI chip 67 and the multilayer wiring board 7
Position the solder bumps so that they face each other, and melt the solder bumps by heating in an inert or reducing atmosphere in the furnace, and then apply the mechanical or magnetic force to the LSI chip 67 before the solder solidifies. It is pulled up by using a centrifugal force or the like to form a staggered solder joint 69. By improving the solder joint from the conventional barrel shape to the slug type, strain in the solder joint can be dispersed and stress concentration can be relieved. Than 4
It is expected to be more than doubled.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

今後、LSIチツプが現状の2〜3倍又はそれ以上(20mm
角以上)に大型化した場合や、LSIチツプを高効率に冷
却するため冷却体にLSIチツプあるいはチツプキヤリア
を金属的に接合した場合には、LSIチツプあるいはチツ
プキヤリアと、半田接合部を介して接合された配線基板
との間に発生する熱歪によつて、その半田接合部が破断
するかあるいはその半田接合部の疲労寿命が大幅に低下
するという問題が生じる。この問題に対しては、現在ま
でに根本的な解決策が見出されていない。
In the future, the number of LSI chips will be 2 to 3 times the current level or more (20 mm
If the size of the LSI chip is larger than that of the LSI chip, or if the LSI chip or chip carrier is metallically joined to the cooling body to cool the LSI chip with high efficiency, the LSI chip or chip carrier is joined via the solder joint. Due to the thermal strain generated between the solder joint and the wiring board, the solder joint is broken or the fatigue life of the solder joint is significantly reduced. To date, no fundamental solution has been found to this problem.

前記の第10図に示した従来の改良案において、半田接合
部の形状をたる形からつづみ形に変えることによつてそ
の疲労寿命の向上を図つているが、半田の疲労寿命は、
次式 Nf=C・(γmax-5 ……(1) γmax δ ……(2) ここで、Nf:低サイクルの疲労寿命 C:定数 γmax:最大剪断歪 δ:配線基板とLSIチツプの相対変位 で示されるように、配線基板とLSIチツプの相対変位の
2乗に反比例して減少するために、例えば、相対変位が
従来の2倍になつた場合に、従来と同じ疲労寿命を得よ
うとすると、特開昭61−156745に開示されているデータ
から試算して半田高さを従来の100μmから400μmに増
さねばならない。しかし、実用的な半田バンプ径50〜20
0μmに対して半田高さを400μm以上に引伸ばすと、溶
融半田はくびれて切れ、実際上接合するのが難しくな
る。
In the conventional improvement plan shown in FIG. 10 described above, the fatigue life of the solder is improved by changing the shape of the solder joint portion from the barrel shape to the zigzag shape.
The following equation N f = C · (γ max ) -5 (1) γ max δ (2) where N f : low cycle fatigue life C: constant γ max : maximum shear strain δ: wiring As shown in the relative displacement between the board and the LSI chip, it decreases in inverse proportion to the square of the relative displacement between the wiring board and the LSI chip. For example, when the relative displacement becomes twice as large as the conventional one, In order to obtain the same fatigue life, it is necessary to increase the solder height from the conventional 100 μm to 400 μm by making a trial calculation from the data disclosed in JP-A-61-156745. However, a practical solder bump diameter of 50-20
When the solder height is extended to 400 μm or more with respect to 0 μm, the molten solder becomes constricted and broken, which makes it practically difficult to join.

従つて、半田高さの増加による半田接合部の疲労寿命の
改善方法は、相対変位が従来の2倍程度すなわち20μm
を限界としてそれ以下に適用され、それ以上の絶対変位
に対しては適用困難である。
Therefore, the method of improving the fatigue life of solder joints by increasing the solder height is that the relative displacement is about twice that of the conventional method, that is, 20 μm.
It is applied below that, and it is difficult to apply to absolute displacements beyond that.

本発明の目的は、半導体部品を配線基板上に電気的に接
続する接合部において、温度変化のために半導体部品と
配線基板との相対変位が数10〜数100μmに達した場合
でも、接合部が破断せず、また、その疲労寿命の向上を
図れるマイクロ継手構造を提供することである。
An object of the present invention is to provide a joint portion for electrically connecting a semiconductor component on a wiring board, even if the relative displacement between the semiconductor component and the wiring board reaches several tens to several hundreds μm due to temperature change. It is an object of the present invention to provide a micro joint structure that does not break and that can improve its fatigue life.

〔問題点を解決するための手段〕[Means for solving problems]

微小間隔を以て配置された被接合部材の相互に対向する
接続端子部を、この接続端子部とは異る材質の接合材料
によつて接合するマイクロ継手構造において、前記接続
端子間に渡した磁性を有する金属を含んだ金属細線と、
少なくともこの金属細線の各端と前記接続端子部のそれ
ぞれを接合したろう材と、から構成されていることを特
徴とするマイクロ継手構造によつて、上記問題は解決さ
れる。
In a micro joint structure in which connecting terminal portions of the members to be joined which are arranged with a minute interval are opposed to each other with a joining material made of a material different from that of the connecting terminal portion, the magnetic force passed between the connecting terminals is A thin metal wire containing a metal having
The above problem is solved by a micro-joint structure characterized by comprising at least each end of the metal thin wire and a brazing material joining each of the connection terminal portions.

〔作用〕[Action]

第1図と共に作用を説明する。 The operation will be described with reference to FIG.

被接合部材1および被接合部材1′は、被接合部材1に
設けられた接続端子部2と、被接合部材1′に設けられ
た接続端子部3と、相互に対向する接続端子部2,3の間
隙に渡した磁性を有する金属を含んだ金属細線6と、そ
の金属細線の各端をそれぞれ接続端子2,3に接合したろ
う材4,5と、からなるマイクロ継手構造によつて、結合
されている。
The member to be joined 1 and the member to be joined 1'include a connection terminal portion 2 provided on the member 1 to be joined, a connection terminal portion 3 provided on the member 1'to be joined, and connection terminal portions 2 facing each other, According to the micro joint structure composed of the thin metal wire 6 containing the magnetic metal passed through the gap of 3, and the brazing materials 4 and 5 in which each end of the thin metal wire is joined to the connection terminals 2 and 3, respectively, Are combined.

今、温度変化のために被接合部材1と被接合部材1′間
に相対変位δが生じたとすれば、磁性を有する金属を含
んだ金属細線6は第1図(a)に示す直線状から第1図
(b)に示す曲線上に変化する。この時、相対変位δは
磁性を有する金属を含んだ金属細線6の曲り変形によつ
て吸収されるために、金属細線およびろう材4,5の層に
生ずる剪断応力は著しく低い。
Now, assuming that a relative displacement δ occurs between the members 1 and 1 ′ to be joined due to a temperature change, the thin metal wire 6 containing a magnetic metal is changed from the linear shape shown in FIG. 1 (a). It changes on the curve shown in FIG. At this time, since the relative displacement δ is absorbed by the bending deformation of the metal thin wire 6 containing a magnetic metal, the shear stress generated in the metal thin wire and the layers of the brazing materials 4 and 5 is extremely low.

〔実施例〕〔Example〕

以下、本発明の実施例を第1図〜第9図を用いて説明す
る。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 9.

第1図(a)は、本発明の基本的な構成を示す図であ
る。半導体部品1および半導体部品1′は、半導体部品
1に設けられた接続端子部2と、半導体部品1′に設け
られた接続端子部3と、それら接続端子部2,3の間隙に
渡した金属細線6と、その金属細線6の各端をそれぞれ
を接続端子部2,3に接合した半田付層4,5からなるマイク
ロ継手構造によつて結合されており、接続端子部2,3の
間には、各接続端子部面に形成され、かつ、金属細線6
の端部を含む半田付層4,5と金属細線6のみからなる層
を含んでいる。
FIG. 1 (a) is a diagram showing the basic configuration of the present invention. The semiconductor component 1 and the semiconductor component 1'include a connection terminal portion 2 provided on the semiconductor component 1, a connection terminal portion 3 provided on the semiconductor component 1 ', and a metal passed through a gap between the connection terminal portions 2 and 3. The fine wire 6 and each end of the metal fine wire 6 are joined by a micro joint structure composed of the soldering layers 4,5 in which the respective ends are joined to the connection terminal portions 2 and 3, and between the connection terminal portions 2 and 3. Is formed on the surface of each connection terminal portion and has a thin metal wire 6
The soldering layers 4 and 5 including the end portions of and the layer including only the thin metal wires 6 are included.

いま、半導体部品1と半導体部品1′に温度変化のため
に相対変位δが生じて、マイクロ継手構造が、第1図
(a)から(b)に示す状態に変化したとする。この状
態は、材料力学的には第2図に示すように、両端が剛接
で、一端の位置が固定で、他端の位置が自由な長柱の問
題と等価であると見なせる。このとき、相対変位δと長
柱なる金属細線の端部における剪断力Fの間には、次式
(2)の関係が成り立ち、金属細線の断面形状を円とす
るとその断面2次モーメントは次式(3)で表わされ
る。
Now, it is assumed that the relative displacement δ occurs between the semiconductor component 1 and the semiconductor component 1'due to a temperature change, and the micro joint structure is changed from the state shown in Fig. 1A to the state shown in Fig. 1B. In terms of material mechanics, this state can be regarded as equivalent to the problem of a long column in which both ends are rigidly contacted, one end position is fixed, and the other end position is free, as shown in FIG. At this time, the relation of the following equation (2) is established between the relative displacement δ and the shearing force F at the end of the thin metal wire which is a long column, and when the cross-sectional shape of the metal thin wire is a circle, the second moment of area is It is expressed by equation (3).

F=12・E・I・δ/l3 ……(2) ここで、E:金属細線の弾性係数 l:金属細線のみからなる層の高さ I=πd4/64 ここで、d:金属細線の直径 すなわち、(2),(3)式からわかるように、相対変
位がδのときに発生する剪断力Fは、金属細線6の直径
dの4乗に比例するので、その直径dを小さくすること
で著しく低減できる。ちなみに、Niの弾性係数E=1.9
×1012dyn/cm2を用い、金属細線6のみからなる層の高
さlを300μm、金属細線6の直径dを5μmとして、1
00μmの相対変位δを生じさせたときの剪断力Fを試算
すると、F=2.6×10-2gとなり、半田材にかかる力は非
常に小さいものとなる。すなわち、半田層の破壊はなく
なる。また、金属細線6自体の歪もその直径dに比例し
て小さくできるため、金属細線6の歪を弾性限内に保つ
ことが可能となるので、低サイクル疲労は弾性歪内では
発生しないことから、金属細線6の繰返し変形に伴う疲
労破断を防ぐことが可能となる。
F = 12 · E · I · δ / l 3 ...... (2) where, E: elastic modulus of the metal thin wires l: thin metal wires only a layer height I = πd 4/64, where, d: Metal Diameter of fine wire That is, as can be seen from equations (2) and (3), the shearing force F generated when the relative displacement is δ is proportional to the fourth power of the diameter d of the fine metal wire 6, It can be significantly reduced by making it smaller. By the way, Ni's elastic modulus E = 1.9
X10 12 dyn / cm 2 was used, the height l of the layer consisting of the thin metal wires 6 was 300 μm, and the diameter d of the thin metal wires 6 was 5 μm.
When the shearing force F when a relative displacement δ of 00 μm is generated is calculated, F = 2.6 × 10 −2 g, and the force applied to the solder material is very small. That is, the solder layer is not destroyed. Further, since the strain of the thin metal wire 6 itself can be reduced in proportion to its diameter d, the strain of the thin metal wire 6 can be kept within the elastic limit, so that low cycle fatigue does not occur within the elastic strain. It is possible to prevent fatigue fracture due to repeated deformation of the thin metal wire 6.

すなわち、直径数μm程度で長さ数100μm以上の金属
細線を用いて、マイクロ継手構造に数100μmの金属細
線のみからなる層を形成すれば、例えば、配置基板とLS
Iチツプの相対変位が100μmに達する熱歪が繰返された
場合でも、疲労破壊の発生がなく信頼性の高いマイクロ
継手構造を得ることができる。
That is, by using a metal thin wire having a diameter of about several μm and a length of several hundred μm or more and forming a layer consisting of only a few hundred μm of metal thin wire in the micro joint structure, for example, the placement substrate and the LS
Even when the thermal strain in which the relative displacement of the I-chip reaches 100 μm is repeated, fatigue fracture does not occur and a highly reliable micro joint structure can be obtained.

一方、電気抵抗の点から見た場合に、マイクロ継手構造
が金属細線を含むためその電気抵抗の増加が心配される
が、金属細線を主に銅で構成した場合、銅の固有抵抗ρ
=1.7μΩ・cmを用い、金属細線の直径を5μm、長さ
を300μmとして、その電気抵抗値を計算すると26mΩと
なり、一端子当り26本の金属細線を用いるとすれば、抵
抗の並列回路となるから、マイクロ継手構造の電気抵抗
は1mΩとなり、この値は配線基板の配線抵抗と同等また
はそれ以下であるので、特に問題とはならない。そし
て、このときの一端子当りの剪断力も0.68gと小さい。
この剪断力は、金属細線をさらに細くするかあるいは金
属細線のみからなる層をさらに高くすることでさらに1
〜2桁程度下げることが可能である。
On the other hand, from the point of view of electrical resistance, the micro-joint structure contains fine metal wires, which may cause an increase in its electrical resistance.However, if the fine metal wires are composed mainly of copper, the specific resistance of copper ρ
= 1.7 μΩ · cm, the diameter of the metal wire is 5 μm, the length is 300 μm, and the electrical resistance is calculated to be 26 mΩ. If 26 metal wires per terminal are used, it will be a parallel circuit of resistors. Therefore, the electric resistance of the micro joint structure is 1 mΩ, and since this value is equal to or less than the wiring resistance of the wiring board, there is no particular problem. And, the shearing force per terminal at this time is as small as 0.68 g.
This shearing force is further increased by further thinning the metal thin wire or by further heightening the layer made of only the metal thin wire.
It is possible to reduce by about 2 digits.

第3図は、多層配線基板上にLSIチツプを実装するとき
の接合工程とモジユールの断面構造を示す図である。LS
Iチツプ7とアルミナセラミツクの多層配線基板8と
は、LSIチツプ7の面に形成された接続端子9と、多層
配線基板8の面に形成された接続端子10と、接続端子9,
10を対面させたその間隙を渡す磁性を有する金属を含ん
だ金属細線13と、接続端子9,10の面上に形成され、か
つ、金属細線13の各端を含む半田層11,12と、からなる
マイクロ継手構造によつて接合されている。
FIG. 3 is a diagram showing a bonding process when mounting an LSI chip on a multilayer wiring board and a cross-sectional structure of the module. LS
The I chip 7 and the alumina ceramic multilayer wiring board 8 are composed of a connection terminal 9 formed on the surface of the LSI chip 7, a connection terminal 10 formed on the surface of the multilayer wiring board 8, and a connection terminal 9,
A fine metal wire 13 containing a metal having a magnetic property that passes through the gap facing 10 and a solder layer 11, 12 formed on the surface of the connection terminals 9, 10 and including each end of the fine metal wire 13, Are joined by a micro joint structure made of.

第I工程は、磁性を有する金属を含んだ金属細線13を供
給する工程で、まず、接続端子10の位置に合せた直径50
μmのスルーホールを接続端子10の数だけ設けた非磁性
体の治具14を多層配線基板8の上方に配置し、次の内部
が磁性金属のNiで、表面層が電気・熱の良導体のCuでな
る長さ200μmで直径10μmの金属細線13を治具14上に
散布し、磁場を治具14の面に垂直方向にかけて、治具14
を細かく振動させる。このとき、金属細線13は、磁場に
より治具14面上で垂直に立つて、移動しながらスルーホ
ールを通つて接続端子10上に落下する。落下する金属細
線13の数量は治具14の通し穴の径を変えることによつて
調整できる。なお、接続端子10の上には、予めメツキあ
るいは蒸着等の手段を用いて所定組成の半田12をコーテ
イングしておく。
The first step is a step of supplying the thin metal wire 13 containing a metal having magnetism. First, the diameter 50 adjusted to the position of the connection terminal 10 is set.
A non-magnetic jig 14 provided with as many through-holes as the number of connection terminals 10 is arranged above the multilayer wiring board 8. The next inside is magnetic metal Ni and the surface layer is a good conductor of electricity and heat. A thin metal wire 13 made of Cu and having a length of 200 μm and a diameter of 10 μm is dispersed on the jig 14, and a magnetic field is applied in a direction perpendicular to the surface of the jig 14 to form the jig 14
Vibrate. At this time, the thin metal wire 13 stands vertically on the surface of the jig 14 due to the magnetic field, and drops on the connection terminal 10 through the through hole while moving. The number of falling metal wires 13 can be adjusted by changing the diameter of the through hole of the jig 14. Note that the solder 12 having a predetermined composition is coated on the connection terminal 10 in advance by using a means such as plating or vapor deposition.

第II工程はLSIチツプを位置めする工程で、チツプアラ
イナーによつて、多層配線基板8の接続端子10とそれに
対面するLSIチツプ7の接続端子9が互いに正確に合致
するようにLSIチツプ7を位置調整し、上方から静かに
金属細線13の林の上に載せる。LSIチツプ7の接続端子
9の上には、前記の接続端子10と同様に、半田11をコー
テイングしておく。なお、磁場は第II工程から印加し続
ける。
The second step is a step of locating the LSI chip, and the chip aligner is used to position the LSI chip 7 so that the connection terminals 10 of the multilayer wiring board 8 and the connection terminals 9 of the LSI chip 7 facing it are accurately aligned with each other. Adjust the position and gently place it from above on the forest of metal wires 13. Solder 11 is coated on the connection terminals 9 of the LSI chip 7 in the same manner as the connection terminals 10 described above. The magnetic field is continuously applied from the step II.

最終の第III工程は半田づけの工程で、ホツトガスある
いは赤外線加熱等の手段により半田11,12を溶融させ、
金属細線13を接続端子9,10に半田づけして最終工程を終
える。
The final third step is the soldering step, in which the solder 11 and 12 are melted by means such as hot gas or infrared heating,
The final step is completed by soldering the thin metal wires 13 to the connection terminals 9 and 10.

金属細線の層の高さは、金属細線13の長さと半田11,12
の量によつて調整される。本実施例では半田11,12の厚
さをそれぞれ20μmとし、金属細線の長さが200μmで
あるので、金属細線の層は160μmとなつている。
The height of the thin metal wire layer depends on the length of the thin metal wire 13 and the solder 11,12.
Is adjusted according to the amount of. In the present embodiment, the thickness of each of the solders 11 and 12 is 20 μm, and the length of the thin metal wire is 200 μm, so the layer of the thin metal wire is 160 μm.

ここで、アルミナセラミツクの多層配線基板に30mm角の
大型のLSIチツプを搭載した場合に半田付後の冷却過程
で生じる多層配線基板とLSIチツプ間に生ずる熱歪につ
いて検討してみる。その熱歪をδとすると、δ=ΔT・
Δα・W/2で表され、半田付温度と室温の差ΔT=300
℃,LSIチツプと多層配線基板の熱膨張率の差Δα=5×
10-6,LSIチツプの長辺の長さW=30mmとすれば、δ=30
0×5×10-6×30/2=22.5×10-6mm、すなわち、δ=22.
5μmである。
Here, let us examine the thermal strain generated between the multilayer wiring board and the LSI chip during the cooling process after soldering when a large 30 mm square LSI chip is mounted on the alumina ceramic multilayer wiring board. If the thermal strain is δ, then δ = ΔT ·
Expressed by Δα ・ W / 2, the difference between soldering temperature and room temperature ΔT = 300
℃, difference in thermal expansion coefficient between LSI chip and multilayer wiring board Δα = 5 ×
10 -6 , If the length of the long side of the LSI chip is W = 30 mm, δ = 30
0 × 5 × 10 -6 × 30/2 = 22.5 × 10 -6 mm, that is, δ = 22.
It is 5 μm.

本実施例によれば、上記の熱歪を金属細線の弾性歪範囲
内での曲り変形によつて吸収でき、また、稼働時に生ず
る低サイクル熱歪も上記熱歪より小さいので金属細線に
よつて容易に吸収できるため、半田付部、金属細線や接
続端子の熱破壊あるいは熱疲労破断を防ぐことができ
る。したがつて、大型LSIチツプを用いた電子装置の製
作を可能とすると同時にその信頼性を大きく向上するこ
とができる。
According to the present embodiment, the above thermal strain can be absorbed by bending deformation within the elastic strain range of the thin metal wire, and the low cycle thermal strain that occurs during operation is also smaller than the above thermal strain, so the thin metal wire is used. Since it can be easily absorbed, it is possible to prevent thermal breakage or thermal fatigue breakage of the soldered portion, the thin metal wire and the connection terminal. Therefore, it is possible to manufacture an electronic device using a large-sized LSI chip, and at the same time, greatly improve its reliability.

第4図は、接続端子および金属細線が、Fe,Ni,Coの内少
なくとも1種類を含む磁性材で構成されている場合の実
施例を示す図である。
FIG. 4 is a diagram showing an embodiment in which the connection terminal and the thin metal wire are made of a magnetic material containing at least one of Fe, Ni and Co.

LSIチツプ7の接続端子9は、LSIチツプ7の面上に形成
された前記磁性材でなる磁性端子膜17と、その磁性端子
膜17を覆う半田付用端子膜とから構成され、また、多層
配線基板8の接続端子10も、前記接続端子9と同じよう
に磁性端子膜16と半田付用端子膜18とから構成され、こ
れら接続端子9,10上に半田11,12がそれぞれ形成されて
いる。接続端子9,10を対向させ、その間隙に配置された
金属細線13の各端を半田11,12で半田付けすることによ
り、LSIチツプ7と多層配線基板8が一体に接合されて
いる。なお、半田付用端子膜は、半田のぬれ性を向上さ
せ、かつ、接続面積を広くするためのものである。
The connection terminal 9 of the LSI chip 7 is composed of a magnetic terminal film 17 formed on the surface of the LSI chip 7 and made of the above-mentioned magnetic material, and a soldering terminal film covering the magnetic terminal film 17, and also has a multilayer structure. The connection terminal 10 of the wiring board 8 is also composed of a magnetic terminal film 16 and a soldering terminal film 18 like the connection terminal 9, and solders 11 and 12 are formed on the connection terminals 9 and 10, respectively. There is. The LSI chip 7 and the multilayer wiring board 8 are integrally joined by connecting the connection terminals 9 and 10 to each other and soldering the ends of the thin metal wires 13 arranged in the gaps with the solders 11 and 12. The soldering terminal film is for improving the wettability of the solder and widening the connection area.

本実施例によれば、前記のような接合工程において磁場
をかけて金属細線を配向制御する場合に、「磁場中に置
かれた強磁性体の内部では他に比べて磁力線が密にな
り、その結果として磁性を有する金属細線は強磁性体に
引寄せられる」という作用を利用して、金属細線を接続
端子の中央部にまとめることができるため、隣り合う接
続端子が接近している場合や多少折れ曲がつた金属細線
が混じつている場合でも、ある接続端子に配置された金
属細線が隣の接続端子に接して短絡するということを防
止でき、接合工程における製品の不良発生率を低減して
歩留りの向上を図ることができる。また、前記第3図で
説明した第II工程のLSIチツプの位置決めにおいて、対
面する上下の接続端子間に多少心ずれがあつたとして
も、共に磁性を有する接続端子と金属細線が磁気力によ
り吸引し合うことにより自己調心されるという効果もあ
る。
According to the present embodiment, when controlling the orientation of the thin metal wires by applying a magnetic field in the above-described joining process, “the magnetic lines of force become denser than the other inside the ferromagnetic body placed in the magnetic field, As a result, the metal thin wire having magnetism is attracted to the ferromagnetic material. ”Therefore, since the metal thin wire can be gathered in the central portion of the connection terminal, when the adjacent connection terminals are close to each other, Even if a thin metal wire with some bends is mixed, it is possible to prevent the metal thin wire arranged on a certain connection terminal from contacting the adjacent connection terminal and short-circuiting, thus reducing the incidence of product defects in the bonding process. The yield can be improved. Further, in the positioning of the LSI chip in the step II described in FIG. 3, even if there is a slight misalignment between the upper and lower connecting terminals facing each other, the connecting terminal and the metal thin wire both having magnetism are attracted by the magnetic force. There is also the effect that self-alignment is achieved by interacting.

第5図は、LSIチツプ(2個)を配線基板(1個)に塔
裁する形態として中間基板をキヤリアに使う方式のキヤ
リア組立方法と組立てられるモジユールの断面を示す図
である。このキヤリア組立方法においては、LSIチツプ1
9および配線基板20は次のような形で供給される。すな
わち、LSIチツプ19は、その下面中央寄りの位置に数個
の接続端子21を設けその接続端子21面に層状に半田25を
形成し、LSIチツプ19の下面両端の位置にはダミー端子3
8を設けそのダミー端子面にボール状の半田24を形成し
ている形で供給され、一方、配線基板20は、その上面
に、前記接続端子21と前記ダミー端子38に対面する位置
に、それぞれ、接続端子22とダミー端子39を設け、接続
端子22にはその上に形成された半田26によつて磁性を有
する金属を含んだ金属細線27がほぼ垂直に半田付されて
おり、配線基板20の下面には反対面の接続端子22に対応
した接続端子23を設けた形で供給される。なお、磁性を
有する金属を含んだ金属細線27は、前記第3図の第I工
程の金属細線の供給後すぐに加熱することにより半田で
固定される。
FIG. 5 is a view showing a carrier assembling method in which an intermediate substrate is used as a carrier and a cross section of a module to be assembled in a form in which an LSI chip (two) is controlled to a wiring substrate (one). In this carrier assembly method, the LSI chip 1
9 and the wiring board 20 are supplied in the following manner. That is, the LSI chip 19 is provided with several connection terminals 21 at positions near the center of the lower surface of the LSI chip 19 and solder 25 is formed in layers on the surface of the connection terminals 21, and the dummy terminals 3 are provided at both ends of the lower surface of the LSI chip 19.
8 is provided in the form of forming a ball-shaped solder 24 on the dummy terminal surface thereof, while the wiring board 20 is provided on the upper surface thereof at positions facing the connection terminals 21 and the dummy terminals 38, respectively. The connection terminals 22 and the dummy terminals 39 are provided, and the connection terminals 22 are soldered with the thin metal wires 27 containing a magnetic metal by the solder 26 formed on the connection terminals 22 substantially vertically. It is supplied in a form in which a connection terminal 23 corresponding to the connection terminal 22 on the opposite surface is provided on the lower surface of the. The thin metal wire 27 containing a metal having magnetism is fixed by soldering by heating immediately after supplying the thin metal wire in the step I of FIG.

第5図に示した第I工程では、金属細線27は固定されて
いるので、磁場を印加する必要はなく、単にLSIチツプ1
9を中間基板20に位置合せして載せるだけである。
In the step I shown in FIG. 5, since the thin metal wire 27 is fixed, it is not necessary to apply a magnetic field, and the LSI chip 1 is simply used.
All that is required is to position 9 on the intermediate substrate 20 and place it.

次に第II工程においては、磁場が中間基板20の面に垂直
方向に印加され、加熱が行われる。半田24,25,26は、い
ずれも溶融し、金属細線27は、前記磁場によつてほぼ垂
直に立つたままで半田付される。このとき、ダミー端子
38,39の間で溶融した半田24は、その表面張力によつて
中間基板20とLSIチツプの互いに対面する接続端子の位
置ずれを修正する自己調心の役割を果す。
Next, in the step II, a magnetic field is applied in a direction perpendicular to the surface of the intermediate substrate 20 to heat the intermediate substrate 20. The solders 24, 25, 26 are all melted, and the thin metal wires 27 are soldered while standing substantially vertically by the magnetic field. At this time, the dummy terminal
The solder 24 melted between 38 and 39 plays the role of self-alignment for correcting the displacement of the connection terminals of the intermediate substrate 20 and the LSI chip facing each other due to the surface tension.

第6図は、前記第5図で説明したLSIチツプ・チツプキ
ヤリアのモジユールを大型計算機に組込んだ部分の断面
図である。第6図において、前記モジユールは、その下
方に配置された配線基板32と、上方と周囲を覆う冷却構
造体とからなる筐体内に密封されている。さらに詳しく
説明すると、前記モジユールは、その上部がLSIチツプ1
9であり、その下部が下面に接続端子23を有する中間基
板20であつて、それらが本発明に係るマイクロ継手によ
り接合されている。配線基板32は、その上面に、前記接
続端子23と対面する位置に設けられた接続端子34と前記
冷却構造体28の側壁を受けるメタライズ膜36を有してい
る。冷却構造体28は、筐体構造になつており、上蓋部に
あたるハウジング28aはその内部に水冷通路28eを有し、
ハウジング28aの下面には、前記LSIチツプ19に対面する
位置に、ベローズ28cを介して冷却ブロツク28dが県垂し
ており、その内部まで水冷通路28eが通じており、そし
て、四方を囲う側壁28bは下方の配線基板32にまで達し
ている。
FIG. 6 is a sectional view of a portion where the LSI chip / chip carrier module described in FIG. 5 is incorporated into a large-scale computer. In FIG. 6, the module is hermetically sealed in a housing including a wiring board 32 arranged below the module and a cooling structure covering the upper part and the surroundings. More specifically, the module has an LSI chip 1 on top.
9, the lower part of which is the intermediate substrate 20 having the connection terminals 23 on the lower surface, which are joined together by the micro joint according to the present invention. The wiring board 32 has, on its upper surface, a connection terminal 34 provided at a position facing the connection terminal 23 and a metallized film 36 that receives a sidewall of the cooling structure 28. The cooling structure 28 has a housing structure, and the housing 28a corresponding to the upper lid has a water cooling passage 28e therein.
On the lower surface of the housing 28a, at a position facing the LSI chip 19, a cooling block 28d hangs down via a bellows 28c, a water cooling passage 28e leads to the inside thereof, and side walls 28b surrounding the four sides. Has reached the wiring board 32 below.

上記のモジユール、配線基板、冷却構造体を一体に組立
る手順について説明すると、まず、配線基板32の上に前
記モジユールを載せ、予め配線基板32の接続端子34に予
めコーテイングしていた半田35によつて半田接合を行
う。ここで、半田35は、LSIチツプ19と中間基板20の接
合に用いた半田24,25,26より低融点のものである必要が
あり、半田24,25,26の95Pb−5Snよりも低融点の60Pb−4
0Snの半田が用いられる。次に冷却構造体28を、前記の
モジユール・配線基板の上にかぶせる。LSIチツプ19の
上面、冷却ブロツク28dの下面およびハウジング側壁28b
の下面には、いずれも半田ぬれ性のよい金属を予めメタ
ライジングしておく。冷却構造体をかぶせるとき、前記
2種類の半田よりさらに低融点(170℃以下)の半田箔3
3,37を、それぞれ、冷却ブロツク28dとLSIチツプ19間お
よびハウジング側壁28bとメタライズ膜36の間に挟んで
おく。そして、全体をHe雰囲気中で170℃以下の温度に
加熱して、半田箔33,37を溶融させて、LSIチツプ19と冷
却ブロツク28dを金属的に結合すると同時に前記匡体内
をHe雰囲気として気密に封じる。
Explaining the procedure for integrally assembling the above module, wiring board, and cooling structure, first, the module is placed on the wiring board 32, and the solder 35 previously coated on the connection terminal 34 of the wiring board 32 is preliminarily attached. Therefore, solder joining is performed. Here, the solder 35 needs to have a lower melting point than the solders 24, 25, 26 used for joining the LSI chip 19 and the intermediate substrate 20, and is more than 95P b −5S n of the solders 24, 25, 26. Low melting point 60P b −4
0S n solder is used. Then, the cooling structure 28 is placed on the module / wiring board. The upper surface of the LSI chip 19, the lower surface of the cooling block 28d, and the housing side wall 28b.
A metal having good solder wettability is metallized in advance on the lower surface of each of the above. Solder foil with a lower melting point (170 ° C or less) than the above two types of solder when covering the cooling structure 3
3, 37 are sandwiched between the cooling block 28d and the LSI chip 19 and between the housing side wall 28b and the metallized film 36, respectively. Then, the whole is heated to a temperature of 170 ° C. or less in a He atmosphere to melt the solder foils 33 and 37, and the LSI chip 19 and the cooling block 28d are metallically coupled, and at the same time, the enclosure is hermetically sealed as a He atmosphere. To seal.

本実施例によれば、冷却構造体28と配線基板32の熱膨張
差によつて、組立時の半田接合後の冷却過程で発生する
水平方向の熱歪を金属細線27の曲がり変形で吸収できる
ため、配線基板32と中間基板20とLSIチツプ19の各電気
接続部が断線することがなく、冷却ブロツク28dとLSIチ
ツプ19を半田固着する方式の実装が可能となる。その結
果、LSIチツプを高効率に冷却することが可能となり、
大集積・大電力のLSIチツプを使用できることから、大
型計算機としての性能、特に演算処理速度を大幅に向上
することが可能となる。また、配線基板と中間基板を同
じ材質で構成することにより、それらの電気的接続が要
求されるところでの半田の疲労破壊がなくなり、装置と
しての信頼性も大きく向上する。なお、LSIチツプと中
間基板間のダミー端子部の半田は破断するが、装置の機
能に何ら影響しないので、この破断は問題とはならな
い。
According to the present embodiment, due to the difference in thermal expansion between the cooling structure 28 and the wiring board 32, the horizontal thermal strain generated in the cooling process after solder joining during assembly can be absorbed by the bending deformation of the thin metal wire 27. Therefore, the wiring boards 32, the intermediate substrate 20, and the LSI chips 19 are not disconnected from each other, and the cooling block 28d and the LSI chips 19 can be mounted by soldering. As a result, it becomes possible to cool the LSI chip with high efficiency,
The ability to use large-scale, high-power LSI chips makes it possible to greatly improve the performance of large-scale computers, especially the processing speed. Further, by forming the wiring board and the intermediate board with the same material, fatigue breakdown of the solder is eliminated where electrical connection between them is required, and the reliability of the device is greatly improved. It should be noted that the solder in the dummy terminal portion between the LSI chip and the intermediate substrate breaks, but this does not affect the function of the device, so this break is not a problem.

第7図は、横方向の大きな相対変位を許容できる、1個
の中間基板と2個の補強基板からなる3段式チツプキヤ
リに、LSIチツプを搭載したモジユールの断面図であ
る。LSIチツプ19と補強基板43とは、LSIチツプ19に設け
られた接続端子46と、対面するそれら接続端子43,44の
間隙に渡した磁性を有する金属を含んだ金属細線57と、
その金属細線57の各端をそれぞれ接続端子45,46と接合
した半田付層51,52とからなるマイクロ継手構造によつ
て結合されている。補強基板43と補強基板44とは、上記
と同様の構成を有する。接続端子47,48と磁性を有する
金属を含んだ金属細線58と半田付層53,54とからマイク
ロ継手構造によつて結合され、また、補強基板43と中間
基板20も、上記と同じように、接続端子49,50と磁性を
有する金属を含んだ金属細線59と半田付層55,56とから
なるマイクロ継手構造により結合されている。
FIG. 7 is a cross-sectional view of a module in which an LSI chip is mounted on a three-stage chip carrier consisting of one intermediate board and two reinforcing boards, which allows a large lateral displacement. The LSI chip 19 and the reinforcing substrate 43 are a connection terminal 46 provided on the LSI chip 19, a thin metal wire 57 containing a metal having magnetism which is passed through a gap between the connection terminals 43 and 44 facing each other,
The ends of the thin metal wires 57 are joined together by a micro joint structure composed of soldering layers 51 and 52 joined to the connection terminals 45 and 46, respectively. The reinforcing substrate 43 and the reinforcing substrate 44 have the same configuration as the above. The connection terminals 47, 48, the metal thin wires 58 containing a metal having magnetism, and the soldering layers 53, 54 are joined by a micro joint structure, and the reinforcing substrate 43 and the intermediate substrate 20 are also the same as above. The connection terminals 49 and 50 are connected to each other by a micro joint structure composed of a metal thin wire 59 containing magnetic metal and soldering layers 55 and 56.

中間基板20とLSIチツプ19との相対変位が、100μmをは
るかに越えるような場合、中間基板20とLSIチツプ19を
直接的に結合するには、金属細線の長さもその相対変位
の数倍以上に長くしなければならない。実際上、直径10
μm程度の金属細線を1mm(1,000μm)以上もの長さで
取扱うと、曲りなどの問題を生じて取扱い性が悪くな
り、組立時の短絡による不良発生も多くなる。
When the relative displacement between the intermediate substrate 20 and the LSI chip 19 is much larger than 100 μm, the length of the fine metal wire must be several times or more the relative displacement in order to directly connect the intermediate substrate 20 and the LSI chip 19. Must be long. Practically a diameter of 10
If you handle a thin metal wire of about μm with a length of 1 mm (1,000 μm) or more, problems such as bending will occur and the handleability will deteriorate, and defects will often occur due to short circuits during assembly.

しかし、本実施例によれば、中間基板20とLSIチツプと
中間に補強基板43,44を設けているため、磁性を有する
金属を含んだ金属細線57,58,59は短くてよく、かつ、ト
ータルの金属細線のみからなる層を高くして変形能を上
げることができる。それにも拘らず、組立時の不良発生
率を小さくできて、装置の信頼性も向上できる。
However, according to this embodiment, since the intermediate substrate 20 and the LSI chip and the reinforcing substrates 43 and 44 are provided in the middle, the thin metal wires 57, 58 and 59 containing magnetic metal may be short, and The deformability can be increased by raising the layer consisting of the total metal fine wires. Nevertheless, the failure rate during assembly can be reduced and the reliability of the device can be improved.

〔参考例〕[Reference example]

第8図は、金属細線として銅線を用いた場合の配線基板
とLSIチツプの接続方法とモジユールの断面を示す図で
ある。このモジユールにおいて、アルミナセラミツク製
配線基板73と、LSIチツプ77とは、配線基板73に設けら
れた接続端子74と、LSIチツプ77に設けられた接続端子7
8と、対面するそれら接続端子74,78の間隙に渡した銅線
72と、その銅線72の各端をそれぞれ接続端子74,78と接
合したろう付け層75,79と、からなるマイクロ継手構造
によつて結合されている。なお、銅線72を配置する位置
決め板76は、モジユールに組込まれたまま残されてい
る。この位置決め板76は、電気的に絶縁性があり、熱膨
張率が配線基板73と同じかあるいはLSIチツプ77に同じ
ものがよく、ここでは、配線基板73と同じ材質のアルミ
ナセラミツクの100μmの薄板を用い、接続端子74の位
置に対応して直径約40μmのスルーホールを設けてい
る。
FIG. 8 is a diagram showing a method of connecting a wiring board and an LSI chip and a cross section of a module when a copper wire is used as the metal thin wire. In this module, the wiring board 73 made of alumina ceramic and the LSI chip 77 include a connection terminal 74 provided on the wiring board 73 and a connection terminal 7 provided on the LSI chip 77.
8 and the copper wire passed in the gap between those connecting terminals 74 and 78 facing each other
72 and a brazing layer 75, 79 in which each end of the copper wire 72 is joined to the connection terminals 74, 78, respectively, by a micro joint structure. The positioning plate 76 on which the copper wire 72 is arranged is left as it is in the module. The positioning plate 76 is preferably electrically insulating and has the same coefficient of thermal expansion as the wiring board 73 or the LSI chip 77. Here, a 100 μm thin plate made of the same material as the wiring board 73 is made of alumina ceramic. A through hole having a diameter of about 40 μm is provided corresponding to the position of the connection terminal 74.

第8図の第I工程において、配線基板73の直上に位置決
め板76を配置し、直径約10μmで長さで切り代のついた
銅線72を一接続端子当り8〜10本程度の割でスルホール
に植え込む。植込み完了後、全体を真空あるいは不活性
雰囲気中で、予め接続端子74にコーテイングしておいた
ろう材の融点以上に加熱し、銅線72を接続端子74にろう
付する。ここでのろう材はその融点が200℃〜900℃の範
囲のものならいずれでもよい。ろう付後は、位置決め板
76を利用して、銅線72を必要な長さに切りそろえる。
In step I of FIG. 8, a positioning plate 76 is arranged directly above the wiring board 73, and a copper wire 72 with a diameter of about 10 μm and a cut margin is provided at a rate of about 8 to 10 per connection terminal. Implant in the through hole. After the implantation is completed, the whole is heated in a vacuum or an inert atmosphere to a temperature equal to or higher than the melting point of the brazing material previously coated on the connection terminal 74, and the copper wire 72 is brazed to the connection terminal 74. Any brazing material may be used as long as its melting point is in the range of 200 ° C to 900 ° C. Positioning plate after brazing
Use 76 to trim the copper wire 72 to the required length.

第II工程においては、位置決め板76を銅線72の上端近く
まで持ち上げ、銅線72の束がまとまる状態にし、接続端
子78に予め半田79をコーテイングしたLSIチツプ77を位
置調整して銅線72の上に載せる。そして不活性あるいは
還元性雰囲気中で半田79をリフローして銅線72の上端を
接続端子78に半田付する。
In the second step, the positioning plate 76 is lifted up to near the upper end of the copper wire 72 to bring the bundle of copper wires 72 into a state of being bundled, and the LSI chip 77 having the solder 79 coated on the connection terminal 78 in advance is positionally adjusted to the copper wire 72. Place it on top. Then, the solder 79 is reflowed in an inert or reducing atmosphere to solder the upper end of the copper wire 72 to the connection terminal 78.

最後の第III工程においては、アルミナセラミツク製の
位置決め板76を配線基板73側に押し下げて全接合工程を
終了する。なお、位置決め板76の材料が、LSIチツプ77
と同等の熱膨張率を有するものである場合には、位置決
め板76をLSIチツプ77に近い位置に留めて接合工程を終
了する。これは、熱膨張差の大きい部品組合せの間で銅
線72の変形量を大きくとれるようにするためである。
In the final third step, the positioning plate 76 made of alumina ceramic is pushed down to the wiring board 73 side to complete the entire joining step. The material of the positioning plate 76 is the LSI chip 77.
If it has a coefficient of thermal expansion equivalent to, the positioning plate 76 is retained at a position close to the LSI chip 77, and the joining process is completed. This is because the amount of deformation of the copper wire 72 can be made large between combinations of components having a large difference in thermal expansion.

本参考例によれば、磁場の作用を利用しなくても金属細
線を接続端子面に垂直な方向にそろえることができ、か
つ、接続端子上に正確に位置決めできるため、LSIチツ
プ位置決め用治具などに磁性材を用いても問題ない。そ
して、磁場の方向や強さなどの解析も不用となるため、
組立て装置の設計が容易となる。また、金属細線を完全
な純銅で構成することができ、その接続部での電気抵抗
を下げられるという効果もある。なお、金属細線のみか
らなる層を設けたことによる熱歪の吸収の効果、すなわ
ち、接合部の破断や熱疲労破壊の防止に有効であること
は云うまでもない。
According to this reference example, the thin metal wires can be aligned in the direction perpendicular to the connection terminal surface without using the action of the magnetic field, and the positioning can be accurately performed on the connection terminal. There is no problem even if a magnetic material is used for such. And since analysis of the direction and strength of the magnetic field is also unnecessary,
The assembly device can be easily designed. In addition, the metal thin wire can be made of pure copper, and the electrical resistance at the connecting portion can be reduced. Needless to say, the effect of absorbing the thermal strain due to the provision of the layer consisting of the thin metal wires, that is, the effect of preventing the fracture of the joint and the thermal fatigue fracture is effective.

本参考例では、一例として、位置決め板を用いて金属細
線の方向付けおよび位置決めを行つたが、他の機械的な
手段を用いて本発明のマイクロ継手構造を実現しても何
らさしつかえない。
In this reference example, as an example, the positioning plate is used to orient and position the metal thin wire, but the micro joint structure of the present invention can be realized by using other mechanical means.

〔発明の効果〕〔The invention's effect〕

本発明は、以上説明したように、各被接合部材に設けら
れた接続端子部と、相互に対向するそれら接続端子部の
間隙に渡した金属細線と、その金属細線と前記接続端子
部を接合するろう材と、からなつており、かつ、前記接
続端子部間に金属細線のみからなる層を含んでいるの
で、被接続部材間に生じる相対変位を金属細線の曲り変
形によつて容易に吸収でき、金属細線の応力およびろう
付層の剪断応力を著しく低減できる。従つて、一方の接
合部材を半導体部品とし、他方の被接合部材を配線基板
として、温度変化のため半導体部品と配線基板の間に大
きな相対変位が生じた場合でも、その接合層が破断せ
ず、疲労寿命を向上させることができる。またLSIチツ
プが大型化した場合や、配線基板上に搭載したチツプキ
ヤリアやLSIチツプの上部を冷却体に金属的に結合して
冷却を行う電子装置を構成した場合でも、配線基板、チ
ツプキヤリア、LSIチツプ、冷却体の各間の熱的または
電気的接続部の熱歪による破断や熱疲労破壊を防ぐこと
ができ、電子装置の信頼性を著しく向上できるという効
果もある。
INDUSTRIAL APPLICABILITY As described above, the present invention provides a connection terminal portion provided on each member to be joined, a metal thin wire extending in a gap between the connection terminal portions facing each other, and the metal thin wire and the connection terminal portion are joined together. Since it includes a brazing filler metal and a layer made of only thin metal wires between the connecting terminal portions, relative displacement generated between the connected members is easily absorbed by bending deformation of the thin metal wires. Therefore, the stress of the thin metal wire and the shear stress of the brazing layer can be significantly reduced. Therefore, one joining member is a semiconductor component and the other joined member is a wiring board, and even if a large relative displacement occurs between the semiconductor component and the wiring board due to temperature change, the joining layer does not break. The fatigue life can be improved. In addition, even if the LSI chip becomes large, or if the chip carrier mounted on the wiring board or the electronic device configured to cool the metal by coupling the upper part of the LSI chip to the cooling body, the wiring board, the chip carrier, the LSI chip Also, it is possible to prevent breakage and thermal fatigue breakage due to thermal strain of the thermal or electrical connection between the cooling bodies, and it is possible to significantly improve the reliability of the electronic device.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の基本構造を示す図、第2図は金属細線
の変形状態を材料力学的に示す図、第3図は実施例によ
るLSIチツプと配線基板の接続方法とその断面構造を示
す図、第4図は他の構造の断面図、第5図は実施例によ
るチツプキヤリアの組立方法とその断面構造を示す図、
投6図はチツプキヤリアを用いた大型計算機の断面構造
を示す図、第7図は3段チツプキヤリアの断面構造を示
す図、第8図は金属細線に銅線を用いた参考例の組立方
法とその断面構造を示す図、第9図は将来の大型計算機
の一般的構成図、第10図は従来の半田継手改良案を示す
図である。 1,1′……被接合部材、2,3……被接合部材の接続端子
部、4,5……ろう材、6……金属細線。
FIG. 1 is a diagram showing a basic structure of the present invention, FIG. 2 is a diagram mechanically showing a deformed state of a thin metal wire, and FIG. 3 is a method for connecting an LSI chip and a wiring board and a sectional structure thereof according to an embodiment. FIG. 4 is a cross-sectional view of another structure, FIG. 5 is a view showing a method of assembling a chip carrier and its cross-sectional structure according to an embodiment,
Fig. 6 is a diagram showing the cross-sectional structure of a large-sized computer using a chip carrier, Fig. 7 is a diagram showing the cross-sectional structure of a three-stage chip carrier, and Fig. 8 is an assembling method of a reference example using a copper wire as a metal thin wire FIG. 9 is a diagram showing a sectional structure, FIG. 9 is a general configuration diagram of a future large-scale computer, and FIG. 10 is a diagram showing a conventional solder joint improvement plan. 1,1 '... Joined member, 2,3 ... Connection terminal of joined member, 4,5 ... Brazing material, 6 ... Metal fine wire.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松坂 矯 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 志田 朝彦 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (56)参考文献 特開 昭61−51838(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Matsuzaka 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Institute, Ltd. (72) Inventor Asahiko Shida 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Institute Co., Ltd. Within Hitachi Research Laboratory (56) Reference JP-A-61-51838 (JP, A)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】微小間隔を以て配置された被接合部材の相
互に対向する接合端子部を、その接合端子部とは異る材
質の接合材料によって接合するマイクロ継手構造におい
て、前記接合端子間に渡した磁性を有する金属を含んだ
金属細線と、少なくとも該金属細線の各端子と前記接続
端子部のそれぞれを接合したろう材と、から構成されて
いることを特徴とするマイクロ継手構造。
1. A micro-joint structure in which joining terminal portions of members to be joined which are arranged with a minute interval are opposed to each other by a joining material made of a material different from that of the joining terminal portion, and the joining terminals are passed between the joining terminals. 2. A micro joint structure comprising: a thin metal wire containing a magnetic metal and a brazing material that joins at least each terminal of the thin metal wire and each of the connection terminal portions.
【請求項2】前記被接合部材が半導体チップと配線基板
である場合において、その配線基板のそれぞれの前記接
続端子部および前記金属細線が、Fe、Ni、Coの内少なく
とも1種類を含む磁性材から構成されていることを特徴
とする特許請求の範囲第1項記載のマイクロ継手構造。
2. When the members to be joined are a semiconductor chip and a wiring board, each of the connection terminal portions and the thin metal wires of the wiring board contains a magnetic material containing at least one of Fe, Ni and Co. The micro joint structure according to claim 1, characterized in that
【請求項3】前記金属細線が、その内部が磁性金属で、
その表面層が電気的熱的に良導体である金属で構成され
ていることを特徴とする特許請求の範囲第1項記載のマ
イクロ継手構造。
3. The thin metal wire has a magnetic metal inside,
2. The micro joint structure according to claim 1, wherein the surface layer is made of a metal that is a good conductor electrically and thermally.
JP62145068A 1987-06-12 1987-06-12 Micro joint structure Expired - Lifetime JPH07120688B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62145068A JPH07120688B2 (en) 1987-06-12 1987-06-12 Micro joint structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62145068A JPH07120688B2 (en) 1987-06-12 1987-06-12 Micro joint structure

Publications (2)

Publication Number Publication Date
JPS63310127A JPS63310127A (en) 1988-12-19
JPH07120688B2 true JPH07120688B2 (en) 1995-12-20

Family

ID=15376638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62145068A Expired - Lifetime JPH07120688B2 (en) 1987-06-12 1987-06-12 Micro joint structure

Country Status (1)

Country Link
JP (1) JPH07120688B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054875A (en) * 2009-09-04 2011-03-17 Fujitsu Ltd Electronic device and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5509815A (en) * 1994-06-08 1996-04-23 At&T Corp. Solder medium for circuit interconnection
JP5292772B2 (en) * 2007-11-15 2013-09-18 富士通株式会社 Electronic component and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151838A (en) * 1984-08-22 1986-03-14 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054875A (en) * 2009-09-04 2011-03-17 Fujitsu Ltd Electronic device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS63310127A (en) 1988-12-19

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