JPH07140211A - Pattern generator for IC tester - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Reduce the amount of hardware for bus switching,
In addition, the pattern data can be generated without lowering the operation margin. [Structure] The address shifter shifts the system address by a predetermined number of bits according to the interleave method,
A count value is output from an empty bit generated by this shift processing to generate an interleave address, and a predetermined range of the shifted system address is output as a read address. The decoder decodes the interleaving address and outputs the first selection signal. The memory control means generates the second selection signal and the write address, and supplies the read / write control signal and the test pattern data to the pattern memory. The multiplexer provided for each segment of the pattern memory is
The read address and the address supplied to the pattern memory are input, and these are switched and output according to the first and second selection signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for inspecting the electrical characteristics of an IC (integrated circuit), and more particularly to a pattern memory in a pattern generator for generating an expected value of a device under test. The present invention relates to a pattern generation device of an IC test device that can write and read data simply and at high speed.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or part of the IC product in each process of the manufacturing department and inspection department and inspect its electrical characteristics. There is. The IC test device is a device for inspecting such electrical characteristics. The IC test apparatus supplies predetermined test pattern data to the device under test, reads the output data of the device under test based on the pattern data, and compares the output data of the device under test with an expected value to determine the basic data of the device under test. It analyzes whether there is no problem in the physical operation and function.

The test in the IC test apparatus is a direct current test (D
It is roughly divided into a C measurement test) and a function test (FC measurement test). The direct current test is to inspect whether or not the basic operation of the device under test is defective by applying a predetermined voltage or current from the DC measuring means to the input / output terminal of the device under test. On the other hand, in the function test, given pattern data for the test from the pattern generator to the input terminal of the device under test, the output data of the device under test is read, and there is no problem in the basic operation and function of the device under test. Is to be inspected.

FIG. 6 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC tester includes a tester unit 70 and I
C attachment device 7D. The tester unit 70 is the control means 7
1, DC measuring means 72, timing generating means 73, pattern generating means 74, pin control means 75, pin electronics 76 and fail memory 77. In the actual tester unit 70, various other components exist, but only necessary parts are shown in the present specification.

The tester section 70 and the IC mounting device 7D are connected by signal lines composed of a plurality (m) of coaxial cables corresponding to the total number m of input / output terminals of the IC mounting device 7D, and each terminal is connected. The connection relationships among the two are associated by a relay matrix (not shown), and various signals are transmitted between predetermined terminals. Note that this signal line is physically the IC mounting device 7D.
The same number as the total number m of input / output terminals exists.

The IC mounting device 7D is constructed so that a plurality of devices under test 7E can be mounted in a socket. Input / output terminals of device under test 7E and IC mounting device 7
The input and output terminals of D are connected in one-to-one correspondence. For example, in the case of the IC attachment device 7D capable of mounting 10 devices under test 7E having 28 input / output terminals, the total number of input / output terminals is 280.

The control means 71 controls the entire IC test apparatus,
It is used for operation and management, and has a microprocessor configuration. Therefore, although not shown, the control means 71 has a ROM for storing a system program, a RAM for storing various data, and the like. The control means 71 is
DC measuring means 72, timing generating means 73, pattern generating means 74, pin control means 75 and fail memory 7
7 through a tester bus (data bus, address bus, control bus) 7C.

The control means 71 sets the data for DC test to D
The C measurement means 72 outputs the timing data for starting the function test to the timing generation means 73, and the program and various data necessary for generating the test pattern are output to the pattern generation means 74. In addition to this, the control means 7
1 outputs various data to the respective constituent elements via the tester bus 7C. The control unit 71 also reads the test results (fail data and DC data) from the fail memory 77 and the DC measurement unit 72, performs various data processing, and analyzes the test data.

The DC measuring means 72 receives the DC test data from the control means 71 and performs a DC test on the device under test 7E of the IC mounting apparatus 7D based on the DC test data.
The DC measuring means 72 starts the DC test by inputting the measurement start signal from the control means 71, and writes the data indicating the test result in the register. When the DC measurement means 72 finishes writing the test result data, it outputs an end signal to the control means 71. The test result data written in the register in the DC measuring means 72 is read by the control means 71 via the tester bus 7C and analyzed there. In this way, the DC test is performed. Also, the DC measuring means 72
Are the reference voltages VIH, VIL, VO for the driver 7A and the comparator 7B of the pin electronics 76.
Outputs H and VOL.

The timing generating means 73 is a control means 71.
The timing data from 1 to 3 are stored in the internal memory, and the high-speed operation clock φ is output to the pattern generation means 74 and the pin control means 75 based on the timing data. Therefore, the operation speeds of the pattern generation means 74 and the pin control means 75 are determined by the operation clock φ from the timing generation means 73. Further, the timing generating means 73 is adapted to input the timing switching control data CH from the pattern generating means 74 and to switch the operation cycle, the phase and the like as appropriate based on the timing switching control data CH.
The H is output to the pin control means 75 and the fail memory 77.

The pattern generating means 74 uses a program method for generating regular test pattern data by various arithmetic processes according to a microprogram, and the same data as that of the device under test is previously stored in an internal memory (hereinafter referred to as a pattern memory). Irregular (random) by writing and reading it at the same address as the device under test
It operates by the memory stored method that generates various patterns (expected value data). As for the program method, the device under test is R
It corresponds to the case of a volatile memory such as AM (Random Access Memory), and the memory stored method corresponds to the case of a non-volatile memory such as a ROM (Read Only Memory). Even in the case of the memory stored method, the generation of the address supplied to the device under test is performed by the program method.

The pin control means 75 comprises a formatter 78 and a comparator logic circuit 79. The formatter 78 is composed of flip-flop circuits and logic circuits in multiple stages, and variously processes the test pattern data from the pattern generating means 74 to synchronize a predetermined applied waveform with the timing signal PH from the timing generating means 73. To the driver 7A of the pin electronics 76. The comparator logic circuit 79 is the comparator 7
The measured data P3 from B and the expected value data P4 from the pattern generating means 74 are compared and determined, and the determination result is output to the fail memory 77 as fail data FD.

The pin electronics 76 is composed of a plurality of drivers 7A and a comparator 7B. One driver 7A and one comparator 7B are provided for each input / output terminal of the IC attachment device 7D, and are connected via a signal line. That is, when the number of input / output terminals of the IC attachment device 7D is m, the number of drivers 7A and the number of comparators 7B are each m. However, when measuring a memory IC or the like, since a comparator is not required for the address terminal, the number of comparators may be small.

The driver 7A responds to the test pattern data P1 from the formatter 78 of the pin control means 75 according to the test pattern data P1.
A test signal is applied to the input / output terminals of the IC attachment device 7D, that is, the signal input terminals such as the address terminal, the data input terminal, the chip select terminal, and the write enable terminal of the device under test 7E, and the desired data is applied to the device under test 7E. Write.

The comparator 7B inputs the data output from the signal output terminal such as the data output terminal of the device under test 7E, compares the data with the reference voltages VOH and VOL at the timing of the strobe signal from the control means 71, and outputs the data. The comparison result (high level “1” or low level “0”) is output to the comparator logic circuit 79 as the measured data P3.

The fail memory 77 stores the fail data FD output from the comparator logic circuit 79, and is composed of a RAM that has a storage capacity similar to that of the device under test 7E and is readable and writable at any time. The fail memory 77 has a data input / output terminal that fixedly corresponds to the data output terminal of the IC attachment device 7D.

For example, when the total number of input / output terminals of the IC mounting device 7D is 280, and 179 of them are data output terminals, the fail memory 77 has the same number of data output terminals or the same number. It is composed of a memory having the above data input terminals. The fail data FD stored in the fail memory 77 is read out by the control means 71, transferred to a data processing memory (not shown), and analyzed. In this way, the function test is performed.

[0018]

The IC test apparatus is composed of hardware that performs data processing at about several tens of MHz, and makes extensive use of the pipeline method to make an operation clock (system clock) from the timing generation means 73. ) A clock machine that operates at high speed based on φ. That is, the IC test apparatus sets the operating conditions of each part through the tester bus 7C, writes desired pattern data in the pattern memory in the pattern generating means 74, and then activates the timing generating means 73. And
The high-speed operation clock φ is output to the pattern generation means 74 and the pin control means 75, and they are operated at high speed at about several tens of MHz.

Since the pattern generating means 74 generates the test pattern data by the program method, by using a part of the test pattern data as the read address of the pattern memory, the expected value data is generated at a high speed of about several tens MHz. be able to. Since the pattern generating means 74 employs the memory stored method that is generated by reading the expected value data stored in the pattern memory in advance at a high speed according to the read address as described above, the pattern memory 74 is expected to be used in the pattern memory. An address bus (tester bus) that transfers a write address when writing value data and an address bus (high-speed bus) that transfers a read address when reading expected value data from the pattern memory are mixed 2
It consists of a system bus.

FIG. 7 is a diagram showing the details of the pattern generating means composed of two buses for generating expected value data by such a memory stored system. In the figure, the pattern memory is composed of two pattern memories 8A and 8B capable of two types of memory access, a 2-way interleave access method and a non-interleave access method.

Flip-flop circuits 81, 86, 87,
Reference numerals 8C, 8D, and 8F are flip-flop circuits for pipeline processing, which operate according to the operation clock φ from the timing generating means 73. These flip-flop circuits 81, 86, 87, 8C, 8D and 8
Since F starts its operation only when the operation clock φ is input after the timing generating means 73 is activated, the read address RAD is stored in the pattern memories 8A and 8B.
Since it takes several cycles to reach the number of clocks, it is basically incompatible with a tester bus that does not have a pipeline configuration.

Therefore, conventionally, a multiplexer (MU) is provided in the preceding stage of the address shifter 83 and the pattern memories 8A and 8B.
X) 82, 88 and 89 are provided, and by switching these, the test pattern data can be written in one cycle of the tester bus 7C. In addition, MUX
The control unit 71 selectively connects and sets 82, 88 and 89. Therefore, MUX8
When the upper input terminals of 2, 88 and 89 are selected, the bus becomes a high-speed bus, high-speed reading processing of test pattern data is performed, and conversely, when the lower input terminal is selected, the bus becomes a tester bus. Writing processing of expected value data and the like is performed.

First, the operation of each part when the lower input terminals of the MUXs 82, 88 and 89 are selected to write the test pattern data to the pattern memories 8A and 8B, that is, in the test pattern data writing mode will be described. . Since the write address is temporarily stored in the address register 8L via the tester bus 7C, the MUX 82 outputs the write address WAD stored in the address register 8L to the address shifter 83.

In the test pattern data write mode, the address shifter 83 does not shift the write address and directly writes the write address to the upper input terminals of the MUXs 84 and 85 and the MUX.
Output to the lower input terminals of 88 and 89. The address shifter 83 outputs the least significant bit of the address to the MUX 8H. By the way, since the lower input terminals of the MUXs 88 and 89 are selected, the write address WAD output to the MUXs 84 and 85 has no meaning. MUX
88 and 89 output the write address WAD to the address terminals of the pattern memories 8A and 8B.

At this time, since the test pattern data is input to the data input terminal Din via the tester bus 7C and the gate 8P in the pattern memories 8A and 8B, the test pattern data is sequentially written to the predetermined write address WAD. In addition, when confirming the contents of the written test pattern data, the address registers 8L and MU are similarly used.
The read address is input to the address terminals of the pattern memories 8A and 8B through the X82, the address shifter 83, and the MUXs 88 and 89, and the test pattern data from the data output terminal Dout is read out through the MUX 8M, the gate 8N, and the tester bus 7C.

Next, the operation of each part in the case where the upper input terminals of the MUXs 82, 88 and 89 are selected and the test pattern data is read from the pattern memories 8A and 8B, that is, in the test pattern data read mode, will be described. The read address RAD created by the program processing in the pattern generating means 74 is fetched in the flip-flop circuit 81 in accordance with the operation clock φ and is output to the upper input terminal of the MUX 82. MUX8
Since the upper input terminal of 2 is selected, the read address RAD from the flip-flop circuit 81 is output to the address shifter 83.

The address shifter 83 uses the pattern memories 8A and 8B in the test pattern data read mode.
If the memory access method is a 2-way interleave access method, the read address RAD shifted by one bit is used. If the memory access method is a non-interleaved access method, the read address RAD that is not shifted is applied to the upper input terminals of the MUXs 84 and 85 and the MUX 88, respectively. And 89 to the lower input terminals. Further, the address shifter 83 sets the least significant bit of the read address RAD to MUX.
Output to the upper input terminal of 8H. However, in the test pattern data read mode, the MUXs 88 and 89
Since the upper input terminal is selected, the read address RAD directly input from the address shifter 83 to the lower input terminals of the MUXs 88 and 89 becomes meaningless.

In the MUX 8H, in the test pattern data read mode, when the memory access method of the pattern memories 8A and 8B is the 2-way interleave access method, the lower input terminal is selected, the count value from the counter 8G and its inverted output value. To the selection terminal S of the MUX 84 and 85, and the read address R output from the address shifter 83 in the case of the non-interleaved access method.
The least significant bit of AD and its inverted output value are output to the selection terminals S of the MUXs 84 and 85.

The MUXs 84 and 85 input the read address RAD from the address shifter 83 to the upper input terminal,
Next-stage flip-flop circuits 86 and 8 are provided at the lower input terminals.
The read address RAD of one clock before output from 7 is input, and one of the read addresses RAD is output to the flip-flop circuits 86 and 87 according to the input level of the selection terminal S.

The flip-flop circuits 86 and 87 are M
Read addresses RAD output from the UXs 84 and 85 are fetched at the cycle of the operation clock φ, and the MUXs 84 and 85
Feedback to the lower input terminal of MUX88
, And 89 to the upper input terminals. At this time, MUX
Since the upper input terminals of 88 and 89 are selected,
The read address RAD from the flip-flop circuits 86 and 87 is transferred to the address terminal A of the pattern memories 8A and 8B.
Output to DR.

The read address R is supplied to the address terminals ADR of the pattern memories 8A and 8B at the cycle of the operation clock φ.
Since AD is input, the test pattern data corresponding to the read address RAD is sequentially output from the data output terminals Dout of the pattern memories 8A and 8B to the flip-flop circuits 8C and 8D at the cycle of the operation clock φ.

The MUX 8E is a flip-flop circuit 8C.
From the flip-flop circuit 8D is input to the lower input terminal. On the other hand, the delay circuits 8J and 8K are MUXs.
The output from 8H is delayed by two operation clocks φ and output to the selection terminal S of the MUX 8E. Therefore, M
The UX8E outputs the read address RAD output from the address shifter 83 to the flip-flop circuit 86 or 87 by two operation clocks before.
Selection processing is performed corresponding to 4 or 85.

That is, the read address RAD from the address shifter 83 corresponding to two operation clocks before is M.
When the flip-flop circuit 86 is loaded via the UX 84, the upper input terminal of the MUX 8E is selected, so the test pattern data loaded in the flip-flop circuit 8C is output via the flip-flop circuit 8F. It Conversely, the read address RAD from the address shifter 83 corresponding to two operation clocks before is MU.
When the flip-flop circuit 87 is loaded via X85, the lower input terminal of the MUX 8E is selected, so the test pattern data loaded in the flip-flop circuit 8D is output via the flip-flop circuit 8F. To be done.

As described above, conventionally, the MUX 8 is provided in the preceding stage of the address shifter 83 and the preceding stages of the pattern memories 8A and 8B.
2, 88 and 89 are provided, and when the upper input terminals of the MUXs 82, 88 and 89 are selected, high-speed read processing of test pattern data is performed as a high-speed bus, and conversely, when the lower input terminals are selected, tester bus is performed. Then, the control means 71 performs the writing process of the test pattern data.

However, conventionally, a multiplexer (MUX 82, 8) is used to switch between the high speed bus and the tester bus.
8) and 89), there is a problem that the amount of hardware becomes too large. Further, this multiplexer causes an increase in the data arrival time from the flip-flop circuits 86 and 87 for pipeline processing to the next-stage flip-flop circuit 8F, which causes a problem that the operation margin of the entire system is reduced.

The present invention has been made in view of the above-mentioned points, and the pattern generation of the IC test apparatus which can reduce the amount of hardware for bus switching and generate the test pattern data without lowering the operation margin. The purpose is to provide a device.

[0037]

A pattern generator of an IC test apparatus according to the present invention stores test pattern data to be supplied to a device under test in a pattern memory in advance according to a first clock, In a pattern generator of an IC test apparatus for generating desired test pattern data by reading it in synchronization with a second clock, a counter that counts the second clock and outputs the count value, and a counter Value and the second
The first address generated in synchronization with the clock is input, the first address is shifted by a predetermined bit according to the interleave access method, and the count value is output from the empty bit generated by this shift processing. To generate an interleave address and output a predetermined range of the shifted first address as the read address, and to decode the interleave address from the address shifter to generate a first selection signal. And a second selection signal and a second selection signal to be supplied to the pattern memory.
Memory address generating means for generating the address in synchronization with the first clock and supplying the read / write control signal and the test pattern data to the pattern memory, the second address, the read address from the address shifter and the A plurality of multiplexers for inputting the addresses supplied to the pattern memory, switching them according to the first and second selection signals, and outputting the same; and the pattern for latching the read addresses output from the multiplexers. The latch circuit is controlled so as to output to the memory, feed back to the input terminal of the multiplexer, and directly output to the pattern memory without latching the second address.

[0038]

Conventionally, the pattern generator of the IC test apparatus stores the test pattern data to be supplied to the device under test in the pattern memory in advance according to the low-speed CPU clock (first clock), and stores it. The desired test pattern data is generated by reading in synchronization with the high-speed system clock (second clock).

In the present invention, the counter and the address shifter are used to generate the interleave address and the read address. That is, the counter counts the high-speed second clock and outputs the count value. The address shifter inputs the count value and a first address (system address) generated in synchronization with the second clock, shifts the first address by a predetermined bit in accordance with the interleave access method, The interleaving address is generated by outputting the count value from the empty bit generated by this shift processing.

For example, when the pattern memory is divided into four segments, 1 Way (non), 2 W
Since the interleave access method of ay and 4Way is possible, the lower 2 bits of the first address are used as the interleave address. Then, the address shifter does not perform shift processing in the case of 1-way (non) interleaving, and outputs the lower 2 bits of the first address as an interleaved address, and outputs 2 way.
In the case of interleave, shift processing is performed by 1 bit,
A total of 2 bits of the lower 1 bit of the counter value and the lower 1 bit of the first address are output as an interleave address. In the case of 4 Way interleave, shift processing is performed by 2 bits, and 2 bits of the counter value are output as an interleave address.

Further, the address shifter outputs a predetermined range of the shifted first address as a read address. That is, the address shifter does not shift in the case of 1-way (non) interleaving.
A first address other than bits, that is, a value obtained by dividing the first address by 4 is output as a read address, and 2 Way is output.
In the case of interleaving, the first address other than the lower 2 bits shifted by 1 bit, that is, the value obtained by dividing the first address by 2 is output as the read address,
In the case of 4-way interleave, the first address other than the lower 2 bits shifted by 2 bits, that is, the first address is output as it is as the read address.

The decoder decodes the interleave address from the address shifter and outputs the first selection signal. Here, the first selection signal is for selecting a segment forming the pattern memory. The memory control means mainly operates when writing the test pattern data in the pattern memory, and sets the second selection signal and the second address to be supplied to the pattern memory as the first.
It is generated in synchronism with the clock signal and the read / write control signal and the test pattern data are supplied to the pattern memory.

Each multiplexer inputs the second address, the read address from the address shifter, and the address supplied to the pattern memory, and switches and outputs them according to the first and second selection signals. The latch circuit is controlled so that the read address output from the multiplexer is latched and output to the pattern memory and fed back to the input end of the multiplexer, and the second address is directly output to the pattern memory without latching. ing.

That is, when the multiplexer reads the test pattern data from the pattern memory at high speed,
When the read address from the address shifter or the address supplied to the pattern memory from the latch circuit is alternately switched according to the interleaving address from the decoder and supplied to the pattern memory, and the test pattern data is written to the pattern memory at low speed. The second address from the memory control means is supplied to the pattern memory without operating the latch circuit. As a result, the pattern generator of the present invention can reduce the amount of hardware for bus switching, and can generate test pattern data without reducing the operation margin.

[0045]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a pattern generating apparatus of an IC test apparatus according to the present invention. Figure 2
Is the pattern memory (memory segment # 0
It is a figure which shows the detail of the peripheral circuit of- # 3). FIG. 3 shows FIG.
It is a figure which shows the detailed structure of the internal memory control means 1D.
FIG. 4 is a diagram showing details of the address distribution circuit for interleave access, which includes the flip-flop circuit 11, the counter 12, the address shifter 13, the decoder 14, the multiplexers MUX0 to 3 and the latch circuits 16 to 19 in FIG.

First, the circuit configuration around the pattern memory (memory segments # 0 to # 3) will be described in detail with reference to FIG. The pattern memory of the present embodiment is capable of three types of memory access including a 4-way interleave access method, a 2-way interleave access method, and a non (1 Way) interleave access method, and 4I /
It has a variable I / O mechanism of O, 8 I / O, 16 I / O, and 32 I / O, is composed of four memory segments # 0 to # 4 in total, and further each memory segment # 0 to #. 4 is divided into eight memory blocks # 0 to # 7. That is, there are 32 pattern memories in total.
It is composed of individual memories M00 to M37.

Memories M00 to M of the memory segment # 0
07 is a write enable signal WE0 from the write enable control 46 of FIG.
Are typing in. Similarly, memory segment # 1 to
# 3 memories M10 to M17, M20 to M27 and M3
0 to M37 input the write enable signals WE1, WE2 and WE3 from the write enable control 46 to the enable terminals WE1, WE2 and WE3, respectively.

The memories M00 to M30 of the memory block # 0 of each of the memory segments # 0 to # 3 have the chip select signal CS from the chip select control 44 of FIG.
0 is input to the chip select terminal CS0. Similarly, the memories M01 to M3 of the memory blocks # 1 to # 7 will be described below.
1, M02 to M32, M03 to M33, M04 to M3
4, M05-M35, M06-M36 and M07-M3
A chip select terminal CS1 receives chip select signals CS1 to CS7 from the chip select control 44.
~ CS7 is input respectively.

In the memories M00 to M30 of the memory block # 0 of each of the memory segments # 0 to # 3, the test pattern data MD0 to MD3 from the data shifter 48 of FIG. 4 are input to the data input terminals Din0-3. Similarly, the memories M01 to M3 of the memory blocks # 1 to # 7 will be described below.
1, M02 to M32, M03 to M33, M04 to M3
4, M05-M35, M06-M36 and M07-M3
7 is the test pattern data MD from the data shifter 48.
0-MD3 to the data input terminals Din4-7, Din8-
11, Din12-15, Din16-19, Din2
0-23, Din24-27, and Din28-31, respectively.

Memories M00 to M of memory segment # 0
07 is a data output terminal Dout0-3, Dout4-
7, Dout8-11, Dout12-15, Dout
16-19, Dout20-23, Dout24-27
And 32-bit test pattern data MD0-MD31 output from Dout 28-31 to the 0th terminal of the multiplexer (MUX) 1A.

Similarly, memory segments # 1 to # 3
Memory M10-M17, M20-M27 and M30-
M37 is a data output terminal Dout0-3, Dout4
-7, Dout8-11, Dout12-15, Dou
t16-19, Dout20-23, Dout24-2
7 and Dout 28-31 to output 32-bit test pattern data MD0-MD31 to the 0th to 3rd terminals of the multiplexer (MUX) 1A, respectively.

The multiplexer (MUX) 1A selects the addresses A0-A1 from the selection circuit 15 as selection terminals S0 and S0.
By inputting 1 into memory segments # 0 to #
It is determined which one of 3 outputs the test pattern data MD0 to MD31 to the data shifter 1B. The data shifter 1B controls the output bit width of the test pattern data MD0-MD31 by shifting the test pattern data MD0-MD31 according to the higher-order 3-bit address A20-A22. The data shifter 1B is composed of four 8-bit shift matrix ICs.

The flip-flop circuit 1C operates in response to the operation clock φ1 from the timing generating means 73 and is a flip-flop circuit for pipeline processing. The flip-flop circuit 1C operates according to the operation clock φ1 from the timing generating means 73, and the test pattern data MD0-MD3 from the data shifter 1B.
Input 1 and output sequentially.

As shown in FIG. 2, the selection circuit 15 includes an AND circuit 21, a flip-flop circuit 22, an OR circuit 23,
24, and selectively outputs either the read address RA0-RA1 from the address shifter 13 or the write address WA0-WA1 from the internal memory control means 1D to the multiplexer (MUX) 1A, and the address shifter. 13 read addresses RA20-RA22 or internal memory control means 1D write address WA20.
-Data shifter 1B selectively selects one of WA22
Output to.

Next, the internal memory control means 1 will be described with reference to FIG.
The detailed configuration of D will be described. Internal memory control means 1
D is a pattern memory (each memory segment # 0 to # 4)
It operates when writing or reading the test pattern data MD0-MD31 to or from the test pattern data MD0-MD31 in synchronization with the CPU clock via the tester bus 7C. Address counter 4
Reference numerals 1, 42 and 43 designate write addresses and read addresses of the pattern memory, which are controlled by the carry control 45 in correspondence with the interleave mode and operate as three types of counters.

That is, the address counters 41 and 42
Is a 1-bit counter, and the address counter 43 is 2
Although it is a 1-bit counter, it is 23 as it is by the carry control 45 in the non-interleave mode.
It operates as a counter for bits (WA0-WA22). In the 2-way interleave mode, the address counter 41 operates as a 1-bit (WA0) counter, and the address counters 42 and 43 are 22-bit (WA0).
1-WA22) operates as a counter.

In the 4-way interleave mode, the address counters 41 and 42 are 2 bits (WA0-WA).
The address counter 43 operates as a 1-bit counter, and the address counter 43 operates as a 21-bit (WA2-WA22) counter. It should be noted that the address counter 43 uses the upper 3 bits W
A20-WA22 chip select control 44,
It outputs to the address shifter 47 and the selection circuit 15. The address counter 41 writes the count value and the least significant bit address (WA0) to the write enable control 46.
The address counter 42 outputs the count value and the lower bit address (WA1) to the first terminal W0 of the write enable control 46.

The carry control 45 controls the outputs of the address counters 41 and 42 as described above according to the interleave mode signal EM input to the mode terminal MODE. The carry control 45 also inputs the memory port enable signal MPE to the master enable terminal ME and controls the output of the pattern memory.

The write enable control 46 supplies the interleave mode signal EM to the mode terminal MODE.
Write control signal CPU to write / read control terminal R / W
R / W, the lower bit address WA1 of the address counter 42 is input to the first terminal W0, and the least significant bit address WA0 of the address counter 41 is input to the second terminal W1, respectively, and the write enable signal WE0 is input according to these signals.
Control the output of WE3.

For example, when the interleave mode signal EM indicates the non-interleave mode, the first terminal W
According to 0 and the low level “0” or the high level “1” of the second terminal W1, only one of the write enable signals WE0 to WE3 is enabled and one segment of the pattern memory is enabled. In the 2-way interleave mode, any two write enable signals WE0 to WE3 are valid according to the low level “0” or the high level “1” of the first terminal W0 or the second terminal W1 and the pattern is set. Enable two segments of memory. Further, in the case of the 4-way interleave mode, all the write enable signals WE0 to WE3 are enabled and all the segments of the pattern memory are enabled.

The chip select control 44 applies the memory port enable signal MPE to the enable terminal EN.
The variable output control signal I / O M to the mode terminal MODE.
ODE is input to the chip select terminal CC, and the upper 3 bit addresses WA20-WA22 from the address counter 43 are respectively input, and chip select signals CS0-CS7 based on these signals are input to the memory blocks # 0 to # 7 of the pattern memory. Output to the chip select pin.

For example, the variable output control signal I / O MOD
If E is in 4 I / O mode, address counter 43
Select only one of the memory blocks based on the higher-order 3-bit address WA20-WA22 from
In the case of 8 I / O mode, select any two memory blocks, in the case of 16 I / O mode, select any four memory blocks, and in the case of 32 I / O mode, select all memory blocks Select.

Further, the address shifter 47 receives the upper 3-bit address WA20-W from the address counter 43.
A22 is shifted according to the variable output control signal I / O MODE. The data shifter 48 shifts the test pattern data MD0-MD31 according to the upper 3 bits shifted by the address shifter 47. The data shifter 48 is composed of four 8-bit shift matrix ICs.

Next, the detailed structure of the address distribution circuit for interleaved high speed access will be described with reference to FIG. This address distribution circuit operates when the test pattern data is read out at high speed from the pattern memory (memory segments # 0 to # 3). The input stage flip-flop circuit 11 uses the read address RAD created by the program processing in the pattern generating means 74 as the operation clock φ.
It is taken in according to 1 and output to the address shifter 13.

The 2-bit counter 12 is for generating an interleave address, is composed of a binary counter, and outputs its count value to the address shifter 13. The address shifter 13 outputs 2 when the memory access method of the pattern memory is the 4-way interleave access method in the test pattern data read mode.
Multiplexers MUX0 to MUX3 are provided for the read addresses shifted by only one bit, the read addresses shifted by one bit in the case of the 2-way interleave access method, and the read addresses not subjected to the shift in the case of the non (1 Way) interleave access method.
To the 0th input terminal D0.

Further, the address shifter 13 outputs the count value R from the 2-bit counter 12 when the memory access system of the pattern memory is the 4-way interleave access system in the test pattern data read mode.
In the case of the 2-way interleave access method, A0-RA1 is set to the interleaving address RA0 from the 2-bit counter 12 and the least significant bit RA1 of the read address RAD from the input stage flip-flop circuit 11 subjected to the 1-bit shift to non ( In the case of the 1 Way) interleave access method, the least significant 2 bits RA0-RA1 of the read address RAD that is not subjected to the shift processing are output to the decoder 14 and the selection circuit 15 as an interleave address. That is, in the case of the non (1 Way) interleaved access method, the 2-bit counter 12
The count value of is meaningless. Further, the address shifter 13 uses the upper 3 bits RA20-R of the read address RAD.
A22 is output to the selection circuit 15.

The decoder 14 receives the interleaving addresses RA0-RA1 from the address shifter 13,
A selection signal based on it is sent to each of the multiplexers MUX0 to MUX0.
It is selectively output to the selection terminal S0 of the MUX3. That is, the decoder 14 uses the interleaving address RA1.
-Multiplexer MUX0 when RA1 is "00"
In case of “01”, MUX1 and in case of “10”, MUX1
A selection signal is output to MUX3 when it is "11" to UX2.

The multiplexers MUX0 to MUX3 input the read addresses RA2 to RA19 from the address shifter 13 to the 0th input terminal D0, and one clock before being output from the latch circuits 16 to 19 of the next stage to the first input terminal D1. Read addresses A2-A19 are input, write addresses WA2-WA19 from the internal memory control means 1D are input to the second and third input terminals D2, D3, and select terminals S0, S1.
One of the addresses A2-A depending on the input level of
19 is output to the latch circuits 16 to 19.

When the latch clock LC from the internal memory control means 1D falls at the time when the output of the decoder 14 is at the low level "0", the latch circuits 16 to 19 are input through the multiplexers MUX0 to MUX3 at that time. Addresses A2 to A19 to be stored are stored, and other than that, the own output is maintained. Therefore, the latch circuits 16 to 19
It works to extend the cycle of the address given to the pattern memory four times as much as the operation clock φ1.

On the other hand, at the time of CPU access, the multiplexers MUX0 to MUX3 input the high level "1" CPU clock CLK to the selection terminal S1.
The addresses WA2-WA19 from the address counter 43 of the internal memory control means 1D are output to the latch circuits 16-19.

Further, the latch circuits 16 to 19 receive the CPU clock CLK and the operation clock .phi.2 (clock having a phase different from that of the operation clock .phi.1) from the internal memory control means 1D, and output the negative value of the logical sum thereof. Since the latch clock LC is input from the circuit 1E, CP
When the U clock CLK is input, the through state is set, and the addresses WA2-WA19 from the address counter 43 of the internal memory control means 1D are directly output to the pattern memory (memory segments # 0 to # 3).

The above operation will be described with reference to the time chart of FIG. FIG. 5 is a time chart showing the operation at the time of interleaved high-speed access, where (a) is 4 Way.
The read address RAD at the time of interleave high-speed access, (b) at the time of 2-way interleave high-speed access, and (c) at the read address RAD at the time of 1-way interleave high-speed access
It shows a relationship with an address given to each pattern memory (memory segments # 0 to # 3).

In FIG. 5, the operation clock φ1 is several tens to
It has a frequency of hundreds of tens of MHz. Since the frequency of the operation clock φ1 is determined by the access cycle time of the device under test 7E, it is not fixed like a large computer, but is determined by a program according to the reading method. Therefore, (a) to (c) of FIG.
In the case where the minimum access cycle time of the device under test is Ta, in the case of the 4-way interleave access method, the operation clock φ1 becomes a cycle of 1/4 of the access cycle minimum time Ta, and in the case of the 2-way interleave access method, Ta. The cycle is half that of Ta, and the cycle is the same as Ta in the case of the 1-way interleave access method.

First, the 4-way interleaved high speed operation of FIG. 5A will be described. The input stage flip-flop circuit 11 has “0” in synchronization with the operation clock φ1.
"0", "1", "3", "3", "3", "4",
Read addresses RAD of "5", "6", and "7" are sequentially input. At this time, the address shifter 13 shifts the read address RAD by 2 bits, and the counter 12
Value from 0, that is, the least significant 2 bits RA0-R
A1 is output to the decoder 14 as an interleaved address. At this time, the decoder 14 sets the multiplexer MUX0 when the interleaving addresses RA1-RA1 are "00", and sets the multiplexer MUX1 when "01" and "1".
In the case of "0", the selection signal is output to MUX2, and in the case of "11", the selection signal is output to MUX3.
UX1, MUX2, MUX3, MUX0, MUX1, M
The selection signal is output in order of UX2 and MUX3 in synchronization with the operation clock φ1.

At this time, the latch circuit 16 operating clock φ
The first read address “0” is latched in synchronization with 1. However, the second to fourth read addresses “0”,
At the time of inputting "1" or "3", the selection terminal S of the MUX0
Since the selection signal is not input to 0, the output of the latch circuit 16 is circulated during this period and the same read address "0" is supplied to the memory segment # 0 of the pattern memory. Similarly, MUX1 to MUX3 and latch circuits 17 to 19 will be described below.
Also operates to supply the read address ADR to the memory segments # 0 to # 3 during the minimum time Ta of the access cycle. Therefore, in the memory segments # 0 to # 3, the read addresses “0”, “0”, “1”, “3”,
"3", "3", "4", "5", "6", "7" will be supplied.

The 2-way interleave high-speed operation of FIG. 5B will be described. In the case of the 2-way interleaved access method, the operation clock φ1 has a cycle of half the access cycle minimum time Ta. Ie 2
The operation clock φ1 in the Way interleave access method has a cycle twice as long as that in the case of FIG. Read addresses RAD of "0", "0", "3", "3", "3" are sequentially input to the input stage flip-flop circuit 11 in synchronization with the operation clock φ1. At this time, the address shifter 13 shifts the read address RAD by one bit, sets the count value from the counter 12 as the least significant bit RA0 of the interleaved address, and sets the least significant bit of the read address RAD as the least significant bit RA1 of the interleaved address. Output to the decoder 14.

Therefore, when the first read address is "0", the decoder 14 has the interleave address R.
Since "00" is input as A1-RA1, MUX0
The selection signal is output to. Similarly, when the second read address is "0", RA1-RA0 is "01", MUX1 is selected, and when the third read address is "3", RA1-RA0 is "10", and MU is selected.
RA1-RA0 becomes "11" when X2 is selected and the fourth read address "3" is selected, and RA1-R is selected when MUX3 is selected and the fifth read address "3" is selected.
A0 becomes "10", and MUX2 is selected. At this time, 1-bit shifted read addresses of the read addresses are input to MUX0 to MUX3 as read addresses RA2-RA19. Therefore, "0", "0", "1", "1" and "1" are supplied as read addresses.

The 1-way interleave high speed operation of FIG. 5C will be described. In the case of the 1-way interleave access method, the operation clock φ1 has the same cycle as the access cycle minimum time Ta. That is, 1 Way
The operation clock φ1 of the interleave access method is shown in FIG.
The period is four times as long as in the case of (a). Read addresses RAD of "0", "1", and "3" are sequentially input to the input stage flip-flop circuit 11 in synchronization with the operation clock φ1. At this time, the address shifter 13 does not shift the read address RAD and directly shifts the lower 2 bits RA.
Decoder 1 with 1-RA0 as interleaved address
Output to 4.

Therefore, in this case, the read address RAD
There is a one-to-one correspondence between the memory segment and the memory segment. That is, when the read address RAD is "0", the address "0" of the memory segment # 0 is accessed, and when the read address RAD is "1", the address "0" of the memory segment # 1 is accessed. When the read address RAD is "3", the address "0" of the memory segment # 3 is accessed.

[0080]

As described above, according to the present invention, it is possible to reduce the amount of hardware for bus switching and to generate test pattern data without lowering the operation margin.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a pattern generation device of an IC test apparatus according to the present invention.

FIG. 2 is a diagram showing details of peripheral circuits of a pattern memory (memory segments # 0 to # 3) in FIG.

FIG. 3 is a diagram showing a detailed configuration of an internal memory control unit of FIG.

FIG. 4 is a diagram showing details of an address distribution circuit for interleave access, which includes the flip-flop circuit, the counter, the address shifter, the decoder, the multiplexer, and the latch circuit in FIG.

FIG. 5 FIG. 1 at the time of interleaved high-speed access
3 is a time chart diagram showing the operation of FIG.

FIG. 6 is a block diagram showing a schematic configuration of a conventional IC test apparatus.

7 is a diagram showing a two-system bus configuration of the pattern generating means of FIG. 6 for generating expected value data by a memory stored method.

[Explanation of symbols]

71 ... Control means, 72 ... DC measurement means, 73 ... Timing generation means, 74 ... Pattern generation means, 75 ... Pin control means, 76 ... Pin electronics, 77 ... Fail memory, 78 ... Formatter, 79 ... Comparator logic, 7A ... Driver, 7B ... Comparator, 7C ... Tester bus, 7D ... IC mounting device, 7E ... IC to be measured, 1
1, 1C ... Flip-flop circuit, 12 ... Counter, 1
3 ... Address shifter, 14 ... Decoder, 15 ... Selection circuit, MUX0, MUX1, MUX2, MUX3, MUX
... multiplexer, 16, 17, 18, 19 ... latch circuit, 1B ... data shifter, 1D ... internal memory control means

Claims (2)

[Claims] 1. A desired test pattern is obtained by storing test pattern data to be supplied to a device under test in a pattern memory in advance according to a first clock and reading it in synchronization with a second clock. In a pattern generator of an IC test device for generating data, a counter that counts the second clock and outputs the count value, and a first counter that is generated in synchronization with the count value and the second clock. An address is input, the first address is shifted by a predetermined number of bits according to the interleave access method, and the count value is output from an empty bit generated by this shift processing to generate an interleave address and shift processing. A predetermined range of the read first address is output as the read address. An address shifter, a decoder for decoding the interleaving address from the address shifter and outputting a first selection signal, a second selection signal and a second address to be supplied to the pattern memory Memory control means for supplying the read / write control signal and the test pattern data to the pattern memory while being generated in synchronization with a clock, and the second address, the read address from the address shifter and the pattern memory. A plurality of multiplexers for inputting addresses, switching them according to the first and second selection signals, and outputting the latches; and latching the read addresses output from the multiplexers for outputting to the pattern memory and the multiplexers. Feedback to the input end of the second Pattern generator of the IC tester being characterized in that comprises a latch circuit which is controlled to output directly to the pattern memory without latching respect dresses. 2. The test pattern data output from the pattern memory according to an address other than the interleaving address and the read address among the first addresses output from the address shifter has a desired output bit width. The pattern generator of the IC test apparatus according to claim 1, further comprising a data shifter for performing shift processing so that