JPH0715297A - Clock signal reception circuit - Google Patents

Abstract

PURPOSE:To exactly receive a clock signal while ignoring noise even when an input impedance is kept high. CONSTITUTION:Concerning the high level part of the clock signal, a high level voltage detection circuit 2 defines it as an inverted signal to be made high at the time of being larger than a high threshold value (Vs-H) or to be made low at the time of being smaller than this threshold value and concerning the low level part of the clock signal, a low level voltage detection circuit 3 is defined it as an inverted signal to be made low at the time of exceeding a low threshold value (Vs-L) or to be made high at the time of being less than the threshold value. Inverted outputs from both the detection circuits 2 and 3 are inputted to a waveform shaping circuit 4, and the waveform is shaped both for a signal to rise by the first rising of the period of the inverted output from the high level voltage detection circuit 2 and for a signal to fall with the first rising of the inverted output from the low level voltage detection circuit 3. The high threshold value is defined as a value subtracting the voltage drop component (Vz) of a transmission line from the minimum value of the high level of the clock signal and the low threshold value is defined as a value adding the voltage drop component to the maximum of the low level of he clock signal.

Description

Detailed Description of the Invention

[0001]

The present invention relates to TTL (Transi)
Stor Transistor Logic) -IC
In (Integrated Circuit),
The present invention relates to a clock signal receiving circuit that receives a high frequency clock signal.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional clock signal receiving circuit. This circuit includes first and second transistors Tr1.
It has Tr2, and the base of the first transistor Tr1 is
It is connected to an input terminal IN for inputting a clock signal from a transmission line such as a cable or a wiring pattern, a collector is connected to an output terminal OUT, and emitters are resistors R1 and R, respectively.
It is connected via 2 to the base and collector of the second transistor Tr2. In addition, the second transistor Tr2
The emitter of is grounded. A constant voltage Vcc is applied to the collector of the first transistor Tr1 and the output terminal OUT via the resistor R3, and the transistors Tr1 and Tr2 are sequentially operated according to the clock signal, so that the edge of the clock signal is constant. The voltage Vcc is detected as a reference.

[0003]

Generally, the input impedance (several tens of KΩ) of the clock signal receiving circuit is much higher than the impedance of the transmission line (about 70 to 100Ω), and the transmission line and the clock signal receiving circuit have a high impedance. An impedance mismatch occurs between them. Therefore, when the waveform of the clock signal changes, reflection noise (wave undulation of the signal) occurs. In addition, noise is also generated by induction on the signal line, distortion of the power supply line, or the like. Therefore, in the conventional clock signal receiving circuit that detects the edge of the clock signal,
Even such noise is detected, that is, the edges of the clock signal are duplicated due to the noise, which causes a malfunction of the operation of the TTL-IC due to inaccurate reception of the clock signal.

Reflection noise can be reduced if the input impedance of the clock signal receiving circuit is made as small as possible or impedance matching is taken, but it is not sufficient.
In addition, mounting technology is difficult.

Therefore, an object of the present invention is to provide a clock signal receiving circuit capable of accurately receiving a clock signal while ignoring noise even if the input impedance remains high.

[0006]

The clock signal receiving circuit according to the present invention, as shown in FIG. 1, has a voltage drop amount of the transmission line from the minimum high level value (Vo-Hmin) of the clock signal from the transmission line. The value obtained by subtracting (Vz) is the threshold value (Vs
-H), a high level voltage detection circuit 2 that outputs an inverted signal that is high when the input clock signal is equal to or higher than this threshold value and is low when the input clock signal is lower than this threshold value, and the maximum value of the low level of the clock signal from the transmission line. A value obtained by adding a voltage drop amount (Vz) to (Vo-Lmax) is set as a threshold value (Vs-L),
Low when the input clock signal exceeds this threshold,
A low-level voltage detection circuit 3 that outputs an inversion signal that becomes high when the voltage is equal to or lower than this threshold, and is connected to the output sides of the high-level voltage detection circuit 2 and the low-level voltage detection circuit 3 to output the inverted output of the high-level voltage detection circuit 2. The low level voltage detection circuit 3 rises at the first rise of the cycle.
And a waveform shaping circuit 4 that outputs a signal that falls at the first rise of the inversion output period.

[0007]

In the present invention, the noise component mixed in the clock signal is removed in both the high level portion and the low level portion of the clock signal. Therefore, as shown in (1) of FIG. High and low thresholds (Vs-H) and (Vs-L) corresponding to each low level are set, and the high level and low level of each cycle of the clock signal are detected separately with reference to this. In this case, the voltage drop (Vz) due to the transmission line is obtained in advance from the circuit constant of the transmission line and the actual measurement value, and the high threshold value (Vs-H) is calculated from the minimum high level value (Vo-Hmin) of the clock signal. A value obtained by subtracting the voltage drop (Vz) is used, and a low threshold value (Vs-
L) is the maximum low level value of the clock signal (Vo-L
The value obtained by adding this voltage drop (Vz) to (max).

The reason why the voltage drop (Vz) is subtracted for the high threshold (Vs-H) and the voltage drop (Vz) is added for the low threshold (Vs-L) is as follows. That is, when the clock signal is at the high level, current flows from the transmission line to the clock signal receiving circuit, and the potential drops by the amount of the flowing current, but when the clock signal is at the low level, current is transmitted from the clock signal receiving circuit to the contrary. This is because the current flows out into the path and the potential becomes higher by the amount of the current.

With respect to the high level portion of the clock signal, the high level voltage detection circuit 2 makes it high when it is higher than a high threshold value (Vs-H) and is low when it is lower than this threshold value as shown in (2) of FIG. As an inversion signal, the low level portion of the clock signal is detected by the low level voltage detection circuit 3 as shown in (3) of FIG.
When it exceeds L), it is low, and when it is less than this threshold, it is high. Then, the inverted outputs from both the detection circuits are input to the waveform shaping circuit 4, and as shown in (4) of FIG. 2, the inverted output of the high-level voltage detection circuit 2 rises at the first rising of the cycle of the inverted output, and the low-level voltage. If the waveform is shaped into a signal that falls at the first rise of the inverted output cycle of the detection circuit 3, an accurate clock signal obtained by removing the noise component from the clock signal of FIG. 1A can be obtained.

[0010]

EXAMPLES Next, examples of the present invention will be described. In FIG. 1, a high level voltage detection circuit 2 and a low level voltage detection circuit 3 are connected in parallel to an input terminal 1 connected to a transmission line, and the waveform shaping circuit 4 is connected to the output terminals of both detection circuits 2 and 3. Both input terminals are connected, and the output terminal 5 is connected to the output terminal of the waveform shaping circuit 4.

Both the high-level voltage detection circuit 2 and the low-level voltage detection circuit 3 are composed of comparison circuits. The high-level voltage detection circuit 2 uses the clock signal input to the input terminal 1 as a high threshold voltage (high threshold voltage). Vs−H), the low level voltage detection circuit 3 compares the clock signal input to the input terminal 1 with a low threshold voltage (V) which is a low reference voltage.
s-L). For the high threshold value (Vs-H), the voltage drop (Vz) due to the transmission line is obtained in advance from the circuit constant of the transmission line, the actual measurement value, etc., and this voltage drop (Vz) is the minimum value of the high level of the clock signal ( Vo-Hmin). Further, the low threshold value (Vs-L) is a value obtained by adding the voltage drop amount (Vz) to the maximum value (Vo-Lmax) of the low level of the clock signal. The minimum high level value (Vo-Hmin) and the maximum low level value (Vo-Lmax) of the clock signal are values when there is no noise, and are also obtained from the actual measurement values.

The high-level voltage detection circuit 2 compares the clock signal as shown in (1) of FIG. 2 with a high threshold value (Vs-H), and as shown in (2) of FIG. An inversion signal that is high when the threshold voltage is higher than the threshold value (Vs-H) and low when the threshold voltage is lower than the threshold value (Vs-H) is output. Further, the low-level voltage detection circuit 3 compares the clock signal such as (1) with a low threshold value (Vs-L), so that the clock signal exceeds the threshold value (Vs-L) as shown in (3). An inversion signal that is low when it is low and high when this threshold value (Vs-L) or less is output.

The waveform shaping circuit 4 is set at the rising edge of the inverted output of the high level voltage detecting circuit 2 and then holds that state until it is reset at the rising edge of the inverted output of the low level voltage detecting circuit 3, for example RS. As shown in (4) of FIG. 2, it is constituted by a flip-flop circuit and rises at the first rising edge of the cycle of the inverted output of the high-level voltage detection circuit 2 and first rising edge of the cycle of the inverted output of the low-level voltage detection circuit 3. The signal that falls at is output. The output (4) of the waveform shaping circuit 4 has a waveform obtained by removing the noise component from the clock signal of (1).

[0014]

As described above, according to the present invention, for each of the high level and the low level of the clock signal, a high and low threshold value is set in consideration of the voltage drop due to the transmission line, and the clock signal of the clock signal is set on the basis of this threshold value. After the high level and low level of each cycle are detected separately, a new signal that combines these is shaped from the first rise of both detection outputs, so the noise component mixed in the clock signal is Both the high level part and the low level part can be removed. Therefore, an accurate clock signal that is not affected by noise can be obtained, and the TTL-I
The reliable operation of C can be guaranteed.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a clock signal receiving circuit according to the present invention.

FIG. 2 is an operation waveform diagram of the above.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 1 input terminal 2 high level voltage detection circuit 3 low level voltage detection circuit 4 waveform shaping circuit 5 output terminal

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[Procedure amendment]

[Submission date] November 2, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

The clock signal receiving circuit according to the present invention, as shown in FIG. 1, has a voltage drop amount of the transmission line from the minimum high level value (Vo-Hmin) of the clock signal from the transmission line. The value obtained by subtracting (Vz) is the threshold value (Vs
-H), a high level voltage detection circuit 2 that outputs an inverted signal that is high when the input clock signal is equal to or higher than this threshold value and is low when the input clock signal is lower than this threshold value, and the maximum value of the low level of the clock signal from the transmission line. A value obtained by adding a voltage drop amount (Vz) to (Vo-Lmax) is set as a threshold value (Vs-L),
Low when the input clock signal exceeds this threshold,
A low-level voltage detection circuit 3 that outputs an inversion signal that becomes high when the voltage is equal to or lower than this threshold, and is connected to the output sides of the high-level voltage detection circuit 2 and the low-level voltage detection circuit 3 to output the inverted output of the high-level voltage detection circuit 2. The low level voltage detection circuit 3 rises at the first rise of the cycle.
And a waveform shaping circuit 4 that outputs a signal that falls at the first rise of the inversion output period. This waveform adjustment
Form circuit is composed of, for example, an RS flip-flop circuit.
You can

Claims (1)

[Claims] 1. A T for receiving a clock signal from a transmission line.
In a clock signal receiving circuit for a TL-IC, a voltage drop (Vz) from a high level minimum value (Vo-Hmin) of a clock signal from the transmission line to the transmission line.
A high level voltage detection circuit that outputs an inverted signal that is high when the input clock signal is equal to or higher than this threshold value and is low when the input clock signal is lower than this threshold value; The threshold value (Vs-L) is a value obtained by adding the voltage drop amount (Vz) to the maximum low level value (Vo-Lmax) of the clock signal, and when the input clock signal exceeds this threshold value, the threshold value is low. It is connected to the output side of the low level voltage detection circuit and the low level voltage detection circuit that outputs an inverted signal that becomes high in the following cases, and it is connected to the output side of these high level voltage detection circuit and the first rising edge of the inverted output cycle of the high level voltage detection circuit. A waveform shaping circuit that outputs a signal that rises and falls at the first rise of the inverted output cycle of the low-level voltage detection circuit; and The clock signal reception circuit.