JPH07161808A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To restrain a defect from being caused and to reduce the concentration of an electric field by a method wherein the corner part of a trench groove is formed to be at a gentler angle and the concentration of a stress in the corner part is reduced remarkably. CONSTITUTION:A substrate by a material having the face anisotropy of solubility is used as a semiconductor substrate 301. A groove 308 for element isolation is formed on the semiconductor substrate 301. After that, by utilizing the face anisotropy of the solubility by the semiconductor substrate 301, the angle of a corner part at the groove 308 is relaxed by a wet etching operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as an LSI.

[0002]

2. Description of the Related Art In recent years, along with the miniaturization of semiconductor devices, a trench method has been used as an element isolation method suitable for miniaturization.

3A to 3E are views showing an example of the trench method. In the trench method, first, a pad oxide film 102 is formed on a silicon substrate 101, an insulating film 103 is formed on the pad oxide film 102 to a thickness sufficient to function as a mask for silicon etching, and a resist pattern 104 is formed. After forming, the insulating film in the portion corresponding to the isolation region is removed by ordinary photolithography and etching. As a result, a region (element isolation region) 110 from which the insulating film has been removed is formed (FIG. 3A).

Next, reactive ion etching is performed on the silicon exposed in the region (element isolation region) 110 from which the insulating film has been removed to form a trench 105 to be a trench. Furthermore, in this state, impurity ions of the same conductivity type as the silicon substrate are implanted as a channel stopper 106 for reducing the parasitic MOS effect (FIG. 3).
(b)). Next, the insulating film 107 is formed to a predetermined thickness on the entire surface of the groove 105 (FIG. 3C). The insulating film 10
7 is formed to protect and embed the groove 105. Then, a polycrystalline silicon film 108 is formed to completely fill the trench 105 (FIG. 3D). Then, the surface of the substrate is flattened by etching the polycrystalline silicon film or the insulating film on the substrate 101 by the film thickness (FIG. 3).
(e)).

[0005]

However, in the above-mentioned method, as shown in FIG. 3C, the insulating film 10 intended to protect and fill the narrow groove 105 is formed.
When forming 7, the stress due to the formation of the insulating film 107 concentrates on the corners of the groove 5, so that defects 109 occur at the corners, resulting in a problem that the element characteristics are greatly impaired.

In order to solve the problem in such a trench method, for example, in Japanese Examined Patent Publication (Kokoku) No. 4-23422, after forming a groove in a semiconductor substrate, a polycrystalline semiconductor film (for example, a polycrystal A silicon film) and oxidize the semiconductor substrate through this polycrystalline semiconductor film to round the boundary surface between the oxide film and the semiconductor substrate, and then peel off the formed oxide film and round the corners of the groove. After
A technique for forming an element isolation region is shown.

In this technique, the corner of the groove of the semiconductor substrate is roundly covered with the polycrystalline semiconductor film, so that the corner of the groove is rounded, and when the oxide film is formed in the groove, the groove is rounded. The concentration of stress on the corners of the is reduced, and the occurrence of defects is suppressed.

However, in the above rounding treatment, when the polycrystalline semiconductor film is thickened, an increase in the oxide film at the time of rounding oxidation and a reduction in the curvature of the groove bottom occur, and defects easily occur at the time of rounding oxidation. There was a problem. In other words, in the above rounding process, the roundness (curvature) of the corner portion of the groove varies depending on the thickness of the polycrystalline semiconductor film, and when the polycrystalline semiconductor film is formed thinly, the corner portion of the groove is sufficiently rounded. Roundness
It is difficult to provide (curvature), and stress concentration at corners cannot be reduced reliably and reliably.

According to the present invention, it is possible to form the corner portion of the trench groove at a gentler angle, remarkably reduce the stress concentration on the corner portion, suppress the generation of defects, and reduce the concentration of the electric field. It is an object to provide a method for manufacturing a semiconductor device.

[0010]

In order to achieve the above object, the present invention uses, as a semiconductor substrate, a substrate made of a semiconductor material having a plane anisotropy of solubility, and the semiconductor substrate is provided with a groove for element isolation. A groove forming step of forming the groove and a step of relaxing the angle of the corner portion of the groove by wet etching are performed after utilizing the surface anisotropy of the solubility of the semiconductor substrate after forming the groove. As a result, the stress concentration on the corners of the groove can be further reduced, the occurrence of defects can be suppressed, and the concentration of the electric field can be reduced as compared with the conventional case.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (e) and 2 (a) to 2 (d) are views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.
In this embodiment, as a semiconductor substrate, (10
A silicon substrate having a (0) plane is used, and the corner portion of the groove is formed at a gentle angle by etching by utilizing the surface anisotropy of the solubility of the silicon substrate.

That is, referring to FIGS. 1A to 1E and 2A to 2D, in this embodiment, first, the surface of an n-type (or p-type) silicon substrate 301 is protected. In order to do so, the pad oxide film 302 is formed to a thickness of about 50 mm. Further, a silicon nitride film 303 is formed as an oxidation resistant film on the pad oxide film 302 by a method such as CVD,
Further, a first BPSG film for forming a sidewall
A (passivation film) 304 is formed by the LP-CVD method. After that, a photoresist is applied, and the photoresist in a portion to be an element isolation region is removed through a normal photographic process. Then, etching is performed using the patterned photoresist as a mask to remove the silicon nitride film 303 and the pad oxide film 302, thereby forming an element isolation region 312 (FIG. 1A).

Then, a second silicon nitride film 305 is formed on the entire surface of the substrate by a CVD method in order to form a trench for element isolation. Further, the second silicon nitride film 30
A BPSG film 306 necessary for forming the sidewall 307 is formed on the film 5 by the LP-CVD method (FIG. 1B).

Next, by reactive ion etching, up to the region where the second silicon nitride film 305 disappears,
Etch back is performed to form sidewalls 307 (FIG. 1C).

Thereafter, reactive ion etching is performed using the sidewalls 307 and the first BPSG film 304 as a mask to form the element isolation trench 308 (FIG. 1D). Further, in order to reduce the parasitic MOS effect in this state, an impurity (n-type impurity (or p-type impurity)) 309 of the same type as the silicon substrate 301 is implanted as a channel stopper by using an ion implantation device, and then, The sidewalls 307, the first BPSG film 304 and the first silicon nitride film 303 are sequentially removed by selective etching (FIG. 1 (e)).

Next, using the pad oxide film 302 as a mask, the silicon substrate 301 exposed in the element isolation region 312 is etched by an alkaline etching solution such as a potassium hydroxide solution. At this time, the etching is performed by (11) due to the plane anisotropy of the solubility of the silicon substrate.
1) Along the plane, the reaction stops when it reaches a depth determined by the pad oxide film 302 (FIG. 2).
(a)). Angle θ of the part to be cut by this etching
Is about 54 degrees with respect to the (100) plane of the silicon substrate 301, which relaxes the angle of the corner portion of the groove 308, as can be seen from FIG.

Next, in order to reduce damage to the silicon substrate 301, the silicon substrate is heated in a steam atmosphere to form a protective oxide film 310 on the surface of the silicon substrate 301 to a thickness of about 40 mm (FIG. 2). (b)). After that,
A BPSG film 311 for completely filling the groove 308 is formed on the protective oxide film 310 by using the LP-CVD method.
The BPSG film 311 is formed to a thickness of about 00 mm, and then subjected to a high temperature heat treatment at about 1000 ° C. in a nitrogen atmosphere.
Is reflowed to flatten the surface (FIG. 2 (c)).

Finally, the BPS remaining in the element formation region
The G film 311 is removed by etch back (see FIG. 2).
(d)). In this state, a device can be formed on the element formation region.

As described above, in this embodiment, it is possible to form a gentle angle (tilt) at the corner of the isolation trench formed on the silicon substrate without causing defects. Further, since wet etching is used to provide the inclination, stress is less likely to occur, and therefore deterioration of the electrical characteristics of the device can be prevented very effectively during device formation. Further, it is possible to reduce the concentration of the electric field at the corners.

Further, by performing the etching back after the flattening, the flatness of the substrate surface is improved, and the photolithography in the device manufacturing process is facilitated. Further, since there are few steps, it is possible to improve the reliability of the wiring and the like.

The above-mentioned embodiment is merely an example, and the present invention is not limited to this embodiment. For example, although the silicon substrate is used as the substrate in the above-described embodiments, any substrate other than the silicon substrate may be used as long as it is a substrate made of a semiconductor material having plane anisotropy of solubility.

[0022]

As described above, according to the present invention, a semiconductor material substrate having a plane anisotropy of solubility is used as a semiconductor substrate, and a groove for element isolation is formed in the semiconductor substrate. Since the forming step and, after forming the groove, the surface anisotropy of the solubility of the semiconductor substrate is used and the angle of the corner portion of the groove is relaxed by wet etching, the step of relaxing the angle is performed. It is possible to further reduce the stress concentration on the corners of the groove, suppress the occurrence of defects, and reduce the concentration of the electric field.

[Brief description of drawings]

1A to 1E are views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

2A to 2D are views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

3A to 3E are views showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 301 Silicon substrate 302 Pad oxide film 303 Silicon nitride film 304 First BPSG film 305 Second silicon nitride film 307 Sidewall 308 Device isolation groove 310 Protective oxide film 311 BPSG film 312 Device isolation region

Claims (5)

[Claims] 1. A semiconductor substrate that is a semiconductor material having a plane anisotropy of solubility is used as a semiconductor substrate, and a groove forming step of forming a groove for element isolation in the semiconductor substrate and the semiconductor substrate after the groove is formed. Utilizing the surface anisotropy of the solubility of, and an angle relaxation step of relaxing the angle of the corner portion of the groove by wet etching. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the groove forming step includes a step of forming a protective film for protecting the surface of the semiconductor substrate, and a step of etching a part of the protective film. The step of forming the element isolation region, the step of forming sidewalls on both sides of the element isolation region, and the region between the sidewalls formed on both sides of the element isolation region are etched to isolate the element on the semiconductor substrate. A step of forming a groove, and the angle loosening step includes a step of removing the sidewall, and a step of removing the sidewall and then performing wet etching using the protective film as a mask. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, further comprising, after relaxing an angle of a corner portion of the groove, filling the groove, flattening the surface, and flattening the surface. Then, a method of manufacturing a semiconductor device, which comprises a step of performing etch back and a step of forming a device in an element formation region. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming the element isolation groove and then implanting an impurity functioning as a channel stopper into the groove. And a method for manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is (100) on an element formation surface.
A method of manufacturing a semiconductor device, wherein a silicon substrate having a surface and wet etching proceeds along a (111) surface is used.