JPH07191347A - Method of manufacturing thin film transistor array - Google Patents

Abstract

(57) [Abstract] [Purpose] A thin film transistor with a good yield by etching the surface of the silicon nitride film for gate insulation, which is the underlying film after the processing of the source / drain electrodes, smoothly, while using a fluorocarbon control gas. An array manufacturing method is provided. A gate electrode 22 is formed on an insulating transparent substrate 21, a gate insulating silicon nitride film 23 of the gate electrode 22 is formed, and the gate insulating silicon nitride film 23 is formed.
A step of forming the blocking layer 25 on the n ⁻ amorphous silicon film 24, a step of forming the n ⁺ amorphous silicon film 26 and the Cr film 27, and the Cr film 27.
Is processed by dry etching using a mixed gas of chlorine and helium to form the upper source / drain electrodes 27a and 27b, and the n ⁺ amorphous silicon film 26.
And the n ^- amorphous silicon film 24 are processed by dry etching using a mixed gas of chlorine and helium, and a step of forming a source / drain contact layer is sequentially performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (AML).
More particularly, the present invention relates to a method of manufacturing a thin film transistor array for an active matrix type liquid crystal display device capable of reducing irregularities of a base film after processing.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. 6 and 7
FIG. 4A is a sectional view of a manufacturing process of a thin film transistor array of a conventional active matrix type liquid crystal display device.

First, as shown in FIG. 6A, a gate electrode 12 is formed on an insulating transparent substrate 11 such as a glass substrate by using an electrode film such as Al or Cr, and then plasma C is formed.
By the VD method, the gate insulating silicon nitride film 13 and the non-doped amorphous silicon film (n ^- a-S)
i film) 14 and blocking silicon nitride film 15 are continuously formed.

Next, a blocking silicon nitride film (S
The iN film) 15 is processed to form a blocking silicon nitride film 15a in the channel portion as shown in FIG. 6B. After that, as shown in FIG. 6C, the n ⁺ a-Si film 16 and the Cr film 17 are continuously formed as ohmic electrodes. After that, the Cr film 17 is processed to form a source electrode 17a and a drain electrode 17b made of a Cr film, as shown in FIG. 7 (A).

Further, the n ⁺ a-Si film 16 and the n ^- a-S film are formed.
The i film 14 is processed, and as shown in FIG. 7B, n ^{+ a} −
Contact layers 16a and 16b made of the Si film 16 are formed. That is, the source electrode 17a and the drain electrode 17b
The source electrodes 17a and the drain electrodes 17b are electrically separated by leaving the contact layers 16a and 16b only in the lower layer and etching away the other portions.

After that, as shown in FIG. 7C, the pixel electrode 18, the source electrode metal 19a, and the drain electrode wiring 1 are formed.
9b is formed and a surface protective film is formed to obtain a thin film transistor for a liquid crystal display device. In the conventional manufacturing process described above, in the source and drain electrode forming process, a mixed gas of CFC ₄ or another CFC gas and oxygen is used for etching Cr, and the subsequent etching of the silicon film is performed by CCl 4.
It was performed in the RIE (reactive ion etching) mode using a mixed gas of ₄ and He.

[0007]

However, as a part of the recent global environmental protection activities, the CCl ₄ gas that has been conventionally used cannot be used after the end of 1995, and so-called CFC-less etching gas is used. It became necessary to switch to the process used (CFC-less process).

Then, as a new gas system replacing CCl ₄ , for example, a mixed gas of sulfur hexafluoride and hydrochloric acid has been studied. In addition, measures such as wet etching of the Cr film are taken. However, using the CFC-less gas system as described above, as shown in FIG.
When the process shown in Fig. 3 is performed, the phenomenon that the surface of the silicon nitride film for gate insulation after the source / drain electrodes are etched becomes uneven, and the sheet resistance value of the ITO transparent electrode that is formed thereafter becomes high. The wet etching method results in a reduction in manufacturing yield of the thin film transistor array for a liquid crystal display device, such as a residue remaining after the wet etching.

The present invention eliminates the above problems,
To provide a method for manufacturing a thin film transistor array with a good yield by smoothly etching the surface of a silicon nitride film for gate insulation, which is a base film after processing a source / drain electrode, using a CFC regulating gas. .

[0010]

In order to achieve the above object, the present invention provides a thin film transistor and a source electrode of the thin film transistor at each intersection of a plurality of address wirings and a plurality of data wirings which are arranged to intersect with each other. A thin film transistor array in which a plurality of display electrodes connected to one of the drain electrodes are arranged in a matrix, and the address wiring is connected to the gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode. In the method for manufacturing the same, after forming a gate electrode on an insulating transparent substrate, a gate insulating silicon nitride film of the gate electrode is formed, and an n ^- amorphous silicon film containing no impurities is formed on the gate insulating silicon nitride film. And a step of forming a blocking layer via the semiconductor film, A step of forming an n ⁺ amorphous silicon film and the Cr film on a substrate, the step of the Cr film fluorine is patterned by dry etching using a non-chlorofluorocarbon-based gas that is not contained, to form the upper layer source and drain electrodes And the n ⁺ amorphous silicon film and n
^- and wherein the patterned by dry etching using a non-chlorofluorocarbon-based gas without an amorphous silicon film containing fluorine, to form a semiconductor element region, and a step of electrically separating the source and drain electrodes To do.

The Cr film is etched with an etching gas containing at least chlorine gas. For example, a mixed gas of chlorine and oxygen or chlorine, oxygen and helium gas is used. Further, the n ⁺ amorphous silicon film and the semiconductor film are etched with an etching gas containing chlorine gas.
For example, chlorine alone or a mixed gas of chlorine and helium gas is used.

Further, the etching of the n ⁺ amorphous silicon film and the semiconductor film is performed in the RIE mode.

[0013]

According to the present invention, since the non-fluorocarbon-based etching gas containing no fluorine is used for the etching of the Cr film and the silicon film, the fluorocarbon-free source gas is used.
The surface of the gate insulating silicon nitride film, which is the base film after the processing of the drain electrode, can be etched smoothly. Therefore, an ITO film having a low sheet resistance can be formed, and a thin film transistor array can be manufactured with a high yield.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a sectional view of a thin film transistor array manufacturing process showing an embodiment of the present invention (No. 1), FIG. 2 is a sectional view of a manufacturing process of the thin film transistor array (No. 2), FIG. 3 is a plan view of the thin film transistor array,
FIG. 4 is a sectional view of the thin film transistor array.

Here, in the TFT array, as shown in FIG. 3, a plurality of address wirings 22a and data wirings 29c intersect each other at right angles on the insulating transparent substrate such as glass in the row direction and the column direction. A plurality of thin film transistors in which the gate electrode 22 is connected to the address wiring 22a and the drain electrode wiring 29b is connected to the data wiring 29c are arranged at each intersection of the address wiring 22a and the data wiring 29c. A plurality of pixel electrodes 28 made of an ITO film connected to the source electrode wiring 29a of the thin film transistor are arranged in a matrix.

Hereinafter, a method of manufacturing a thin film transistor array showing an embodiment of the present invention will be described with reference to FIGS. (1) First, as in the conventional process, as shown in FIG. 1 (A), A is formed on an insulating transparent substrate 21 such as a glass substrate.
The gate electrode 22 made of Al, Al-based alloy, Ta, Ta alloy, Cr or the like is formed by sputtering and a predetermined processing method.

Next, a silicon nitride film for gate insulation (Si
An N film) 23 is formed, and an undoped impurity n ^- a-Si (hydrogenated amorphous silicon) film 24 and a silicon nitride film 25, which will be semiconductor layers, are continuously formed thereon by plasma CVD. (2) Next, as shown in FIG. 1B, the silicon nitride film 25 is processed into a predetermined shape to form a blocking silicon nitride film 25a in the channel portion.

(3) Next, as shown in FIG. 1C, n ⁺ a doped with an n-type impurity is used as an ohmic electrode.
-Si film 26 and Cr film 27 are continuously formed. (4) Next, the Cr film 27 is processed by dry etching using a mixed gas of Cl ₂ and O ₂ , which is a chlorine-based non-fluorocarbon gas that does not contain fluorine, as shown in FIG. A source electrode 27a and a drain electrode 2 made of a Cr film.
7b is formed.

[0019] (5) In addition, n ⁺ a-Si film 26 and the n ^-
The a-Si film 24 is processed by dry etching using a mixed gas of Cl ₂ and He is a non-chlorofluorocarbon-based gas chlorine system containing no fluorine, as shown in FIG. 2 (B), n ⁺
A source contact layer 26a and a drain contact layer 26b made of an a-Si film are formed. That is, only the source contact layer 26a, the source electrode 27a and the drain contact layer 26b, the drain electrode 27b are left, and the other portions are removed by etching to remove the source electrode 27.
a and the drain electrode 27b are electrically separated. Then, subsequently, the pixel electrode 28 is formed on the gate insulating film.

(6) After that, as shown in FIG.
The pixel electrode 28, the source electrode metal 29a, the drain electrode wiring 29b are formed, and the surface protection film 30 (see FIG. 4) is formed to obtain a thin film transistor array. The etching of Cr and the etching of the n ⁺ -a-Si film are performed by using a dry etching apparatus as shown in FIG.

FIG. 5 is a configuration diagram of a parallel plate type dry etching apparatus showing an embodiment of the present invention, and FIG. 5A is a configuration of a parallel plate type dry etching apparatus for the RIE (reactive ion etching). Figure, Figure 5 (B) shows the PE
It is a block diagram of the parallel plate type dry etching apparatus for (isotropic ion etching). 5A and FIG.
As shown in (B), the substrate 40 on which the thin film transistor array of the present invention is formed is placed on the lower electrode 42,
RF power of 30 kHz to 13.56 MHz is applied between the upper electrode 41 and the upper electrode 41. The etching gas pressure is changed depending on the mode, and is 0.2 Torr and 0.
It was fixed at 1 Torr. The total flow rate of the etching gas was set in the range of 150 SCCM to 400 SCCM, and the RF power was set in the range of 1.3 to 2.0 KW.

(1) First, in the etching of the Cr film
Cl as an etching gas₂And O ₂Mixed gas with
Gas pressure of 0.3 Torr and gas flow rate of
480/120 (SCCM / SCCM), RF power
1.8 kW, PE (isotropic ion etching) mode
The gap between the upper and lower electrodes to 100 mm
It was set and etched.

As described above, the etching of the Cr film is performed using chlorine.
A mixture of oxygen and oxygen for all samples.
The amount of ching was the same. (2) Also, in the Cr film etching, etching
Cl as gas₂/ O ₂/ He mixed gas
Pressure of 0.1 Torr and gas flow rate of 100 /
100/200 (SCCM / SCCM / SCCM), R
F power is set to 1.8 kW and RIE (reactive ion etch
(Etching) or PE (isotropic ion etching) mode
The gap between the upper and lower electrodes to 100 mm.
And etching was performed. For any of the above etching
Even if the entire surface of the substrate is etched,
It was

(3) Next, in etching the silicon film (n ⁺ a-Si film and n ^- a-Si film), Cl ₂ / BCl ₃ / He (chlorine + boron trichloride + helium) was used as an etching gas. Mixed gas is used and the gas pressure is 0.1
Torr and gas flow rate are 10/50/240 (S
CCM / SCCM / SCCM), RF power 1.3K
Etching was performed in the RIE mode with W set to 100 mm for the gap between the upper electrode and the lower electrode. As a result, the unevenness of the underlying silicon nitride film was in the range of 10 to 20Å, and a smooth surface was obtained to the extent that the resistance value of ITO was not increased.

(4) In etching the silicon film (n ⁺ a-Si film and n ⁻ a-Si film), Cl ₂ gas is used as an etching gas and the gas pressure is 0.1 To.
rr, the gas flow rate was 300 (SCCM), the RF power was 1.8 KW, and the gap between the upper electrode and the lower electrode was set to 100 mm in the RIE mode. As a result, the unevenness of the underlying silicon nitride film was found. Is 10 to 20
It was Å.

(5) Further, a silicon film (n ⁺ a-Si)
In the etching of the film and the n ^- a-Si film), a mixed gas of Cl ₂ / He is used as an etching gas, the gas pressure is 0.1 Torr, and the gas flow rate is 60/240, respectively.
(SCCM / SCCM), RF power was 1.5 kW, and etching was performed in the RIE mode with the gap between the upper electrode and the lower electrode set to 100 mm. As a result, the unevenness of the underlying silicon nitride film was 10 to 10. It was 20Å.

Furthermore, chlorine + silicon tetrachloride + helium (Cl ₂ / SiCl ₄ / H) is used as an etching gas.
The smoothness of the underlying silicon nitride film was also good when etching was performed using the mixed gas consisting of e). As described above, since the chlorine-based non-freon-based gas containing no fluorine is used as the etching gas, the n ⁺ -a-Si film and the n ^-- a film are not impaired without impairing the smoothness of the underlying silicon nitride film. -Si film can be etched.
Further, even if these etching gases leak to the outside air, environmental damage is not caused. Considering the smoothness of the underlying silicon film, it is preferable to use chlorine gas or a mixed gas of chlorine helium among the above etching gases.

The RF power and the like in each of the dry etchings described above may be set according to the etching rate.
Even if the F power is changed, the same underlying film surface as in the above dry etching can be obtained. (6) In contrast to the above embodiment, SF is used as an etching gas.
_{Using 6} / HCl mixed gas, the gas pressure is 0.1 Tor.
r and gas flow rate 100/30 (SCCM / SC
CM), RF power was 1.3 kW, and etching was performed in RIE (reactive ion etching) mode with the gap between the upper electrode and the lower electrode set to 100 mm. As a result, the surface of the underlying silicon nitride film has 10 irregularities.
A rough surface of 00 Å or more was not obtained, and a smooth surface was not obtained.

The surface roughness of the underlying silicon nitride film was evaluated by forming an ITO transparent electrode film of about 500 liters on the silicon etching surface and measuring the sheet resistance value thereof. That is, the larger the unevenness of the surface of the underlying silicon nitride film, the larger the sheet resistance value. In addition, when the Cr film is etched by the wet etching method and then the silicon film is dry-etched with a chlorine-based CFC, it is difficult to uniformly etch the silicon film over the entire surface of the substrate. The silicon film remained locally. In particular, when L / S (line & space) is small, it easily occurs, and it has been difficult to perform wet etching for the Cr film.

It is needless to say that the source electrode and the drain electrode in the above embodiments can be replaced with the drain electrode and the source electrode, respectively. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0031]

As described above in detail, according to the present invention, the Cr film and the silicon film are etched by using a non-CFC-based etching gas while keeping the smoothness of the base film good. Since dry etching can be performed and the base film is smooth, an ITO film having a low sheet resistance can be formed and a thin film transistor array can be obtained with a high yield.

Since the etching gas used in the present invention is a non-CFC type gas, the environment will not be destroyed even if this gas leaks.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) of a manufacturing process of a thin film transistor array showing an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) of a manufacturing process of the thin film transistor array showing the embodiment of the present invention.

FIG. 3 is a plan view of a thin film transistor array showing an embodiment of the present invention.

FIG. 4 is a sectional view of a thin film transistor array showing an embodiment of the present invention.

FIG. 5 is a configuration diagram of a parallel plate type dry etching apparatus showing an embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process of a thin film transistor array of a conventional active matrix type liquid crystal display device (Part 1).
Is.

FIG. 7 is a manufacturing process sectional view of a thin film transistor array of a conventional active matrix type liquid crystal display device (Part 2).
Is.

[Explanation of symbols]

21 Insulating Transparent Substrate 22 Gate Electrode 22a Address Wiring 23 Gate Insulating Silicon Nitride Film (SiN Film) 24 n ^- a-Si (Amorphous Silicon) Film 25 Silicon Nitride Film 25a Blocking Silicon Nitride Film 26 n ⁺ a-Si Film 26a Source Contact Layer 26b Drain Contact Layer 27 Cr Film 27a Source Electrode 27b Drain Electrode 28 Pixel Electrode (ITO Film) 29a Source Electrode Metal 29b Drain Electrode Wiring 29c Data Wiring 30 Surface Protection Film 40 Substrate 41 Upper Electrode 42 Lower Electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromitsu Ishii 2951-5 Ishikawa-cho, Hachioji-shi, Tokyo Casio Computer Co., Ltd. Hachioji Research Center

Claims (6)

[Claims] 1. A matrix of a thin film transistor and a display electrode connected to any one of a source electrode and a drain electrode of the thin film transistor at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other. In a method of manufacturing a thin film transistor array in which a plurality of gate electrodes of the thin film transistor are connected to the address wiring, and the other of the source electrode and the drain electrode is connected to the data wiring, a gate electrode is formed on an insulating transparent substrate. Is formed, a gate insulating silicon nitride film of the gate electrode is formed, and a semiconductor film made of an n ^- amorphous silicon film containing no impurities is formed on the gate insulating silicon nitride film. forming a blocking layer Te, and (b) n ⁺ amorphous silicon film on the substrate a step of forming a r film, a step of patterning by dry etching to form the source and drain electrodes using a non-chlorofluorocarbon-based gas not containing fluorine and (c) the Cr film, (d) the n ⁺ A step of patterning the amorphous silicon film and the n ^- amorphous silicon film by dry etching using a non-fluorocarbon gas containing no fluorine to form a semiconductor element region and electrically separating the source / drain electrodes; A method of manufacturing a thin film transistor array, comprising: 2. The method of manufacturing a thin film transistor array according to claim 1, wherein the Cr film is etched with an etching gas containing at least chlorine gas. 3. The etching gas is a mixed gas of chlorine and oxygen or chlorine, oxygen and helium gas.
A method of manufacturing the thin film transistor array described. 4. The method of manufacturing a thin film transistor array according to claim 1, wherein the n ⁺ amorphous silicon film and the semiconductor film are etched with an etching gas containing chlorine gas. 5. The method of manufacturing a thin film transistor array according to claim 4, wherein the etching gas is chlorine or a mixed gas of chlorine and helium gas. 6. The method of manufacturing a thin film transistor array according to claim 4, wherein the n ⁺ amorphous silicon film and the semiconductor film are etched in a RIE mode.