JPH0720487A - Liquid crystal display element - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent deterioration of conductive connection between the upper transparent conductive film formed on the upper transparent substrate and the terminal electrode film formed on the lower transparent substrate. A color filter FIL (G, G, G) is formed under the upper transparent conductive film ITO2 with a conductive adhesive CM interposed.
The dummy color filter pattern FIL (C) formed at the time of patterning any of (B, R) was provided. [Effect] It is possible to prevent connection failure and disconnection due to environmental changes of the conductive adhesive that conductively connects the common conductive film formed on the upper transparent substrate and the terminal electrode film formed on the lower transparent substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color liquid crystal display device, and more particularly to a conductive connection failure with a terminal electrode film formed on an upper transparent conductive film and a lower transparent substrate formed on an upper transparent substrate with a conductive adhesive. The present invention relates to a resolved liquid crystal display element.

[0002]

2. Description of the Related Art Various types of liquid crystal display elements are known. Among them, a liquid crystal display device called an active matrix type corresponds to a plurality of pixel electrodes arranged in a matrix. A non-linear element (switching element) is provided, and a drive signal is applied to each pixel to display an image.

In the active system, the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), and the contrast is better than that in the so-called simple matrix system which employs the time-division drive system, which is particularly important in a color liquid crystal display device. Technology is becoming impossible. A typical example of this switching element is a thin film transistor (TFT).

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-309921, "1.
2.5-inch active matrix color LCD ", Nikkei Electronics, pages 193-210, 1986 12
Known on the 15th of March, published by Nikkei McGraw-Hill, Inc.

[0005]

In the above-mentioned conventional color liquid crystal display element, a plurality of color filters are formed on the upper transparent conductive film and the upper transparent conductive film which cover the color filters to form a common electrode. An upper transparent substrate having at least an upper alignment film, a lower transparent conductive film forming an individual electrode corresponding to a color filter, a terminal electrode film connected to the upper transparent conductive film, and a lower alignment film formed on the lower transparent conductive film. A liquid crystal is injected into a gap between the upper transparent conductive film and the lower transparent conductive film, and a lower transparent substrate having at least is provided between the upper transparent conductive film of the upper transparent substrate and the terminal electrode film of the lower transparent substrate. The liquid crystal injected between the upper transparent substrate and the lower transparent substrate is sealed with a sealant with a conductive adhesive intervening therebetween being interposed.

In such a structure, the conductive adhesive for conductively connecting the upper transparent conductive film of the upper transparent substrate to the terminal electrode film of the lower transparent substrate is arranged at the corners of the upper and lower substrates. The conductive adhesive has a thermosetting epoxy resin-based adhesive or the like as a base material, and a conductive material such as nickel powder or silver particles in an amount of about 20 to 50 vol% is mixed therein, and the base material has a high cohesive force. Therefore, changes in physical properties such as expansion and contraction due to changes in temperature and changes in humidity are small.

On the other hand, since the sealing material uses a thermosetting epoxy adhesive or the like as it is, the sealing material retains relatively flexibility and the above-mentioned change in physical properties is larger than that of the conductive adhesive. Therefore, the liquid crystal expands due to temperature changes and humidity changes, or due to the expansion and contraction of the upper and lower transparent substrates, etc.
The connectivity between the conductive adhesive and the upper transparent conductive film formed on the upper transparent substrate or the terminal electrode film formed on the lower transparent substrate deteriorates, resulting in an increase in resistance and deterioration of display quality. However, there is a problem that it causes a disconnection and causes defective lighting.

An object of the present invention is to solve the above-mentioned problems of the prior art and to prevent deterioration of conductive connection between the upper transparent conductive film formed on the upper transparent substrate and the terminal electrode film formed on the lower transparent substrate. It is to provide a liquid crystal display device of high quality and high reliability that has been lost.

[0009]

In order to achieve the above object, the present invention provides a color filter FIL (G, G,
B, R) and the color filters FIL (G,
(B, R) to form a common electrode and form an upper transparent conductive film IT
Upper transparent substrate SUB2 having at least O2 and an upper alignment film ORI2 formed on the upper transparent conductive film ITO2
And on the lower transparent conductive film ITO1 and the terminal electrode film ITO connected to the lower transparent conductive film ITO1 and the upper transparent conductive film ITO2 which form the individual electrodes corresponding to the color filters FIL (G, B, R). Formed lower alignment film ORI
Of the lower transparent substrate SUB1 having at least 1, the liquid crystal LC injected into the gap between the upper transparent conductive film ITO2 and the lower transparent conductive film ITO1, and the upper transparent conductive film ITO2 of the upper transparent substrate SUB2 and the lower transparent substrate SUB1. And a conductive adhesive CM interposed between the terminal electrode film ITO and the terminal electrode film ITO to electrically connect the two, and seals the liquid crystal LC injected between the upper transparent substrate SUB2 and the lower transparent substrate SUB1. In the liquid crystal display element including the sealing material SL that stops, the upper transparent conductive film ITO with the conductive adhesive CM interposed.
2 has a dummy color filter pattern FIL (C) formed at the time of patterning any one of the color filters FIL (G, B, R) in the lower layer.

Needless to say, the present invention can be applied not only to a TFT type liquid crystal display element but also to a simple matrix type liquid crystal display element and other color liquid crystal displays, and is not limited to color and a monochrome liquid crystal. It can also be applied to a display element. In that case, a thin film having the same function as a dummy color frame pattern is formed at a required position.

[0011]

With the above-described structure of the present invention, the conductive adhesive CM uses the dummy color filter pattern as a mechanical cushioning material to form the conductive adhesive CM in the upper transparent substrate SUB2 and the lower transparent substrate SUB.
Even if the gap between the upper transparent substrate SUB2 and the lower transparent substrate SUB1 changes due to environmental changes such as changes in temperature and humidity, the conductive connection is ensured. .

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a plan view of an essential part of an upper transparent substrate for explaining an embodiment of a liquid crystal display device according to the present invention, and FIG. 2 is a partial cross-sectional view including a lower transparent substrate taken along the line AA 'of FIG. is there.

In each figure, SUB1 is a lower transparent substrate, SUB2 is an upper transparent substrate, BM is a black matrix, FIL (G, B, R) is a color filter, and FIL.
(C) is a dummy color filter pattern, ITO1, I
TO2 is a transparent conductive film, ITO is a terminal electrode film, PSV is a protective film, ORI1 is an upper alignment film, ORI2 is a lower alignment film,
SL is a sealing material, CM (AGP) is a conductive adhesive, TF
T is a thin film transistor, LC is a liquid crystal, POL1 is an upper polarizing plate, and POL2 is a lower polarizing plate.

Upper transparent substrate SU made of transparent glass plate
A black matrix BM is formed on B2 to prevent photoconducting of TFTs and color mixing of color filters. The black matrix BM is formed by using a material such as chromium or an organic black film to selectively remove the pixel portion by a photolithography method. On this black matrix BM, three color filters FI
L (G, B, R) is formed.

Further, the color filter FIL (G, B,
The dummy color filter pattern FIL (C) is formed at the same time when any of R) is formed. The color filter FIL (G, B, R) and the dummy color filter pattern FIL (C) are formed by photolithography by depositing a photocurable dyeable resin.

That is, first, the black matrix BM
A dyeable resin made of gelatin, acrylic resin, or the like is applied on the upper transparent substrate SUB2 on which is formed by a spin coating method, a roll coating method, or the like so that the film thickness becomes uniform. Then, pre-baking is performed to remove the solvent in the film, exposure is performed through the pattern mask for the first color, and development is performed to remove the dyeable resin in unnecessary portions.

Next, 0.1 to 2.0% of the anionic dye
The aqueous solution is heated to 40 to 70 ° C., and the upper transparent substrate SUB2 on which the pattern of the dyeable resin is formed is immersed in the aqueous solution for coloring. After coloring, a dye-proof treatment is carried out with tannic acid, sodium atimonyl tartrate or the like to prepare a first color filter. The above operation is repeated three times to obtain the color filter FIL (G, B, R) and the dummy color filter pattern FIL (C).

After forming these color filters, an acrylic resin or an epoxy resin for preventing elution of the dye and ensuring the flatness of the surface is applied by a spin coating method, a roll coating method, or a transfer printing method, and heat is applied. The protective film PSV is formed by curing. After forming the protective film PSV, a conductive material containing indium oxide as a main component is formed by a sputtering method to form a transparent conductive film ITO2 to be a common electrode.

An upper alignment film ORI2 is formed by a transfer printing method on the upper transparent substrate SUB2 on which various films are formed as described above, and after orientation processing, a sealing material SL containing a thermosetting epoxy resin as a main component and a conductive material. Lower transparent substrate SUB in which a lower alignment film ORI1 is formed on the thin film transistor TFT after applying a conductive adhesive CM (AGP) by a screen printing method, a dispenser coating method, etc. and drying to remove the solvent
1, and a load of 0.5 to 1.0 kg / cm ² is applied to perform curing treatment at 150 to 180 ° C. for 1 to 4 hours.

Both the cured transparent substrates are cut into a predetermined size, the liquid crystal LC is injected into the gap between the two substrates, and the injection portion is filled with epoxy resin or the like for sealing. After that, the upper polarizing plate POL2 is attached to the upper transparent substrate SUB2 side, and the lower polarizing plate POL1 is attached to the lower transparent substrate SUB1 side.
The FT liquid crystal display device is completed.

The color TFT liquid crystal display device thus obtained was subjected to accelerated tests such as leaving it at 60 ° C. and leaving it at 60 ° C. and 90% RH . No defective lighting was observed. As described above, according to the present embodiment, it is possible to obtain the color liquid crystal display element in which the display quality is not deteriorated and the lighting failure is not generated in the conventional technique. Examples of a liquid crystal display device constructed by using the color liquid crystal display element will be described below.
In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

FIG. 3 shows an active system to which the present invention is applied.
FIG. 4 is a cross-sectional view taken along the line 3-3 in FIG. 3, and FIG. 5 is a cross-sectional view taken along the line 4-4 in FIG.
As shown in FIG. 3, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent scanning signal lines GL.
Book video signal line (drain signal line or vertical signal line) D
It is arranged in a region intersecting with L (in a region surrounded by four signal lines).

Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. The video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction. As shown in FIG. 4, a thin film transistor TFT and a transparent pixel electrode (lower transparent conductive film) ITO1 are formed on the lower transparent glass substrate (lower transparent substrate) SUB1 side with respect to the liquid crystal layer LC, and an upper transparent glass substrate (upper). On the transparent substrate SUB2 side, a color filter FIL and a light-shielding black matrix pattern BM are formed.

Silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Upper transparent glass substrate SUB2
A light-shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (upper transparent conductive film) ITO2 (COM), and an upper alignment film (upper alignment film) ORI2 are sequentially formed on the inner surface (liquid crystal LC side) of the. It is provided by stacking.

FIG. 6 shows upper and lower glass substrates SUB1 and SUB.
2 is a plan view of a main part around a matrix (AR) of a display panel PNL including 2; FIG. 7 is a plan view in which the peripheral part is further exaggerated;
FIG. 8 is an enlarged plan view of the vicinity of the seal portion SL corresponding to the upper left corner of the panels of FIGS. 6 and 7. 9 is a cross-sectional view showing the cross section taken along the line 8a-8a of FIG. 8 on the left side and the cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected, on the right side, with the cross section of FIG. 4 as the center. Is.

Similarly, FIG. 10 is a cross-sectional view showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side. In the manufacturing of this panel, if it is a small size, one glass substrate is processed into a plurality of devices at the same time in order to improve the throughput, and then it is divided. However, after processing a standardized glass substrate, it is reduced to a size that suits each product type, and in each case, the glass is cut after going through a series of steps. FIGS. 6 to 8 show the latter example. In both of FIGS. 6 and 7, the upper and lower substrates SUB1 and SU are shown.
B2 after cleavage and FIG. 8 before cleavage, LN
Indicates the edges of both substrates before cutting, and CT1 and CT2 indicate the positions of the substrates SUB1 and SUB2 to be cut, respectively. In either case, the size of the upper substrate SUB2 is smaller than the lower substrate SUB1 so that the external connection terminal groups Tg and Td (subscripts omitted) (upper side and left side in the figure) are exposed in the completed state. Is more restricted to the inside.

The terminal groups Tg and Td are respectively a scanning circuit connecting terminal GTM and a video signal circuit connecting terminal DTM, which will be described later.
And those lead-out wiring portions are mounted on the tape carrier package TCP (FIGS. 19 and 20) on which the integrated circuit chip CHI is mounted.
(See below in) It is the one that is collectively named in the unit.
The lead wiring from the matrix portion of each group to the external connection terminal portion is inclined toward both ends. This is because the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP are equal to the terminals DT of the display panel PNL.
This is to match M and GTM.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal filling port INJ, the liquid crystal LC
A seal pattern SL is formed so as to seal the. This sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate SUB2 is provided in at least one place, in the present embodiment, at the four corners of the panel by the silver paste material AGP by the lower transparent glass substrate SUB.
It is connected to the lead wire INT formed on the first side. The lead wiring INT is a gate terminal GTM, which will be described later.
It is formed in the same manufacturing process as the drain terminal DTM.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1, the common transparent pixel electrode ITO2, and the respective layers are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are the lower transparent glass substrate SUB.
1, formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules.

The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side. In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, the seal pattern SL is formed on the substrate SUB2 side, and the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB are formed.
2 is overlapped, the liquid crystal LC is injected from the opening INJ of the seal material SL, the injection port INJ is sealed with an epoxy resin, and the upper and lower substrates are cut to assemble.

Next, returning to FIGS. 3 and 4, the TFT substrate S
The configuration on the UB1 side will be described in detail. Thin film transistor T
FT, when a positive bias is applied to the gate electrode GT,
When the channel resistance between the source and the drain becomes small and the bias becomes zero, the channel resistance operates so as to become large. Each pixel has a plurality (two) of thin film transistors T.
FT1 and TFT2 are redundantly provided. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic).
sic, i-type semiconductor layer AS made of amorphous silicon (Si which is not doped with conductivity determining impurities) (Si), a pair of source electrode SD1 and drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

The gate electrode GT has a shape protruding vertically from the scanning signal line GL (branched into a T shape). The gate electrode GT is a thin film transistor TF
It projects so as to exceed the active regions of T1 and TFT2. The gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrally configured (as a common gate electrode) and are formed continuously with the scanning signal line GL.

In this example, the gate electrode GT is formed of a single-layer second conductive film g2. An aluminum (Al) film formed by sputtering, for example, is used as the second conductive film g2, and an Al anodic oxide film AOF is provided thereon. The gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below), and is devised so that the i-type semiconductor layer AS is not exposed to external light or backlight light.

The scanning signal line GL is composed of the second conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. In addition, the scanning signal line GL
An Al anodic oxide film AOF is also provided on the top. The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistors TFT1 and TFT2.

The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected, and has a thickness of 1200 to 2700Å (in the present embodiment,
About 2000Å) is formed. The gate insulating film GI is shown in FIG.
As shown in FIG. 7, the matrix portion AR is formed so as to surround the whole, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI also contributes to the electrical insulation between the scanning signal line GL and the video signal line DL.

In this example, the i-type semiconductor layer AS is formed so as to be an independent island in each of the thin film transistors TFT1 and TFT2.
It is formed to have a thickness of Å (in this embodiment, a film thickness of about 2000 Å). The layer d0 is a phosphorus (P) -doped N (+)-type amorphous silicon semiconductor layer for ohmic contact, the i-type semiconductor layer AS exists on the lower side, and the conductive layer d2 (d3) exists on the upper side. It is left only where you do.

The i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection. The transparent pixel electrode ITO1 constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT1 and the source electrode SD1 of the thin film transistor TFT2. Therefore, the thin film transistors TFT1, T
Even if a defect occurs in one of the FT2s, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor is operating normally, so it is left alone. Good. Transparent pixel electrode I
TO1 is composed of a first conductive film d1, and this first conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering.
With a thickness of 00 to 2000 Å (in this embodiment, 1400 Å
Film thickness).

Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon. The second conductive film d2 is a chromium (Cr) film formed by sputtering and is formed to a thickness of 500 to 1000Å (in this embodiment, about 600Å). If the Cr film is formed thick, the stress increases, so 2
It is formed within a range not exceeding the film thickness of about 000Å. The Cr film improves the adhesiveness to the N (+) type semiconductor layer d0,
It is used for the purpose of preventing Al of the conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used instead of the Cr film.

The third conductive film d3 is formed by sputtering Al to a thickness of 3000 to 5000Å (400 in this embodiment).
0 Å) formed. The Al film has less stress than the Cr film and can be formed to have a large film thickness, and the source electrode SD1, the drain electrode SD2 and the video signal line DL can be formed.
Of the gate electrode GT and the i-type semiconductor layer AS are ensured (step coverage is improved).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, using the same mask, or using the second conductive film d2 and the third conductive film d3 as masks, N (+) type The semiconductor layer d0 is removed. That is, the N (+) type semiconductor layer d0 remaining on the i-type semiconductor layer AS is self-aligned except for the second conductive film d2 and the third conductive film d3. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface of the i type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.

The video signal line DL has a second conductive film d2 and a third conductive film d2 in the same layer as the source electrode SD1 and the drain electrode SD2.
It is composed of three. A protective film PSV1 is provided on the thin film transistor TFT and the transparent pixel electrode ITO1. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. Protective film PSV1
Is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a film thickness of about 1 μm.

As shown in FIG. 8, the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the common electrode of the upper substrate side SUB2. COM to the lower substrate SUB
Silver paste A on the lead wire INT for connecting the external connection terminal 1
The part connected by GP is also removed. Protective film PSV1
Regarding the thickness relationship between the gate insulating film GI and the gate insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made thin in the transconductance gm of the transistor. Therefore, as shown in FIG. 8, the protective film PSV1 having a high protective effect is formed to be larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

On the upper transparent glass substrate SUB2 side, a light shielding film BM is provided so that external light or backlight light does not enter the i-type semiconductor layer AS. Light-shielding film B shown in FIG.
The closed polygonal contour line of M indicates an opening in which the light shielding film BM is not formed. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to have a thickness of about 1300 Å.

Therefore, the thin film transistors TFT1 and TF
The i-type semiconductor layer AS of T2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and external natural light or backlight light is not exposed.
The light-shielding film BM is formed in a lattice shape around each pixel (so-called,
(Black matrix), an effective display area of one pixel is partitioned by this grid. Therefore, the outline of each pixel is
M improves clarity and contrast. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Since the edge portion of the transparent pixel electrode ITO1 on the root side in the rubbing direction (the lower right portion in FIG. 3) is also shielded by the light shielding film BM, even if a domain occurs in the above portion, the domain cannot be seen. The display characteristics do not deteriorate. As shown in FIG. 7, the light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. 3 in which a plurality of dots-like openings are provided. The light-shielding film BM in the peripheral portion is shown in FIGS.
As shown in 0, it is extended to the outside of the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion. On the other hand, this light-shielding film BM
Is fixed to the inside of the edge of the substrate SUB2 by about 0.3 to 1.0 mm, and is formed so as to avoid the cutting region of the substrate SUB2.

The color filter FIL is formed in a stripe shape by repeating R (red), G (green) and B (blue) at a position facing the pixel. The color filter FIL is formed to have a large size so as to cover the entire transparent pixel electrode ITO1, and the light-shielding film BM includes the color filter FIL and the transparent pixel electrode I.
Transparent pixel electrode ITO1 overlaps with the edge of TO1
Is formed inside the peripheral portion of

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin. The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side,
The optical state of the liquid crystal LC changes in response to a potential difference (electric field) between each pixel electrode ITO1 and the common transparent pixel electrode ITO2. A common voltage Vcom is applied to the common transparent pixel electrode ITO2.

In this embodiment, the common voltage Vcom is set to an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL, but it is used in the video signal drive circuit. If it is desired to reduce the power supply voltage of the integrated circuit to about half, an AC voltage may be applied. For the planar shape of the common transparent pixel electrode ITO2, see FIGS. 7 and 8.

The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. As is clear from FIG. 5, this superposition constitutes a holding capacitance element (electrostatic capacitance element) Cadd having the transparent pixel electrode ITO1 as one electrode PL2 and the adjacent scanning signal line GL as the other electrode PL1. To do.

The dielectric film of the storage capacitor Cadd is composed of an insulating film GI and an anodized film AOF used as a gate insulating film of the thin film transistor TFT.
The storage capacitor Cadd is the second conductive film g2 of the scanning signal line GL.
Is formed in the part where the width of is widened. The second conductive film g2 at the portion intersecting the video signal line DL is the video signal line DL.
It is narrowed to reduce the probability of short-circuiting with.

Even if the transparent pixel electrode ITO1 is broken at the step of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3. 11A and 11B are explanatory views of a connection structure from the scanning signal line GL of the display matrix to the external connection terminal GTM thereof. FIG. 11A is a plan view and FIG. 11B is a sectional view taken along the line BB of FIG. Is. Note that the same drawing corresponds to the lower part of FIG. 8, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In FIG. 3A, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. The oxide Al ₂ O ₃ film AOF is formed on the surface of the anodized AL layer g2, and the volume of the conductive portion below is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains.

The mask pattern AO does not intersect the scanning line GL with a single straight line, but is bent in a crank shape and intersects with it. In the figure, the AL layer g2 is hatched for the sake of clarity, but the region not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this embodiment, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM has a good adhesion to the silicon oxide SIO layer and a Cr layer g1 having a higher electric contact resistance than Al or the like.
Further, the surface thereof is protected and is composed of a transparent conductive layer d1 of the same level (same layer, simultaneously formed) as the pixel electrode ITO1.
In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion G located at the left end is formed.
The TMs are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG.
(FIGS. 7 and 8), the left end of the gate terminal is extended beyond the cutting region CT1 of the substrate and short-circuited by the wiring SHg in the manufacturing process.

Such a short-circuit line SHg in the manufacturing process
Is useful for feeding power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1. FIG. 12 is an explanatory diagram of the connection from the video signal line DL to its external connection terminal DTM.
(A) is the top view, (B) is sectional drawing in the BB cutting line of (A). The drawing corresponds to the vicinity of the upper right of FIG. 8, and although the orientation of the drawing is changed for convenience, the right end direction is the substrate S.
It corresponds to the upper end (or the lower end) of UB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than the wiring portion so that a probe needle or the like can come into contact therewith. Similarly, the drain terminal D
The width of the TM is also wider than that of the wiring portion so that the TM can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure, but the drain terminal DTM.
As shown in FIG. 8, the terminal group Td (subscripts are omitted) is further extended beyond the cutting line CT1 of the substrate SUB1, and all of them are interconnected with each other to prevent electrostatic breakdown during the manufacturing process.
Shorted by Hd.

Video signal line D having inspection terminal TSTd
The drain connection terminal is connected to the opposite side across the L matrix, and conversely, the inspection terminal is connected to the opposite side across the matrix of the video signal line DL in which the drain connection terminal DTM exists. The drain connection terminal DTM has the Cr layer g1 and the ITO layer d1 for the same reason as the above-mentioned gate terminal GTM.
Is formed of two layers, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed.

The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. The protective film PSV1 is, of course, removed on the terminal DTM to connect to an external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with a mask.
This pattern is not directly relevant since there is no layer g2 in the parts not covered in this figure.

The lead wiring from the matrix portion to the drain terminal portion DTM is, as shown in FIG. 9C, a video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal portion DTM. Although the layers d2 and d3 of the same level are laminated part way up to the middle of the seal pattern SL, this minimizes the probability of disconnection and facilitates electrical contact.
The purpose is to protect the l layer d3 as much as possible with the protective film PSV1 and the seal pattern SL.

FIG. 13 shows a wiring diagram of an equivalent circuit of the display matrix section and its peripheral circuits. Although the figure is a circuit diagram,
It is drawn according to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged. In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y means the scanning signal line GL, and the subscripts 1, 2,
3, ..., End are added according to the order of the scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho, and the scanning signal line Y is used.
(Subscript omitted) is connected to the vertical scanning circuit V. SU
P is a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source.
It is a circuit including a circuit for exchanging CRT (cathode ray tube) information from the above with information for a TFT liquid crystal display device.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation. ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg where Cgs is the gate electrode G of the thin film transistor TFT
Parasitic capacitance formed between T and source electrode SD1, C
pix is a capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM), ΔV
lc represents a change amount of the pixel electrode potential due to ΔVg.

This change ΔVlc causes a direct current component applied to the liquid crystal LC, and the value can be reduced as the holding capacitance Cadd is increased. Further, the storage capacitor element Cadd also has a function of prolonging the discharge time, and stores the image information for a long time after the thin film transistor TFT is turned off. The reduction of the direct current component applied to the liquid crystal LC is
It is possible to improve the service life of the device and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and the parasitic capacitance Cgs is increased accordingly. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, this demerit can be eliminated by providing the storage capacitor element Cadd.

The holding capacitance of the holding capacitance element Cadd is 4 to 8 times (4.
Cpix <Cadd <8 · Cpix), 8 for parasitic capacitance Cgs
Set to a value of approximately 32 times (8 · Cgs <Cadd <32 · Cgs). The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is the common transparent pixel electrode ITO2.
Set to the same potential as (Vcom). In the example of FIG. 8, the scanning signal line at the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead wire INT, the terminal DT0 and the external wiring. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is the scanning signal line Ye in the last stage.
It may be connected to nd, connected to a DC potential point (AC ground point) other than Vcom, or connected to receive one extra scanning pulse Y ₀ from the vertical scanning circuit V.

Next, the substrate SU of the above-mentioned liquid crystal display device
The manufacturing method on the B1 side will be described with reference to FIGS. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 4, and the right side shows the flow of processing seen in the sectional shape near the gate terminal shown in FIG.

Further, except for the step D, the steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage where the processing after the photographic process is completed and the photoresist is removed. ing. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 14 After a silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip processing, baking is performed at 500 ° C. for 60 minutes. The film thickness is 1100Å on the lower transparent glass substrate SUB1.
The first conductive film g1 made of chromium is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd shorting the drain terminal DTM, and the anodized pad (not shown) connected to the anodized bus line SHg. To form.

Step B, FIG. 14 Al-Pd, Al-Si, Al-S having a film thickness of 2800Å
The second conductive film g2 made of i-Ti, Al-Si-Cu, or the like
Are provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid. Step C, FIG. 14 After photographic processing (after forming the anodizing mask AO described above), 3
Substrate SUB1 was immersed in an anodizing solution consisting of a solution of% tartaric acid adjusted to pH 6.25 ± 0.05 with ammonia, diluted 1: 9 with ethylene glycol solution, and the formation current density was 0.5 mA / cm 2. Adjust so that it becomes (constant current formation).

Next, anodization is performed until the formation voltage of 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached.
After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. Thereby, the conductive film g2 is anodized, and the scanning signal line GL, the gate electrode GT, and the electrode PL1.
An anodic oxide film AOF having a film thickness of 1800Å is formed on the upper surface.

Step D, FIG. 15 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus. After forming an i-type amorphous Si film having a thickness of 2000 Å, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+)-type amorphous Si film having a film thickness of 300 Å.

Step E, FIG. 15 After photo processing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous S
The island of the i-type semiconductor layer AS is formed by selectively etching the i film. Step F, FIG. 15 After the photographic processing, SF ₆ is used as a dry etching gas to selectively etch the Si nitride film.

Step G, FIG. 16 A first conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H, FIG. 16: A second conductive film d2 made of Cr and having a film thickness of 600 Å is provided by sputtering.
Pd, Al-Si, Al-Si-Ti, Al-Si-C
A third conductive film d3 made of u or the like is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as the process B, and the second conductive film d2 is etched with the same liquid as the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do.

Next, a dry etching apparatus was used for CC.
l ₄ and SF ₆ are introduced to etch the N (+) type amorphous Si film, so that N (+) between the source and the drain is increased.
The type semiconductor layer d0 is selectively removed. Step I, FIG. 16 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 1 μm. After the photo processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique using SF ₆ as a dry etching gas.

FIG. 17 is an exploded perspective view showing each component of the liquid crystal display module MDL. SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, BL
S is the backlight support, LCA is the lower case,
The modules MDL are assembled by stacking the respective members in a vertical arrangement relationship as shown in the figure.

The module MDL is a shield case SH.
The whole is fixed by the claw CL and the hook FK provided on D. The intermediate frame MFR is formed in a frame shape so as to have an opening corresponding to the display window LCW, and the frame portion has unevenness corresponding to the shapes and thicknesses of the diffusion plate SPB, the backlight support BLS, and various circuit components, An opening for heat dissipation is provided.

The lower case LCA also serves as a reflector for backlight light, and a reflection mountain RM is formed corresponding to the fluorescent tube BL so as to efficiently reflect light. FIG.
FIG. 7 is a top view showing a state in which video signal drive circuits He and Ho and a vertical scanning circuit V are connected to the display panel PNL shown in FIG. 6 and the like. CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side)
Chips, 6 each on the left and right are drive I on the video signal drive circuit side
C chip).

In the TCP, as will be described later with reference to FIGS. 19 and 20, the driving IC chip CHI is a tape automated type.
The tape carrier package mounted by the bonding method (TAB), PCB1 is the above TCP or capacitor C
A drive circuit board on which a DS or the like is mounted is divided into three parts. FGP is a frame ground pad, and is a spring-like fragment F cut into the shield case SHD.
G is soldered. FC is the lower drive circuit board PCB
1 is a flat cable that electrically connects the left drive circuit board PCB1 and the lower drive circuit board PCB1 and the right drive circuit board PCB1.

As shown in the figure, the flat cable FC has a plurality of lead wires (phosphor bronze material plated with Sn) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer and supported. To use. FIG. 19 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which the integrated circuit chip CHI, which constitutes the scanning signal drive circuit V and the video signal drive circuits He and Ho, is mounted on a flexible wiring board, and FIG. In this example of the liquid crystal display panel, the video signal circuit terminal DT
It is a principal part sectional view which shows the state connected to M.

In the figure, TTB is an input terminal / wiring part of the integrated circuit CHI, and TTM is an output terminal / wiring part of the integrated circuit CHI, which is made of, for example, Cu, and has inner end parts (commonly called inner parts). The bonding pad PAD of the integrated circuit CHI is connected to the lead) by a so-called face-down bonding method. Terminal TTB,
The outer tip of the TTM (commonly called outer lead) corresponds to the input and output of the semiconductor integrated circuit chip CHI, and is displayed on the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like, and a liquid crystal display is made by an anisotropic conductive film ACF It is connected to the panel PNL.

The package TCP is connected to the panel so that its tip portion covers the protective film PSV1 exposing the connection terminal DTM on the panel PNL side. Therefore, the external connection terminal DTM (GTM) is the protective film PSV1 or the package T
Since it is covered on at least one of the CPs, it becomes strong against electric contact. BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to an unnecessary place during soldering.

The gap between the upper and lower glass substrates outside the seal pattern SL is protected by epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to provide multiple protection. As shown in FIG. 21, the drive circuit board PCB2 of the liquid crystal display unit LCD held and housed in the intermediate frame MFR is L-shaped, and has electronic parts such as ICs, capacitors and resistors mounted thereon. This drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting into information for a TFT liquid crystal display device is mounted.

CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected. Drive circuit board P
The CB2 and the inverter circuit board PCB3 are electrically connected by a backlight cable through a connector hole provided in the intermediate frame MFR. The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a foldable flat cable FC. When assembled, the drive circuit board PCB2 connects the flat cable FC 180 °
By being folded, it is stacked on the back side of the drive circuit board PCB1 and fitted into a predetermined recess of the intermediate frame MFR.

As described above, by providing the dummy filter FIL (C) at the interposition of the conductive adhesive on the upper transparent substrate SUB2 of the liquid crystal display element constituting the color liquid crystal display device, the liquid crystal or other It is possible to provide a high-quality and highly reliable color liquid crystal display device which avoids the occurrence of defective conduction due to deformation of constituent members due to changes in temperature and humidity.

[0088]

As described above, according to the present invention,
High quality, high reliability color liquid crystal display that can prevent connection failure and disconnection due to environmental changes of the conductive adhesive that conductively connects the common conductive film formed on the upper transparent substrate and the terminal electrode film formed on the lower transparent substrate. A device can be provided.

[Brief description of drawings]

FIG. 1 is a plan view of an essential part of an upper transparent substrate for explaining an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a partial cross-sectional view including a lower transparent substrate as seen from the line AA ′ in FIG.

FIG. 3 is a main part plan view showing one pixel and its periphery of a liquid crystal display unit of an active matrix type color liquid crystal display device to which the present invention is applied.

4 is a cross-sectional view showing one pixel and its periphery taken along the line 3-3 in FIG.

5 is a cross-sectional view of the additional capacitance Cadd taken along section line 4-4 of FIG.

FIG. 6 is a plan view for explaining a configuration of a peripheral portion of a matrix of a display panel.

FIG. 7 is a panel plan view for slightly exaggerating the peripheral portion of FIG. 5 to explain it more specifically.

FIG. 8 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates.

FIG. 9 is a cross-sectional view showing the vicinity of a panel angle and the vicinity of a video signal terminal portion on both sides, with the pixel portion of the matrix at the center.

FIG. 10 is a cross-sectional view showing a scan signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 11 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 12 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 13 is a circuit diagram including a matrix portion of an active matrix type color liquid crystal display device and its periphery.

FIG. 14 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 15 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps D to F on the substrate SUB1 side.

FIG. 16 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps GI on the side of the substrate SUB1.

FIG. 17 is an exploded perspective view of a liquid crystal display module.

FIG. 18 is a top view showing a state in which a peripheral drive circuit is mounted on a liquid crystal display panel.

FIG. 19 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI which constitutes a drive circuit is mounted on a flexible wiring board.

FIG. 20 is a main-portion cross-sectional view showing a state where the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 21: Peripheral drive circuit board PCB1 (top surface visible)
It is a top view which shows the connection state of power supply circuit circuit board PCB2 (a lower surface is visible).

[Explanation of symbols]

 SUB1 Lower transparent substrate SUB2 Upper transparent substrate BM Black matrix FIL (G, B, R) Color filter FIL (C) Dummy color filter pattern ITO1, ITO2 Transparent conductive film ITO terminal electrode film PSV protective film ORI1 Upper alignment film ORI2 Lower alignment film SL is a sealing material CM (AGP) Conductive adhesive TFT TFT Thin film transistor LC Liquid crystal POL1 Upper polarizing plate POL2 Lower polarizing plate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Aoki 3300 Hayano, Mobara-shi, Chiba Electronic device division, Hitachi, Ltd. (72) Hiroyuki Inoue 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic device business Department

Claims (1)

[Claims] 1. An upper transparent substrate comprising at least a color filter of a plurality of colors, an upper transparent conductive film that covers the color filters of a plurality of colors to form a common electrode, and an upper alignment film formed on the upper transparent conductive film. And a lower transparent substrate having at least a lower transparent conductive film forming an individual electrode corresponding to the color filter and a terminal electrode film connected to the upper transparent conductive film, and a lower alignment film formed on the lower transparent conductive film. , The liquid crystal injected into the gap between the upper transparent conductive film and the lower transparent conductive film, and the liquid crystal injected between the upper transparent conductive film of the upper transparent substrate and the terminal electrode film of the lower transparent substrate are electrically connected to each other. In a liquid crystal display device having a conductive adhesive for connection, the liquid crystal display device including a sealing material for sealing the liquid crystal injected between the upper transparent substrate and the lower transparent substrate, wherein the conductive adhesive is interposed. The upper transparent conductive film A liquid crystal display device having a dummy color filter pattern formed at the time of patterning any of the color filters as an underlayer.