[go: up one dir, main page]

JPH07202070A - Electronic component mounter and its manufacture - Google Patents

Electronic component mounter and its manufacture

Info

Publication number
JPH07202070A
JPH07202070A JP5354310A JP35431093A JPH07202070A JP H07202070 A JPH07202070 A JP H07202070A JP 5354310 A JP5354310 A JP 5354310A JP 35431093 A JP35431093 A JP 35431093A JP H07202070 A JPH07202070 A JP H07202070A
Authority
JP
Japan
Prior art keywords
wiring board
lead frame
hole
surface side
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5354310A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kondo
光広 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP5354310A priority Critical patent/JPH07202070A/en
Publication of JPH07202070A publication Critical patent/JPH07202070A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To fine down the pitches of the tip of the conductor wiring of a semiconductor chip mounter. CONSTITUTION:The first layer wiring board 10 is provided with an aperture 11 at the center, and a through hole 12 in the vicinity of the periphery. An adhesive layer 14 is provided near the periphery of the first wiring board, and the tip of the inner lead 31a of a lead frame 30 is arranged on and bonded to the through hole 12. The first wiring board is soaked in solder bath, and solder junction is made between the lead frame and the through hole by the solder having gone up through the through hole. The second wiring board 20 is provided with an aperture 21 larger than the aperture 11 at the center, and is provided with a through hole 22 in the vicinity of the periphery. The second wiring board is bonded onto the first wiring board and the lead frame, and solder junction is made between the lead frame and the through hole. The peripheral wall of a chip mounter is provided with a step, and this step is made the connector terminal for wire bonding, whereby the terminal pitches are roughly doubled substantially.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子部品搭載装置に係
り、特に所謂リードフレームを使用して製造されると共
に配線基板に配設された導体配線の電子部品の端子との
接続用ボンディング端子のピッチの細かい電子部品搭載
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component mounting apparatus, and more particularly to a bonding terminal for connecting a conductor wiring, which is manufactured by using a so-called lead frame and arranged on a wiring board, to a terminal of an electronic component. Relates to an electronic component mounting device having a fine pitch.

【0002】[0002]

【従来の技術】従来、この種の電子部品搭載装置は、配
線基板の導体配線のピッチを細かくすることにより、電
子部品の端子との接続用ボンディング端子のピッチを細
かくしていた。そして、かかる電子部品搭載装置の導体
ピッチの限界は、ボンディングワイヤーのつぶれ幅を考
えると180μm程度であった。
2. Description of the Related Art Conventionally, in the electronic component mounting apparatus of this type, the pitch of the conductor wirings of the wiring board is made fine so that the pitch of the bonding terminals for connection with the terminals of the electronic component is made fine. The limit of the conductor pitch of the electronic component mounting apparatus is about 180 μm in consideration of the crushed width of the bonding wire.

【0003】[0003]

【発明が解決しようとする課題】しかるに、電子部品搭
載装置の高密度実装の要請は大であり、ボンディング端
子のピッチも100μm以下という非常なファインピッ
チが要求されている。かかる特性を得るためには、例え
ばピングリッドアレイパッケージ用基板について、特公
平2ー5014号公報に示されている方法を用いること
もできる。同公報によれば、各々の半導体素子収容開口
部の面積の大きさの異なる複数の配線基板を、面積の大
きい順に重合わせ、かつ上下側に開口部を設けない基板
を貼り合わせていた。そして、この積層された基板に穴
明け、銅めっき等の複数の処理を加えた後に、表面側の
基板に蓋取り加工を行っていた。このようにして、半導
体素子収容部の周壁に段を設け、ワイヤーボンディング
の配線基板側のボンディング位置を複数段に分散させる
ことにより実効的にボンディング端子のファインピッチ
化を図っていた。しかし、上記方法によれば、積層基板
の製造工程が長くなると共に製造工程において基板に加
わる応力に耐えるために基板の厚みを厚くしなければな
らない等の問題がある。本発明は、上記した問題を解決
しようとするもので、簡易な構造でかつ配線基板のボン
ディング端子のピッチを実効的に非常に細かくした電子
部品搭載装置及びその製造方法を提供することを目的と
する。
However, there is a great demand for high-density mounting of electronic component mounting devices, and the pitch of bonding terminals is required to be a very fine pitch of 100 μm or less. In order to obtain such characteristics, for example, for a pin grid array package substrate, the method disclosed in Japanese Patent Publication No. 2-5014 can be used. According to the publication, a plurality of wiring boards each having a different area size of the semiconductor element accommodating opening are stacked in order of increasing area, and boards having no opening on the upper and lower sides are bonded together. Then, after performing a plurality of treatments such as drilling and copper plating on the laminated substrates, the substrate on the front surface side is capped. In this way, steps are provided on the peripheral wall of the semiconductor element accommodating portion, and the bonding positions on the wiring board side of wire bonding are dispersed in a plurality of steps to effectively achieve a fine pitch of the bonding terminals. However, according to the above method, there are problems that the manufacturing process of the laminated substrate becomes long and the thickness of the substrate must be increased in order to withstand the stress applied to the substrate in the manufacturing process. The present invention is intended to solve the above problems, and an object thereof is to provide an electronic component mounting apparatus having a simple structure and effectively making the pitch of the bonding terminals of the wiring board very fine, and a manufacturing method thereof. To do.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するため
に、上記請求項1に係る発明の構成上の特徴は、外周の
近傍位置に複数の第1スルーホールを有した第1配線基
板と、第1配線基板より形状が大きく、外周の近傍位置
に複数の第2スルーホールを有し、かつ開口部を設け、
第1配線基板の表面側の一部に接着剤層を介して接着さ
れた第2配線基板と、第1配線基板及び第2配線基板の
端部間に挟まれた複数のリードを有し、複数のリードの
内の少なくとも一部の片面がはんだにより第1スルーホ
ールに接合され、複数のリードの内の少なくとも一部の
反対面がはんだにより第2スルーホールに接合されたリ
ードフレームとを設けたことにある。
In order to achieve the above-mentioned object, a structural feature of the invention according to claim 1 is that a first wiring board having a plurality of first through holes in a position near an outer periphery is provided. , Having a shape larger than that of the first wiring board, having a plurality of second through holes in the vicinity of the outer circumference, and providing an opening,
A second wiring board adhered to a part of the front surface side of the first wiring board via an adhesive layer; and a plurality of leads sandwiched between the end portions of the first wiring board and the second wiring board, And a lead frame in which at least a part of one side of the plurality of leads is joined to the first through hole by solder, and at least a part of the opposite side of the plurality of leads is joined to the second through hole by solder. There is something.

【0005】上記目的を達成するために、上記請求項2
に係る発明の構成上の特徴は、外周の近傍位置に複数の
第1スルーホールを有した第1配線基板の表面側の外周
近傍に設けた接着剤層を介してリードフレームの複数の
リードの内の少なくとも一部を第1スルーホール上に配
置した状態で第1配線基板の表面側に固定させるリード
フレーム接着工程と、リードフレームの接着された第1
配線基板の裏面側から第1スルーホールを通してはんだ
を進入させ、第1スルーホールとリードフレームとの間
にはんだ接合を形成する第1はんだ接合形成工程と、第
1配線基板より形状が大きく、外周の近傍位置に複数の
第2スルーホールを有し、かつ開口部を設けた第2配線
基板の裏面側を、接着剤層を介して第1配線基板及びリ
ードフレームに接着させる第2配線基板接着工程と、第
2配線基板の表面側から第2スルーホールを通してはん
だを進入させ、第2スルーホールとリードフレームとの
間にはんだ接合を形成する第2はんだ接合形成工程とを
設けたことにある。
In order to achieve the above object, the above-mentioned claim 2
The structural feature of the invention according to the invention is that a plurality of leads of a lead frame are provided via an adhesive layer provided in the vicinity of the outer periphery on the front surface side of the first wiring board having a plurality of first through holes in the vicinity of the outer periphery. A lead frame bonding step of fixing at least a part of the inside to the front surface side of the first wiring board in a state where the lead frame is bonded to the first through hole;
A first solder joint forming step of forming a solder joint between the first through hole and the lead frame by injecting solder from the back surface side of the wiring board through the first through hole; Adhesion of a second wiring board having a plurality of second through holes in the vicinity of the first wiring board having openings and provided with openings to the first wiring board and the lead frame via an adhesive layer And a second solder joint forming step of forming a solder joint between the second through hole and the lead frame by injecting solder from the front surface side of the second wiring board through the second through hole. .

【0006】[0006]

【発明の作用・効果】上記のように構成した請求項1に
係る発明においては、リードフレームを挟んだ第1配線
基板及び第2配線基板が各々のスルーホールを介してリ
ードフレームにはんだにより接合されることにより積層
基板に形成される。そして、第2配線基板の開口部を第
1配線基板の導体配線の一部を表面に露出させるような
大きさにしているので、第1及び第2配線基板により構
成される電子部品収容部の周壁に段差を設けることが出
来る。このため、積層基板の電子部品とのワイヤーボン
ディングの接続位置を複数段に分散して設けることが出
来る。その結果、電子部品搭載装置の基板側のワイヤー
ボンディング接続位置のピッチを実効的に従来の2倍程
度に細かくすることができる。
In the invention according to claim 1 configured as described above, the first wiring board and the second wiring board sandwiching the lead frame are joined to the lead frame by soldering through the respective through holes. By doing so, a laminated substrate is formed. Since the opening of the second wiring board is sized so that a part of the conductor wiring of the first wiring board is exposed on the surface of the first wiring board, the electronic component housing portion composed of the first and second wiring boards A step can be provided on the peripheral wall. Therefore, it is possible to disperse the connection positions of the wire bonding with the electronic components of the laminated substrate in a plurality of stages. As a result, the pitch of the wire bonding connection positions on the substrate side of the electronic component mounting apparatus can be effectively made twice as fine as the conventional pitch.

【0007】上記のように構成した請求項2に係る発明
においては、外周の近傍位置に複数の第1スルーホール
を有した第1配線基板に、その外周側近傍に設けた接着
剤層を介してリードフレームの少なくとも一部を第1ス
ルーホール上に配置された状態でリードフレームを接着
固定させ、さらに、第1配線基板の裏面側から第1スル
ーホールを通してはんだを上昇させて、リードフレーム
と第1スルーホールの間にはんだ接合を形成している。
そして、リードフレームの反対側に同様に第1配線基板
より形状が大きく、外周の近傍位置に複数の第2スルー
ホールを有し、かつ開口部を設けた第2配線基板の裏面
側を、接着剤層を介して第1配線基板及びリードフレー
ムに接着させ、さらに、第2スルーホールとリードフレ
ーム間にはんだ接合を形成している。その結果、積層型
電子部品搭載装置の製造工程を、従来の方法に比べて短
くすることが出来、製造コストを低減させることが出来
る。
In the invention according to claim 2 configured as described above, the first wiring board having the plurality of first through holes in the vicinity of the outer periphery is provided with the adhesive layer provided near the outer periphery thereof. The lead frame is bonded and fixed with at least a part of the lead frame placed on the first through hole, and solder is raised from the back surface side of the first wiring board through the first through hole to form the lead frame. Solder joints are formed between the first through holes.
Then, on the opposite side of the lead frame, the back surface side of the second wiring board, which is also larger in shape than the first wiring board, has a plurality of second through holes in the vicinity of the outer periphery, and has an opening, is bonded. It is adhered to the first wiring board and the lead frame via the agent layer, and further, solder joint is formed between the second through hole and the lead frame. As a result, the manufacturing process of the laminated electronic component mounting apparatus can be shortened as compared with the conventional method, and the manufacturing cost can be reduced.

【0008】また、上記請求項2に係る発明によれば、
第1配線基板の導体配線の一部と第2配線基板の導体配
線の一部は段差が設けられており、積層基板の電子部品
とのワイヤーボンディングの接続位置を複数段に分散し
て設けることが出来る。その結果、基板側のボンディン
グのピッチを実効的に従来の2倍程度に細かくすること
ができる。さらに、上記請求項2に係る発明によれば、
第1配線基板及び第2配線基板について良品のみを選別
して用いることが出来るので、電子部品搭載装置の製造
歩留りを高めることが出来ると共にその信頼性も高める
ことができる。また、上記請求項2に係る発明によれ
ば、電子部品搭載装置がリードフレームを挟んで両側に
配線基板を設けているので、後の樹脂モールド工程にお
いて金型内に注入される樹脂の流れがリードフレームの
上下部分において均一にされる。そのため、ボイド等の
ない充填の均質な樹脂モールド層が得られ、電子部品の
信頼性が高められる。
According to the second aspect of the invention,
A part of the conductor wiring of the first wiring board and a part of the conductor wiring of the second wiring board are provided with a step, and the connection positions for wire bonding with the electronic components of the laminated board are provided in a plurality of stages. Can be done. As a result, the pitch of bonding on the substrate side can be effectively made finer by a factor of about two. Further, according to the invention of claim 2,
Since only good products can be selected and used for the first wiring board and the second wiring board, it is possible to increase the manufacturing yield of the electronic component mounting apparatus and also increase its reliability. Further, according to the invention of claim 2, since the electronic component mounting apparatus has the wiring boards on both sides of the lead frame, the flow of the resin injected into the mold in the subsequent resin molding step can be prevented. The top and bottom parts of the lead frame are made uniform. Therefore, a filled and homogeneous resin mold layer without voids can be obtained, and the reliability of the electronic component can be improved.

【0009】[0009]

【実施例】以下、本発明の一実施例を図面により説明す
る。図1は、実施例に係る半導体チップ搭載装置の一部
を斜視図により示したものであり、また、図2は組み立
て工程における半導体チップ搭載装置の断面を模式的に
示したものである。この半導体チップ搭載装置は、第1
層配線基板10と第2層配線基板20とリードフレーム
30と導体板40とを備えている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a part of a semiconductor chip mounting apparatus according to an embodiment, and FIG. 2 is a schematic sectional view of the semiconductor chip mounting apparatus in an assembly process. This semiconductor chip mounting device is the first
A layer wiring board 10, a second layer wiring board 20, a lead frame 30, and a conductor plate 40 are provided.

【0010】第1層配線基板10は、正方形で0.1m
m厚の銅張りガラス/トリアジン基板であり、中央に半
導体チップ搭載用の開口部11を設けると共に周縁部に
基板面を貫通した0.3mmφの複数のスルーホール1
2を設けている。スルーホール12の内壁には銅めっき
後にニッケルめっき及び金めっきが施されて導電層が形
成されている。そして、第1層配線基板10の表面側
は、基板10の表面の銅層をフォトエッチングすること
により開口部11近傍から4方に向けて各38本づつ合
計152本の導体配線13が形成されており、各導体配
線13の外端部の一部はスルーホール12に導通してい
る。また、導体配線13の少なくとも内端部にはワイヤ
ーボンディング用の金めっき13aが形成され、そのボ
ンディング端子は0.16mmピッチである。
The first layer wiring board 10 is a square and has a length of 0.1 m.
This is a copper-clad glass / triazine substrate having a thickness of m, and a plurality of through holes 1 having a diameter of 0.3 mm and having an opening 11 for mounting a semiconductor chip in the center and penetrating the substrate surface in the peripheral portion
2 is provided. A conductive layer is formed on the inner wall of the through hole 12 by copper plating, nickel plating, and gold plating. Then, on the front surface side of the first-layer wiring board 10, by photo-etching the copper layer on the surface of the board 10, 38 conductive wires 13 are formed in each of 38 directions from the vicinity of the opening 11 toward the four directions, that is, a total of 152 conductive wires 13 are formed. Therefore, a part of the outer end of each conductor wiring 13 is electrically connected to the through hole 12. Further, gold plating 13a for wire bonding is formed on at least the inner end portion of the conductor wiring 13, and its bonding terminal has a pitch of 0.16 mm.

【0011】第2層配線基板20は、第1層配線基板1
0より大きな正方形の0.1mm厚の銅張りガラス/ト
リアジン基板であり、中央に第1層配線基板10の開口
部11より面積の大きな半導体チップ搭載用の開口部2
1を設けている。また、第2層配線基板20は、周縁部
に基板面を貫通した0.3mmφの複数のスルーホール
22を設けている。スルーホール12の内壁には銅めっ
き後にニッケルめっき及び金めっきが施されて導電層が
形成されている。そして、第2層配線基板20の表面側
は、基板20表面の銅層をフォトエッチングすることに
より開口部21から4方に向けて各38本づつ合計15
2本の導体配線23が形成されており、各導体配線23
の外端部の一部はスルーホール22に導通している。ま
た、導体配線23の少なくとも内端部にはワイヤーボン
ディング用の金めっき23aが形成され、そのボンディ
ング端子は0.16mmピッチである。
The second-layer wiring board 20 is the first-layer wiring board 1.
It is a square 0.1 mm thick copper-clad glass / triazine substrate larger than 0, and has an opening 2 for mounting a semiconductor chip, which has a larger area than the opening 11 of the first layer wiring board 10 in the center.
1 is provided. Further, the second layer wiring board 20 is provided with a plurality of through holes 22 of 0.3 mmφ penetrating the board surface in the peripheral portion. A conductive layer is formed on the inner wall of the through hole 12 by copper plating, nickel plating, and gold plating. Then, on the front surface side of the second-layer wiring board 20, by etching the copper layer on the surface of the board 20 by photoetching, 38 wires each are provided from the opening 21 toward the four directions, for a total of 15 pieces.
Two conductor wirings 23 are formed, and each conductor wiring 23
A part of the outer end portion of is connected to the through hole 22. Further, gold plating 23a for wire bonding is formed on at least the inner end portion of the conductor wiring 23, and the bonding terminals thereof have a pitch of 0.16 mm.

【0012】リードフレーム30は、厚さ0.15mm
の銅合金製であり、フレーム(図示省略する)に連結さ
れた304本のリード31を有している。リードは、中
間にてダムバー31cによって支持されており、内側の
インナーリード31aと外側のアウターリード31bと
に分離されている。そして、インナーリード31aが、
第1配線基板10と第2配線基板20の間に挟まれてお
り、表面側が第2配線基板20のスルーホール22上に
位置し、裏面側が第1配線基板10のスルーホール12
上に位置している。インナーリード31aの裏面側と第
1配線基板10のスルーホール12間は、図2に示すよ
うに、はんだ12aにより固定されており、インナーリ
ード31aの表面側とスルーホール22間も、はんだ2
2aにより固定されている。導体板40は、厚さ1.3
mmの無酸素銅製であり、下側面にはNiめっきが施さ
れており、またその表面には中央の半導体チップ搭載部
位40aを除いて耐熱エポキシベースの60μm厚みの
接着剤シート41が貼り付けられている。導体板40
は、半導体チップ接着用に用いられると共に放熱板とし
ての機能を有する。
The lead frame 30 has a thickness of 0.15 mm.
Of copper alloy, and has 304 leads 31 connected to a frame (not shown). The lead is supported by a dam bar 31c in the middle, and is separated into an inner lead 31a on the inside and an outer lead 31b on the outside. Then, the inner lead 31a
It is sandwiched between the first wiring board 10 and the second wiring board 20, the front surface side is located on the through hole 22 of the second wiring board 20, and the back surface side is the through hole 12 of the first wiring board 10.
Located on top. The back surface side of the inner lead 31a and the through hole 12 of the first wiring board 10 are fixed by solder 12a as shown in FIG. 2, and the front surface side of the inner lead 31a and the through hole 22 are also solder 2
It is fixed by 2a. The conductor plate 40 has a thickness of 1.3.
It is made of oxygen-free copper and has a lower surface plated with Ni, and a heat-resistant epoxy-based adhesive sheet 41 having a thickness of 60 μm is attached to the surface except the central semiconductor chip mounting portion 40a. ing. Conductor plate 40
Is used for bonding a semiconductor chip and has a function as a heat dissipation plate.

【0013】つぎに、半導体チップ搭載装置の組み立て
について図2により説明する。まず、第1層配線基板1
0の表面側の所定位置に接着剤14を塗布し、その上に
リードフレーム30をインナーリード31aの先端をス
ルーホール12上に位置合わせして接着させる(図2
(a)参照)。そして、リードフレーム30の接着され
た第1層配線基板10を、裏面側を下側にして噴流はん
だ槽に接触させることにより、リードフレーム30はス
ルーホール12を上昇したはんだ12aによって第1層
配線基板10に簡単にかつ強固に固定される(図2
(b)参照)。
Next, assembly of the semiconductor chip mounting device will be described with reference to FIG. First, the first layer wiring board 1
The adhesive 14 is applied to a predetermined position on the surface side of 0, and the lead frame 30 is adhered thereon by aligning the tips of the inner leads 31a with the through holes 12 (see FIG. 2).
(See (a)). Then, the first layer wiring board 10 to which the lead frame 30 is adhered is brought into contact with the jet solder bath with the back surface side facing down, so that the lead frame 30 uses the solder 12a that has moved up the through hole 12 to form the first layer wiring. It is easily and firmly fixed to the substrate 10 (see FIG. 2).
(See (b)).

【0014】つぎに、第2層配線基板20の裏面側の開
口部21周囲に厚さ約0.2mmの接着剤シート24a
を貼り、外周の近傍に厚さ約0.06mmの接着剤シー
ト24bを貼り付ける。この第2層配線基板20を第1
配線基板10およびリードフレーム30に接着させる。
そして、第2層配線基板20の表面側に所定の位置以外
にはんだが付着しないように治具(図示しない)を取り
付けた後、第2層配線基板20の表面側を噴流はんだ槽
に接触させることにより、リードフレーム30はスルー
ホール22を上昇したはんだ22aによって第2層配線
基板20に容易にかつ強固に固定される(図2(c)参
照)。さらに、第1層配線基板10の裏面側の第1開口
部を覆って導体板40を接着剤層41を介して接着させ
ることにより、積層型の半導体チップ搭載装置が得られ
る(図2(c)参照)。
Next, an adhesive sheet 24a having a thickness of about 0.2 mm is formed around the opening 21 on the back surface side of the second layer wiring board 20.
Then, an adhesive sheet 24b having a thickness of about 0.06 mm is attached near the outer periphery. This second layer wiring board 20 is
It is adhered to the wiring board 10 and the lead frame 30.
Then, after a jig (not shown) is attached to the surface side of the second layer wiring board 20 so that the solder does not adhere to other than a predetermined position, the surface side of the second layer wiring board 20 is brought into contact with the jet solder bath. As a result, the lead frame 30 is easily and firmly fixed to the second-layer wiring board 20 by the solder 22a that has risen in the through hole 22 (see FIG. 2C). Furthermore, the laminated semiconductor chip mounting device is obtained by covering the first opening on the back surface side of the first layer wiring board 10 and adhering the conductor plate 40 via the adhesive layer 41 (FIG. 2 (c)). )reference).

【0015】以上のようにして得られた半導体チップ搭
載装置は、半導体チップを収容する開口部が大小の2段
に形成されているので、これら各段に設けた導体配線を
半導体チップとのワイヤーボンディング接続のボンディ
ング端子として用いることが出来る。従って、1層配線
基板の場合に比べて、同一ピッチの配線を設けることに
より実質2倍の配線ピッチを得ることができ、半導体チ
ップ搭載装置の実装密度を従来の2倍程度に高めること
ができる。また、上記積層タイプの半導体チップ搭載装
置は、配線基板を貼り合わせ、リードフレームを接着剤
層により積層基板に接着させ、この積層基板をはんだ層
に浸漬させることにより製造することができるので、従
来の積層タイプの半導体チップ搭載装置に比べて工程が
簡単なので、非常に安価に提供される。さらに、上記積
層タイプの半導体チップ搭載装置は、良品の配線基板を
選んで、これを積層させるようにしているので、従来の
ものに比べて、製造歩留りが高く、また製品の信頼性も
優れている。
In the semiconductor chip mounting apparatus obtained as described above, the openings for accommodating the semiconductor chips are formed in two steps, large and small. Therefore, the conductor wiring provided in each of these steps is connected to the wire with the semiconductor chip. It can be used as a bonding terminal for bonding connection. Therefore, as compared with the case of the single-layer wiring board, the wiring pitch can be substantially doubled by providing the wirings with the same pitch, and the mounting density of the semiconductor chip mounting device can be increased to about double the conventional one. . In addition, the above-mentioned laminated type semiconductor chip mounting device can be manufactured by bonding the wiring boards, adhering the lead frame to the laminated board with the adhesive layer, and immersing the laminated board in the solder layer. Since the process is simpler than that of the stacked type semiconductor chip mounting device, it is provided at a very low cost. Furthermore, since the above-mentioned laminated type semiconductor chip mounting device selects good wiring boards and stacks them, the manufacturing yield is higher and the product reliability is superior to the conventional ones. There is.

【0016】つぎに、導体板40の半導体チップ搭載部
位40aに半導体チップSを接着剤によりダイボンディ
ングさせる。そして、半導体チップSの電極と第1層配
線基板10の導体配線13および第2層配線基板20の
導体配線23間をワイヤーボンディングにより接続させ
る(図2(d)参照)。半導体チップSの組付けられた
第1層配線基板10を導体板40の外側面を露出させる
ようにして樹脂封止する。このとき、半導体チップ搭載
装置は、リードフレーム30の両面に配線基板を設けて
いるので、モールド金型のゲートから注入されたモール
ド樹脂Rがリードフレーム30の両面に均一に流れる。
そのため、金型内にモールド樹脂が均一に充填されるの
で、ボイド等の欠陥を生じることがなく、信頼性のよい
モールド樹脂層が形成される。さらにリードフレームを
切断し、リードを折り曲げることにより、図3に示すよ
うに、半導体装置の完成品が得られる。
Next, the semiconductor chip S is die-bonded to the semiconductor chip mounting portion 40a of the conductor plate 40 with an adhesive. Then, the electrodes of the semiconductor chip S and the conductor wirings 13 of the first layer wiring board 10 and the conductor wirings 23 of the second layer wiring board 20 are connected by wire bonding (see FIG. 2D). The first layer wiring board 10 with the semiconductor chip S assembled is resin-sealed so that the outer surface of the conductor plate 40 is exposed. At this time, in the semiconductor chip mounting apparatus, since the wiring boards are provided on both sides of the lead frame 30, the molding resin R injected from the gate of the molding die flows evenly on both sides of the lead frame 30.
Therefore, since the mold resin is uniformly filled in the mold, defects such as voids do not occur and a reliable mold resin layer is formed. Further, by cutting the lead frame and bending the leads, a completed semiconductor device is obtained as shown in FIG.

【0017】次に、第2各実施例について図面により説
明する。第2実施例においては、図4に示すように、半
導体チップ搭載部として放熱板を設けず、第1配線基板
50上に設けるようにしたものである。そして、第1配
線基板上に開口部を設けた第2配線基板60を積層させ
るようにしたものである。そして、半導体チップ搭載部
50aに半導体チップSを搭載した後、ワイヤーボンデ
ィングの接続端子を第1配線基板50と第2配線基板6
0に分散して設けることができる。従って、配線基板が
一層の場合に比べて、同一ピッチの配線を設けることに
より、実質2倍程度の配線ピッチのボンディング端子を
得ることができ、半導体チップ搭載装置の実装密度を2
倍程度に高めることができる等、上記第1実施例におい
て得られる効果と同様の効果を得ることができる。本実
施例においては、半導体チップからの放熱があまり問題
にならない場合に特に有効である。また、半導体チップ
搭載部にザグリ加工による凹部(図示しない)を設ける
ようにしてもよい。
Next, a second embodiment will be described with reference to the drawings. In the second embodiment, as shown in FIG. 4, the heat dissipation plate is not provided as the semiconductor chip mounting portion but is provided on the first wiring substrate 50. Then, the second wiring board 60 having the opening is provided on the first wiring board. After mounting the semiconductor chip S on the semiconductor chip mounting portion 50a, the connection terminals for wire bonding are connected to the first wiring board 50 and the second wiring board 6.
It can be dispersed and provided in 0. Therefore, by providing the wirings having the same pitch as compared with the case where the number of wiring boards is one, it is possible to obtain the bonding terminals having the wiring pitch which is substantially doubled, and to increase the mounting density of the semiconductor chip mounting device to 2
It is possible to obtain the same effect as that obtained in the first embodiment described above, such as being able to double the amount. The present embodiment is particularly effective when heat dissipation from the semiconductor chip does not pose a problem. In addition, a recess (not shown) may be provided in the semiconductor chip mounting portion by counterboring.

【0018】なお、上記各実施例においては、1個の半
導体チップを導体板へ搭載した場合について説明してい
るが、複数個の半導体チップを導体板へ搭載させるよう
にしてもよい。また、上記実施例において、半導体チッ
プの代わりに他の電子部品チップを組立てるようにして
もよい。また、上記各実施例においては、リードフレー
ムの両面を配線基板により挟んんで積層させたものであ
るが、この配線基板にさらに開口部の大きさの異なる配
線基板を積層させてもよい。これにより、3段以上の段
差をワイヤーボンディングの接続端子として利用するこ
とができる。さらに、上記各実施例において、配線基
板、リードフレーム、導体板等の形状、材質、数等は目
的用途に応じて適宜変更することができる。
In each of the above embodiments, the case where one semiconductor chip is mounted on the conductor plate has been described, but a plurality of semiconductor chips may be mounted on the conductor plate. Further, in the above embodiment, another electronic component chip may be assembled instead of the semiconductor chip. Further, in each of the above-mentioned embodiments, the lead frame is laminated by sandwiching both sides of the wiring board, but wiring boards having different sizes of openings may be further laminated on this wiring board. Thereby, the steps of three or more steps can be used as connection terminals for wire bonding. Further, in each of the above embodiments, the shape, material, number, etc. of the wiring board, the lead frame, the conductor plate, etc. can be appropriately changed according to the intended use.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に係る半導体チップ搭載装
置の一部を示す斜視図である。
FIG. 1 is a perspective view showing a part of a semiconductor chip mounting apparatus according to a first embodiment of the present invention.

【図2】同半導体チップ搭載装置の組み立て工程におけ
る断面を示す模式図である。
FIG. 2 is a schematic view showing a cross section in the assembly process of the semiconductor chip mounting apparatus.

【図3】同半導体チップ搭載装置を用いた完成状態の半
導体装置の断面を示す模式図である。
FIG. 3 is a schematic view showing a cross section of a semiconductor device in a completed state using the same semiconductor chip mounting device.

【図4】第2実施例に係る半導体チップ搭載装置の一部
を示す断面図である。
FIG. 4 is a sectional view showing a part of a semiconductor chip mounting device according to a second embodiment.

【符号の説明】[Explanation of symbols]

10;第1層配線基板、11;開口部、12;スルーホ
ール、13;導体配線、14;接着剤シート、20;第
2層配線基板、21;開口部、22;スルーホール、2
3;導体配線、24a,24b;接着剤シート、30;
リードフレーム、31a;インナーリード、31b;ア
ウターリード、40;導体板、41;接着剤シート、
S;半導体チップ。
10; First layer wiring board, 11; Opening part, 12; Through hole, 13; Conductor wiring, 14; Adhesive sheet, 20; Second layer wiring board, 21; Opening part, 22; Through hole, 2
3; conductor wiring, 24a, 24b; adhesive sheet, 30;
Lead frame, 31a; inner lead, 31b; outer lead, 40; conductor plate, 41; adhesive sheet,
S: Semiconductor chip.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/46 Q 6921−4E N 6921−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H05K 3/46 Q 6921-4E N 6921-4E

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 外周の近傍位置に複数の第1スルーホー
ルを有した第1配線基板と、 前記第1配線基板より形状が大きく、外周の近傍位置に
複数の第2スルーホールを有し、かつ開口部を設け、前
記第1配線基板の表面側の一部に接着剤層を介して接着
された第2配線基板と、 前記第1配線基板及び第2配線基板の端部間に挟まれた
複数のリードを有し、同複数のリードの内の少なくとも
一部の片面がはんだにより前記第1スルーホールに接合
され、同複数のリードの内の少なくとも一部の反対面が
はんだにより前記第2スルーホールに接合されたリード
フレームとを設けたことを特徴とする電子部品搭載装
置。
1. A first wiring board having a plurality of first through holes in the vicinity of the outer circumference, and a plurality of second through holes having a shape larger than that of the first wiring board and in the vicinity of the outer circumference, In addition, it is sandwiched between a second wiring board provided with an opening and adhered to a part of the front surface side of the first wiring board via an adhesive layer, and an end portion of the first wiring board and the second wiring board. A plurality of leads, at least a part of one surface of the plurality of leads is joined to the first through hole by soldering, and at least a part of the other surface of the plurality of leads is soldering the first surface. An electronic component mounting apparatus, characterized in that a lead frame joined to two through holes is provided.
【請求項2】 外周の近傍位置に複数の第1スルーホー
ルを有した第1配線基板の表面側の外周近傍に設けた接
着剤層を介してリードフレームの複数のリードの内の少
なくとも一部を同第1スルーホール上に配置した状態で
同第1配線基板の表面側に固定させるリードフレーム接
着工程と、 前記リードフレームの接着された第1配線基板の裏面側
から前記第1スルーホールを通してはんだを進入させ、
同第1スルーホールと同リードフレームとの間にはんだ
接合を形成する第1はんだ接合形成工程と、 前記第1配線基板より形状が大きく、外周の近傍位置に
複数の第2スルーホールを有し、かつ開口部を設けた第
2配線基板の裏面側を、接着剤層を介して前記第1配線
基板及び前記リードフレームに接着させる第2配線基板
接着工程と、 前記第2配線基板の表面側から前記第2スルーホールを
通してはんだを進入させ、同第2スルーホールと前記リ
ードフレームとの間にはんだ接合を形成する第2はんだ
接合形成工程とを設けたことを特徴とする電子部品搭載
装置の製造方法。
2. At least a part of a plurality of leads of a lead frame via an adhesive layer provided in the vicinity of the outer periphery on the front surface side of a first wiring board having a plurality of first through holes in the vicinity of the outer periphery And a lead frame bonding step of fixing the same to the front surface side of the first wiring board in a state of being arranged on the first through hole, and through the first through hole from the back surface side of the first wiring board to which the lead frame is bonded. Inject solder,
A first solder joint forming step of forming a solder joint between the first through hole and the lead frame; and a plurality of second through holes having a shape larger than that of the first wiring board and near the outer periphery. A second wiring board adhering step of adhering the back surface side of the second wiring board provided with the opening to the first wiring board and the lead frame via an adhesive layer; and a front surface side of the second wiring board A second solder joint forming step of forming a solder joint between the second through hole and the lead frame by injecting solder through the second through hole. Production method.
JP5354310A 1993-12-30 1993-12-30 Electronic component mounter and its manufacture Pending JPH07202070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5354310A JPH07202070A (en) 1993-12-30 1993-12-30 Electronic component mounter and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5354310A JPH07202070A (en) 1993-12-30 1993-12-30 Electronic component mounter and its manufacture

Publications (1)

Publication Number Publication Date
JPH07202070A true JPH07202070A (en) 1995-08-04

Family

ID=18436688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5354310A Pending JPH07202070A (en) 1993-12-30 1993-12-30 Electronic component mounter and its manufacture

Country Status (1)

Country Link
JP (1) JPH07202070A (en)

Similar Documents

Publication Publication Date Title
US6828661B2 (en) Lead frame and a resin-sealed semiconductor device exhibiting improved resin balance, and a method for manufacturing the same
US6228683B1 (en) High density leaded ball-grid array package
JP3176542B2 (en) Semiconductor device and manufacturing method thereof
JP3310617B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
US8569082B2 (en) Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
US8659146B2 (en) Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
JPH06295962A (en) Electronic part mounting substrate and manufacture thereof as well as electronic part mounting device
JP2001339011A (en) Semiconductor device and its manufacturing method
JP2003017518A (en) Method for manufacturing hybrid integrated circuit device
US5661337A (en) Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages
JP2003017517A (en) Hybrid integrated circuit device and its manufacturing method
US6037662A (en) Chip scale package
JP3478139B2 (en) Lead frame manufacturing method
US20020003308A1 (en) Semiconductor chip package and method for fabricating the same
JP2569400B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JP2622862B2 (en) Substrate for mounting electronic components with leads
JP4038021B2 (en) Manufacturing method of semiconductor device
JP3191617B2 (en) Lead frame and semiconductor device using the same
JP2798108B2 (en) Hybrid integrated circuit device
JP3297959B2 (en) Semiconductor device
JPH07202070A (en) Electronic component mounter and its manufacture
JPH07202069A (en) Electronic component mounter and its manufacture
JP3398556B2 (en) Method for manufacturing semiconductor device
JP2974819B2 (en) Semiconductor device and manufacturing method thereof
JP3251810B2 (en) Mounting method of integrated circuit device