JPH07235604A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can be stably operated even when input-output terminal potential exceeded the range of supply voltage when the device is in operation and also sufficient electrostatic protection effect can be displayed. CONSTITUTION:An N-channel type MOS transistor 38, on which a drain 3e is electrically connected to a VBB terminal 32, a source 35 is electrically connected to an input-output terminal 24, and a gate 37 is electrically connected to a VSS terminal 36, is provided in the title semiconductor device. According to this constitution, as the gate 37 of the N-channel type MOS transistor 38 is fixed to the VSS terminal 36 which is in the lowest potential on the circuit, the N-channel type MOS transistor 38 does not turn ON when the potential of the input/output terminal 34 exceeded the potential of the VBB terminal 32. As a result, the title semiconductor device can be operated stably even when it is used in excess of the potential of VBB terminal 32 of the output/input terminal 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure of an electrostatic protection circuit for protecting a circuit formed on a semiconductor chip against external static electricity.

[0002]

2. Description of the Related Art An integrated circuit semiconductor device is an element that constitutes an integrated circuit by applying static electricity charged to a person or substance to be handled to a semiconductor chip contained in an outer enclosure through external terminal leads. It is easy to cause a so-called electrostatic breakdown failure that destroys the. A diode for absorbing static electricity, a MOS transistor, or a bipolar transistor is connected to the electrode for the input / output bonding pad provided in the peripheral portion of the chip to prevent this electrostatic breakdown through a metal wiring pattern, and this is used as a path. A widely used method is to protect an internal circuit by letting static electricity applied from the outside escape to a power supply terminal (high-potential setting power supply terminal or low-potential setting power supply terminal).

The structure of a conventional protection circuit generally used for preventing electrostatic breakdown will be described with reference to FIGS.

FIG. 3A shows an example of the most general protection circuit, which includes an N-channel MOS transistor 1 and a P-channel MOS transistor.
This is an example in which the channel MOS transistor 2 is applied as an electrostatic protection circuit for protecting the internal circuit 3. In this case, the N-channel MOS transistor 1 has a drain 6 between the input / output terminal 4 used for an input signal or an output signal and a low potential setting power supply terminal (hereinafter referred to as VSS terminal) 5, The circuit is configured so that the source 7 and the gate 8 are electrically connected to the VSS terminal 5. On the other hand, the P-channel MOS transistor 2 has an input / output terminal 4
The drain 10 is electrically connected to the input / output terminal 4 and the source 11 and the gate 12 are electrically connected to the VDD terminal 9 between the high potential setting power supply terminal (hereinafter referred to as the VDD terminal) 9 and the high potential setting power supply terminal 9. The characteristic of this protection circuit configuration is that the potential of the input / output terminal 4 is V when the semiconductor device is used.
As long as it exists between the potential of the DD terminal 9 and the potential of the VSS terminal 5, the N-channel MOS transistor 1 and the P-channel MOS transistor 2 are not turned on.
In other words, even if the potential of the input / output terminal 4 is V
Exceeding the range of the potential of the DD terminal 9 and the potential of the VSS terminal 5 means that the operation of the semiconductor is not allowed.

FIG. 3B shows an example in which the protection circuit is composed of only N-channel MOS transistors, and FIG. 3C shows P.
An example in which only channel MOS transistors are used, as shown in FIG.
FIG. 4A shows an example in which only a normal PN diode 13 is used, and FIG. 4B shows an NPN bipolar transistor 14
And an example of a PNP bipolar transistor 15,
4C shows an example in which only the NPN bipolar transistor 16 is used and FIG. 4D shows an example in which only the PNP bipolar transistor 17 is used. In any protection circuit configuration, FIG.
As in the case of (a), the operation of the semiconductor device requires a constraint that the potential of the input / output terminal 4 must be within the range of the potential of the VDD terminal 9 and the potential of the VSS terminal 5.

[0006]

The miniaturization of semiconductor devices has progressed, and along with this, the movement of lowering the operating voltage is remarkable. Along with this, there is a tendency for malfunctions to occur even with external noise that comes in during use. In particular, the malfunction margin for the signal potential coming from the I / O terminal is protected even if the I / O terminal potential exceeds the power supply voltage range because the usable potential of the I / O terminal due to the protection circuit is limited as described above. It was difficult to secure a sufficient margin so that the circuit would not operate. In addition, as an application, there is a case where the input / output terminal potential exceeds the power supply voltage range, but in this case, a method of removing a part of the protection circuit and configuring the circuit is used. As an example of this, FIG. 4 shows an example of a conventional circuit configuration when the input / output terminal potential is used at a potential higher than the high potential setting power supply terminal potential. FIG. 5 (a)-
(D) shows N-channel MOS transistor 1
8, P-channel MOS transistor 19, normal PN
In this example, the diode 20 and the NPN bipolar transistor 21 are used in a protection circuit.

In either case, no protection circuit is provided between the high potential setting power supply terminal, that is, the VDD terminal 22 and the input / output terminal 23, which is a problem. For this reason, there is a problem of being protected from static electricity applied between the VDD terminal 22 and the input / output terminal 23, and therefore, there is a problem that the static electricity resistance is significantly reduced as compared with the case where it is applied between the low potential setting power supply terminal, that is, the VSS terminal 24. Similarly, FIG. 5 shows a conventional circuit configuration example when the input / output terminal potential is used at a low potential setting power supply terminal potential or less. 6A to 6D are P channel MOs, respectively.
In this example, the S transistor 25, the N-channel MOS transistor 26, the normal PN diode 27, and the NPN bipolar transistor 28 are used in the protection circuit. In either case, no protection circuit is provided between the low potential setting power supply terminal, that is, the VSS terminal 29 and the input / output terminal 30, which is a problem. Therefore, contrary to the case shown in FIG. 5, there is a problem that it is vulnerable to static electricity applied between the VSS terminal 29 and the input / output terminal 30, and the electrostatic withstand capability is lower than that when applied between the VDD terminals 31. As described above, it has been desired to develop a protection circuit in which the semiconductor device operates stably even when the input / output terminal potential exceeds the power supply voltage range and which has a sufficient electrostatic protection effect.

The present invention solves the above-mentioned problems and provides a protection circuit which can be used with the input / output terminal potential exceeding the power supply voltage range and which can dramatically improve the noise margin of the input / output terminal potential. It is an object.

[0009]

In order to solve the above problems, the present invention sets a high potential setting power supply terminal, a low potential setting power supply terminal, and a potential higher than the setting potentials of the high potential setting power supply terminal. In a semiconductor device having an input / output terminal used as an input signal terminal or an output signal terminal, a drain is electrically connected to the high potential setting power supply terminal and a source is electrically connected to the input / output terminal. It has an N-channel MOS transistor whose gates are electrically connected. The high potential setting power supply terminal is electrically connected to the drain, and the low potential setting power supply terminal is electrically connected to the gate and the source. Further, an NPN bipolar transistor is provided in which a collector is electrically connected to the high potential setting power supply terminal, an emitter is electrically connected to the input / output terminal, and a base is electrically connected to the low potential setting power supply terminal. The high potential setting power supply terminal is electrically connected to a collector, and the low potential setting power supply terminal is electrically connected to a base and an emitter.

Further, it has a high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a potential lower than the setting potential of the low potential setting power supply terminal. In semiconductor devices,
A P-channel type MOS transistor having a drain electrically connected to the low potential setting power supply terminal and a source electrically connected to the input / output terminal and a gate electrically connected to the high potential setting power supply terminal is provided. Further, a P-channel type MOS transistor in which a drain is electrically connected to the low potential setting power supply terminal and a gate and a source are electrically connected to the high potential setting power supply terminal is provided. A PNP-type bipolar transistor is also provided in which a collector is electrically connected to the low potential setting power supply terminal and an emitter is electrically connected to the input / output terminal, and a base is electrically connected to the high potential setting power supply terminal. Further, a PNP bipolar transistor in which a collector is electrically connected to the low potential setting power supply terminal and a gate and an emitter are electrically connected to the high potential setting power supply terminal is provided.

[0011]

The present invention has the following functions due to the above-mentioned structure. When the input / output terminal potential exceeds the VDD terminal potential, an N-channel MOS transistor or base whose gate is electrically connected to the VSS terminal is used as a protection circuit for connecting to the high potential setting power supply terminal (hereinafter referred to as VBB terminal). VSS
An NPN bipolar transistor electrically connected to the terminal is used. Therefore, the protection circuit does not turn on even when the input / output terminal potential exceeds the VDB terminal potential. Further, since the static electricity applied between the VBB terminal and the input / output terminal is discharged through this protection circuit, there is no concern that it will be applied to the internal circuit. As a result, the use of input / output terminals having a potential higher than the VBB terminal potential and the electrostatic protection function can be satisfied at the same time.

Further, the input / output terminal potential is VSS and the terminal potential is VSS.
When the potential becomes lower than the terminal potential, a P-channel type MOS transistor whose gate is electrically connected to the VBB terminal or a PNP bipolar transistor whose base is electrically connected to the VBB terminal is used as a protection circuit connected to the VSS terminal. Therefore, the protection circuit does not turn on even when the input / output terminal potential is lower than the VSS terminal potential. Further, since the static electricity applied between the VSS terminal and the input / output terminal is discharged through this protection circuit, there is no fear of being applied to the internal circuit. As a result, the use of input / output terminals having a potential lower than the VSS terminal potential and the electrostatic protection function can be satisfied at the same time.

With the above operation, it is possible to expand the range of potentials used in the input / output terminals of the semiconductor device and secure a noise margin without lowering the electrostatic withstand capability of the semiconductor device.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows an embodiment in which the input / output terminal potential exceeds the VBB terminal potential. FIG. 1A shows the VBB terminal 32.
The drain 33 to the input / output terminal 34 and the source 35 to the V
N electrically connected to the SS terminal 36 and the gate 37, respectively
This is an example in which a channel type MOS transistor 38 is applied.

With the above structure, the gate 37 of the N-channel type MOS transistor 38 is fixed to the VSS terminal 36 which is the lowest potential in the circuit, so that the input / output terminal 34 is
The N-channel type MOS transistor 38 does not turn on even when the potential of the above exceeds the potential of the VBB terminal 32. Therefore, stable operation is possible even when the input / output terminal 34 is used in excess of the potential of the VBB terminal 32. Further, for example, when negative static electricity is applied to the input / output terminal 34 with reference to the VBB terminal 32,
Since the discharge current flows from the VBB terminal 32 to the input / output terminal 34 via the N-channel MOS transistor 38, there is no concern that discharge charge will be added to the internal circuit 39.

In FIG. 1B, the drain 4 is connected to the VBB terminal 40.
1 is an N-channel MOS transistor 45 in which a VSS terminal 42 is electrically connected to a source 43 and a gate 44.
Is an example of applying.

Even in the above structure, since the gate 44 is connected to the VSS terminal 42, the potential of the input / output terminal 46 is V
Even if the BB terminal 40 is exceeded, the N-channel MOS transistor 45 does not turn on. VBB terminal 40 and input / output terminal 4
With respect to static electricity applied between 6, the discharge current is N-channel MOS transistor 45 and N-channel MOS.
Since it flows through the transistor 47, the internal circuit 39
There is no concern that the discharge current will flow to the.

In FIG. 1C, the collector 4 is connected to the VBB terminal 48.
9, the input / output terminal 50, the emitter 51, and the VSS terminal 52
In this example, an NPN bipolar transistor in which the bases 53 are electrically connected to each other is applied. Figure 1 (d)
Is an NPN in which a collector 55 is electrically connected to the VBB terminal 54 and an emitter 57 and a base 58 are electrically connected to the VSS terminal 56.
This is an example in which a bipolar transistor is applied.

In both FIGS. 1C and 1D, the base potential of the NPN transistor is VSS, which is the lowest potential in the circuit.
Since it is fixed to the terminal, the above-mentioned FIG.
The same effect as in the case of (b) can be expected.

FIG. 2 shows an embodiment in which the input / output terminal potential is lower than the VSS terminal. In this case, the gate 60 serves as a protection circuit connected to the VSS terminal 59 and the VBB terminal 6
A PNP bipolar transistor 64 in which a P channel type MOS transistor 62 electrically connected to 1 or a base 63 is electrically connected to a VBB terminal 61 is used.

As a result, the protection circuit does not turn on even if the potential of the input / output terminal 65 drops below the potential of the VSS terminal 59. Further, since the static electricity applied between the VSS terminal 59 and the input / output terminal 65 is discharged through this protection circuit, there is no concern that it will be applied to the internal circuit 66.

2A and 2B, the P channel M
The OS transistor is shown in FIG. 2 (c) and FIG. 2 (d) as a PNP.
An example in which a bipolar transistor is applied is shown. With the above configuration, the use of the input / output terminal having a potential lower than the VSS terminal potential and the electrostatic protection function can be satisfied at the same time.

The NPN type or P type used in the present invention
It goes without saying that the same effect can be expected for both the lateral and vertical NP-type bipolar transistors. However, when formed in a MOS integrated circuit, a lateral bipolar transistor which does not require a new mask is advantageous in terms of process and cost.

In the embodiment shown in FIGS. 1 and 2, the N channel type MOS transistor, the NPN type bipolar transistor, the P channel type MOS transistor, the PNP type bipolar transistor, etc. are bonded for all the input / output terminals on the semiconductor element. By providing the pad around the pad, the electrostatic discharge path can have a low impedance. As a result, the effect of the protection circuit of the present invention can be further enhanced.

[0026]

According to the present invention, when the input / output terminal potential exceeds the power supply voltage range, the function can be satisfied without lowering the electrostatic resistance. Even if the input / output terminal potential does not exceed the rated power supply voltage range,
By applying the present invention, it is possible to secure a sufficient margin for the fluctuation of the input / output terminal potential due to the noise margin. In addition, the application of the protection circuit according to the present invention,
It is most effective to apply it to all the input / output terminals, but the effect can be expected even if it is applied according to the used potential of the input / output terminals.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a protection circuit configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a protection circuit configuration of a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a protection circuit configuration of a conventional semiconductor device.

FIG. 4 is a circuit diagram showing a protection circuit configuration of a conventional semiconductor device.

FIG. 5 is a circuit diagram showing a protection circuit configuration of a conventional semiconductor device.

FIG. 6 is a circuit diagram showing a protection circuit configuration of a conventional semiconductor device.

[Explanation of symbols]

32, 40, 48, 54, 61 High potential setting power supply terminal (VBB terminal) 33, 41 Drain 34, 46, 50, 65 Input / output terminal 35, 43 Source 36, 42, 52, 56, 59 Low potential setting power supply terminal (VSS terminal) 37,44,60 Gate 38,45,47 N-channel MOS transistor 39,66 Internal circuit 49,55 Collector 51,57 Emitter 53,58,63 Base 62 P-channel MOS transistor 64 PNP bipolar transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (16)

[Claims] 1. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a higher potential than the set potential of the high potential setting power supply terminal. A semiconductor device comprising an N-channel MOS transistor in which a drain is electrically connected to the high potential setting power supply terminal and a source is electrically connected to the input / output terminal, and a gate is electrically connected to the low potential setting power supply terminal. A semiconductor device characterized by being provided. 2. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a higher potential than the set potential of the high potential setting power supply terminal. A semiconductor device comprising: an N-channel MOS transistor in which a drain is electrically connected to the high potential setting power supply terminal and a gate and a source are electrically connected to the low potential setting power supply terminal. 3. A semiconductor device according to claim 2, wherein an N-channel type MOS transistor is provided around all the bonding pads for input / output terminals on the semiconductor element. 4. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a higher potential than the set potential of the high potential setting power supply terminal. A semiconductor device comprising an NPN bipolar transistor in which a collector is electrically connected to the high potential setting power supply terminal and an emitter is electrically connected to the input / output terminal, and a base is electrically connected to the low potential setting power supply terminal. A semiconductor device characterized by the above. 5. The semiconductor device according to claim 4, wherein a lateral NPN transistor is used as the NPN bipolar transistor. 6. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a higher potential than the set potential of the high potential setting power supply terminal. A semiconductor device comprising: an NPN in which a collector is electrically connected to the high potential setting power supply terminal and a base and an emitter are electrically connected to the low potential setting power supply terminal.
Type semiconductor device having a bipolar transistor. 7. The semiconductor device according to claim 6, wherein a lateral NPN transistor is used as the NPN bipolar transistor. 8. The semiconductor device according to claim 6, wherein an NPN bipolar transistor is provided around all the input / output terminal bonding pads on the semiconductor element. 9. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a potential lower than a setting potential of the low potential setting power supply terminal. A semiconductor device having a P-channel type MOS transistor in which a drain is electrically connected to the low potential setting power supply terminal and a source is electrically connected to the input / output terminal, and a gate is electrically connected to the high potential setting power supply terminal. A semiconductor device characterized by the above. 10. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a potential lower than a setting potential of the low potential setting power supply terminal. A semiconductor device having a P-channel MOS transistor in which a drain is electrically connected to the low potential setting power supply terminal and a gate and a source are electrically connected to the high potential setting power supply terminal. 11. A semiconductor device according to claim 10, wherein a P-channel type MOS transistor is provided around all the input / output terminal bonding pads on the semiconductor element. 12. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a potential lower than a setting potential of the low potential setting power supply terminal. A semiconductor device having a PNP type bipolar transistor in which a collector is electrically connected to the low potential setting power supply terminal and an emitter is electrically connected to the input / output terminal, and a base is electrically connected to the high potential setting power supply terminal. A semiconductor device characterized by the above. 13. The semiconductor device according to claim 12, wherein a lateral PNP type transistor is used as the PNP type bipolar transistor. 14. A high potential setting power supply terminal, a low potential setting power supply terminal, and an input / output terminal used as an input signal terminal or an output signal terminal set to a potential lower than a setting potential of the low potential setting power supply terminal. A semiconductor device having a PN in which a collector is electrically connected to the low potential setting power supply terminal and a gate and an emitter are electrically connected to the high potential setting power supply terminal.
A semiconductor device comprising a P-type bipolar transistor. 15. The semiconductor device according to claim 14, wherein a lateral PNP transistor is used as the PNP bipolar transistor. 16. The semiconductor device according to claim 14, wherein the PNP bipolar transistor is provided around all the input / output terminal bonding pads on the semiconductor element.