JPH07253962A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to design a microcomputer that can control the DRAM at a higher speed than the conventional arithmetic processing method, and greatly contributes to the speedup and high integration of the entire system. A semiconductor device is provided. A semiconductor device 1 comprising a memory means 2 of a type for multiplex inputting an address and a microcomputer 3, said microcomputer 3
A semiconductor device 1 in which a control means 4 for controlling the operation of the microcomputer 3 is provided, and the microcomputer 3 has a function of outputting address information for accessing the memory means 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure for controlling a memory by using a microcomputer.

[0002]

2. Description of the Related Art Conventionally, various types of semiconductor devices having a built-in system configured to control a memory by using a microcomputer are known, and the type of the microcomputer or the type of the microcomputer. There are various types of memory devices that are externally connected memory means, and there are various types of computing systems configured by combining them.

Among them, DRAM is used quite frequently as a memory means. In the past, the D
A system using a RAM is composed of a DRAM controller for controlling such a DRAM and a microcomputer for controlling the entire system, and is required in a predetermined designed system in recent years. The function is improved year by year, and there is a strong demand for high integration, large amount of arithmetic processing, and high speed, and from this viewpoint, it is necessary to integrate the conventional system into a more compact and one chip. It is coming.

That is, a DRAM controller is built in a one-chip microcomputer to achieve high integration.

[0005]

However, in such a conventional one-chip microcomputer, although the operation speed of the microcomputer is increasing, the improvement in the access speed of the DRAM is delayed, The problem that the access speed of the DRAM cannot keep up with the operation speed of the microcomputer has come to the surface.

A method that has been conventionally adopted to solve the above problem is, for example, to intentionally reduce the operation speed of the microcomputer so that the operation speed of the microcomputer matches the operation speed of the DRAM. Matching is adopted and arithmetic control is executed. That is, the operation speed of the semiconductor device including the microcomputer and the DRAM is restricted by the access speed of the DRAM, and further high speed operation processing cannot be realized.

Therefore, such a method wastes the capacity of the microcomputer and hinders the economical realization of a high-speed arithmetic processing system. It is said that one of the causes is that it takes time to process the address signal when accessing predetermined information in the DRAM. An object of the present invention is to solve the problems in the prior art and to provide a semiconductor device having a function of accessing predetermined information in a DRAM memory at high speed.

[0008]

In order to achieve the above-mentioned object, the present invention basically provides a semiconductor device adopting the technical constitution as described below.
That is, the semiconductor device according to the present invention is a semiconductor device composed of a memory means of a type for multiplex inputting an address and a microcomputer, and a control for controlling the operation of the microcomputer in the microcomputer. Means are provided, and the microcomputer device has a function of outputting address information for accessing the memory means in the microcomputer.

A more specific mode of the semiconductor device according to the present invention is, for example, a semiconductor device including a memory means of a type for multiplex inputting an address and a microcomputer. A control means for controlling the operation of the microcomputer is provided in the control means, and the control means determines the access time to the predetermined information in the memory means based on the address information provided in the microcomputer. The semiconductor device is configured to control.

[0010]

Since the semiconductor device according to the present invention has the technical structure as described above, it is a specific example of a memory means of a type for inputting an address in multiplex.
In the case of accessing the information contained in the AM, the predetermined address information is input from the outside via the row decoder and the column decoder to access the predetermined information, whereas in the present invention, In addition to providing internal address information on the microcomputer side, it has a built-in address information output function for accessing predetermined information recorded in a DRAM, which is one of the memory means, at high speed in a short time. Therefore, the memory means can respond only to the address information from the microcomputer, so that the predetermined information recorded in the memory means can be accessed at high speed, and therefore the operation of the entire system can be performed. The speed will be greatly improved.

In the semiconductor device according to the present invention,
The control signal including the address information output from the microcomputer to the memory means includes the control signal for causing the memory means to execute the arithmetic processing in the high speed page mode, and as a result, the memory means. In this case, for example, when the row address signal at each address clock is constant, only the column address signal is processed without outputting the row address signal. Since it is possible to increase the operating speed, it greatly contributes to the improvement of the operation speed of the semiconductor device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor device according to the present invention will be described in detail below with reference to the drawings. That is, FIG. 1 is a block diagram for explaining the outline of the configuration of a specific example of a semiconductor device according to the present invention, and in the figure, it is composed of a memory means 2 of a type for multiplex inputting an address and a microcomputer 3. The semiconductor device 1 includes a control means 4 for controlling the operation of the microcomputer 3 in the microcomputer 3, and an address for accessing the memory means 2 in the microcomputer 3. A semiconductor device 1 having a function of outputting information is shown.

In the semiconductor device 1 according to the present invention, the microcomputer 3 and the memory means 2 may be arranged on the same substrate and formed in one chip. It may be arranged individually.
The memory means 2 used in the present invention needs to be a DRAM, and above all, it is necessary to use a DRAM of a type in which addresses are multiplexed.

Further, the microcomputer 3 in the semiconductor device 1 according to the present invention is provided with an operation block (CPU block) 5 in addition to the control means 4 described above, and further, the operation block. The (CPU block) 5 is provided with an address control circuit 6 containing address information for accessing various information stored in the memory means 2.

Further, as will be described later, the control means 4 provided in the microcomputer 3 according to the present invention is as follows.
It is desirable to have a function of outputting address information for accessing the memory means 2 and at the same time have a function of controlling an access time to predetermined information in the memory means 2. To more specifically explain such a function, from the address information built in the address control circuit 6 of the microcomputer 3, row address information, for example, / RAS (RAS bar) signal or column address information / CAS ( Based on the information of at least one of the (CAS bar) signal, the arithmetic processing of the microcomputer 3 is controlled so as to shorten the access time to the predetermined information in the memory means 2.

That is, in the present invention, in order to solve the above-mentioned conventional problems, the microcomputer 3 side positively stores predetermined information stored in the DRAM as the memory means 2. Of the conventional memory means 2 while being configured to output an address information signal for accessing
When reading the specified information from the DRAM in
Since the address information of both the row address signal, that is, / RAS (RAS bar) and the column address signal, that is, / CAS (CAS bar) is used, a certain access time was required, but in the present invention. In this case, each time the internal address clock signal is output, the predetermined address information is accessed using the address information of both the row address decoder and the column address decoder. Even if one of the two indicates the same address, it is necessary to read the address information of both of the above, so extra access time is used accordingly.

Therefore, in the present invention, address information is built into the address control circuit 6 provided on the side of the microcomputer 3 and the control means 4 is used to store both of the address information. If one of the addresses indicates the same address, and the subsequent address information is accessed, the same address information is not accessed, so that the memory means DR
The predetermined information is read from the AM at high speed in a short time.

In this case, it is arbitrary which of the column address information and the row address information is used as the key information. In the embodiment of the present invention described below, the row address signal, that is, / RAS (RAS bar). ) The above control is executed while using a signal as key information. That is,
More specifically, by the control means 4 in the present invention,
The control of the access time to the predetermined information in the memory means 2 is performed by using address information contained in the microcomputer 3, row address information or column address information, which are adjacent to each other. Comparing the address information with each other in synchronization with the address clock, and controlling the microcomputer 2 so as to shorten the access time to the predetermined information in the memory means when the address information matches. Is.

In this control method, as an example, the high speed page mode processing held by the DRAM which is the memory means 2 is executed by the control address signal from the microcomputer 3. That is, the control for shortening the access time to the predetermined information in the memory means 2 by the control means 4 in the present invention is the high speed page mode control.

In order to carry out such control, an address comparison circuit for inputting address information output from the address control circuit 6 provided in the arithmetic block (CPU block) 5 is input to the control means 4 in the present invention. 7 and the output of the address comparison circuit 7 as input, and the output from the high speed page mode determination circuit 8 as input, and controls address information from the arithmetic block (CPU block) 5. And a control circuit 12 for controlling the control circuit 12. The control circuit 12 is provided with a / RAS (RAS bar) control circuit 9, a / CAS (CAS bar) control circuit 10 and an address control circuit 11. desirable.

Further, each of the / RAS (RA in the present invention
The respective control output signals from the S bar) control circuit 9, the / CAS (CAS bar) control circuit 10 and the address control circuit 11 are the / RAS (RAS bar) signal input terminal / RAS (RAS bar) in the memory means 2. ), / CAS
(CAS bar) signal input terminal / CAS (CAS bar) and address signal input terminal ADD, respectively.

That is, as is apparent from FIG. 1, the address control circuit 6 in the arithmetic block (CPU block) 5
The address signal (for example, a 16-bit signal) output from is compared by the address comparison circuit 7, and the high speed page mode determination circuit 8 determines whether or not to set the high speed page mode. Then, the judgment result is used as a calculation block (C
When the calculation block (CPU block) 5 recognizes the judgment result as the high-speed page mode by feeding back to the PU block) 5, the calculation block (CPU block) 5
Executes the arithmetic processing operation in the specified number of cycles and executes the high speed page mode / RAS (RA
The S bar signal, the / CAS (CAS bar) signal and the address control signal are output from the microcomputer 3 to the memory means 1.

An example of a data access method in the fast page mode in the multiplex input type DRAM which is the memory means 2 used in the present invention will be described with reference to FIG. FIG. 2 is a timing chart showing signal waveforms in the high speed page mode control described above.

The access to the DRAM in the normal arithmetic processing is set to the same DRAM access period at a timing slightly delayed from the timing of the address signal, and within that period, the row address signal and the column address must be used. Signals are what is accessed. On the other hand, in the high speed page mode processing, the first address information out of the address information ADD output from the address control circuit in the operation block (CPU block) 5 in synchronization with an internal address clock (not shown). When n is output, the DRAM slightly delayed from the timing
The access period is set, and / RAS (RAS
The low address information signal is output to the address terminal ADD of the microcomputer 3 and then / CAS (CAS bar) becomes the "L" level, so that the address terminal ADD of the microcomputer 3 is changed. A column address information signal is output to. After that, the second address information n + 1 is output in synchronization with the next internal address clock, but / RAS (RAS bar)
Remains at the "L" level, the row address information signal is not output to the address terminal ADD of the microcomputer 3, and then / CAS (CAS bar) becomes "L".
When the level becomes the level, only the column address information signal is output to the address terminal ADD of the microcomputer 3.

Therefore, at the time of this internal address clock, the row address signal is not read out, and only the column address signal is read out.
The RAM access period will be shorter than the normal DRAM access period. Similarly, the third and fourth address information n + 2 and n + 3 are sequentially output in synchronization with the internal address clock, but / RAS (RA
Since the S bar) is maintained at the "L" level, only the column address information signal is output to the address terminal ADD of the microcomputer 3. Then, by supplying the address information signal to the DRAM 1,
The access time for the predetermined information stored in M is shortened.

When the high speed page mode processing is executed by the semiconductor device 1 according to the present invention, as shown in FIG. 3, / RAS at the time of outputting the last internal address clock is synchronized with the internal address clock. (RAS bar) signal and / RA when outputting internal address clock this time
Compared with the S (RAS bar) signal, both / RAS
If the (RAS bar) signals match, the / RAS
If the address information signal is supplied to the DRAM by keeping the (RAS bar) signal at the "L" level, the DRAM judges that it is the high speed page mode processing and accesses only the column address signal. become.

That is, at the timing A in FIG. 3, as a result of comparing the address information n in the DRAM access period and the address information n + 1 in the DRAM access period, both / RAS (RAS bar) signals are obtained. Therefore, the cycle during the DRAM access period is processed in the fast page mode. Further, as a result of comparing the address information n + 1 in the DRAM access period with the address information n + 2 in the DRAM access period at the timing B in FIG.
Since the S (RAS bar) signals match, the cycle of the DRAM access period is also processed in the high speed page mode.

Further, at timing C in FIG. 3, address information n + in the DRAM access period
2 and address information n + in the DRAM access period
As a result of comparison with 3, the / RAS (RAS bar) signals of both are inconsistent, so in this cycle, / RAS
Since the (RAS bar) signal is raised to "H" level and the high speed page mode processing is stopped and the processing is executed in the normal arithmetic processing cycle, the cycle of the DRAM access period becomes the same cycle as the DRAM access period.

Next, a specific example of the address comparison circuit 7 used in the semiconductor device 1 according to the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing the configuration of a specific example of the address comparison circuit 7 used in the present invention, in which the address information output from the address control circuit 6 of the operation block (CPU block) 5 is input. Latch circuit 7 connected to the input terminal IN1
1 and the address information n output at the last internal address clock timing latched by the latch circuit 71 and the address information n + 1 at the current internal address clock are compared to see if they match. An exclusive OR (E-OR) circuit 72 for determining whether or not
The input of the output of the exclusive OR (E-OR) circuit 72 and the signal ADE indicating the address coincidence detection period output from the operation block (CPU block) 5
And an R circuit 73.

A signal A indicating the address coincidence detection period
DE is assumed to be active at "L" level.
Further, in the exclusive OR (E-OR) circuit 72, for example, of two pieces of address information that are continuously output, for example, both / RAS (RAS bar) signals are the same. In this case, the exclusive OR (E-O
The R) circuit 72 outputs an "L" level signal. Therefore, if the signal (ADE) indicating the address coincidence detection period is at "L" level and the output of the exclusive OR (E-OR) circuit 72 is also at "L" level, the NOR circuit 73 outputs " An H "level signal is output, and this signal is used as a signal indicating address matching.

The address comparison circuit 7 according to the present invention.
In the configuration of the latch circuit 71 used for, the three inverters INV1 to INV3 are connected and wired as shown in FIG. 4, and the address latch signals C and CX are input to the inverters INV1 and INV2. Is. As the circuit for generating the address latch signals C and CX in the present invention, for example, a circuit having a configuration as shown in FIG. 5 can be used. Specifically, the arithmetic block (CPU block) 5 Internal address clock 2 (A
DCLOCK2) and an internal clock INCLOCK are input to the NAND gate circuit 74 and an inverter INV4 to which the output of the NAND gate circuit 74 is input. The address latch signal CX is output from the output of the NAND gate circuit 74. The inverter IN
The address latch signal C is output from the output of V4.

FIG. 6 is a drive timing chart of the semiconductor device 1 according to the present invention using the address comparison circuit 7.
Shown in. As is clear from FIG. 6, the address clock 1
The address information output to the internal address bus (ADDBUS) is output in synchronization with (ADCLOCK1), and the address information output to the internal address bus (ADDBUS) is output in synchronization with the address clock 2 (ADCLOCK2).
The data is latched (ADLATCH) in the latch circuit 71 of FIG. 4 with a predetermined delay time.

On the other hand, the address clock (ADCLO
Address match detection signal (ADE) in synchronization with CK1)
Is output, the address information is compared in the address comparison circuit 7, and two consecutive pieces of address information, for example, /
If it is determined that the RAS (RAS bar) signals match each other, the address match signal (ADICH) is output, and the high speed page mode process is started.

Next, a configuration example of the high speed page mode determination circuit 8 used in the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a block diagram showing an example of the configuration of the high speed page mode determination circuit 8 used in the present invention, in which the address match signal (ADICH) output from the address comparison circuit 7 and the internal clock ( INCLOCK) is input to the NAND gate circuit 81, a reset terminal RX to which the output of the NAND gate circuit 81 is input, and a signal (PAGEND) indicating the end of high-speed page mode processing described later are input. Flip-flop 8 having terminal SX
When the address match signal (ADICH) signal is output, an "H" level signal is output from the QX terminal of the flip-flop 82 in synchronization with the internal clock (INCLOCK). Become a signal.

On the other hand, in the above circuit, the high speed page mode processing end signal (PAGEND) may be one that uses the circuit 83 having the structure as shown in FIG. 8, for example. Page mode processing end signal (P
The AGEND) generation circuit 83 includes an inverter INV5 to which the address match signal (ADICH) is input, a NOR gate circuit 84 to which the output of the inverter INV5 and the signal (ADE) indicating the address match detection period are input, and The NAND gate circuit 85 receives the output of the NOR gate circuit 84 and the internal clock (INCLOCK).

The high speed page mode processing end signal (PA
When the signal (ADE) indicating the address match detection period which is active at the “L” level is output, when the address match signal is not output, the (GEND) generation circuit 83 of the NOR gate circuit 84. Output is "H"
The NAND gate circuit 85 outputs the high-speed page mode processing end signal (PAGEND) during the "H" level period of the internal clock.

The high speed page mode processing end signal (PA
(GEND) is input to the set terminal SX of the flip-flop 82, and as a result, the QX terminal of the flip-flop 82 becomes "L" level, and the high speed page mode processing is completed. The signal (HSM) indicating the high-speed page mode processing output from the flip-flop 82 of the high-speed page mode determination circuit 8 is returned to the operation block (CPU block) 5, and the microcomputer 3 is in the high-speed page mode. It will be recognized that the DRAM is accessed.

FIG. 9 shows a drive timing chart of the semiconductor device 1 according to the present invention using the high speed page mode determination circuit 8. As is apparent from FIG. 9, the address information is output to the internal address bus (ADDBUS) in synchronization with the address clock (ADCLOCK), and is output to the internal address bus (ADDBUS) in synchronization with another address clock (ADCLOCK). The generated address information is latched (ADLATCH) in the latch circuit 71 of FIG. 4 with a predetermined delay time.

When the signal (ADE) indicating the address match detection period is output in synchronization with the internal clock C1, the address comparison circuit 7 described above operates and the address match signal (ADICH) is output. As a result, A signal (HSM) indicating the high speed page mode processing is output. On the other hand, a signal (ADE) indicating the next address match detection period is output in synchronization with the next internal clock C2.
Since the address coincidence signal (ADICH) is not output, as a result, the high speed page mode processing end signal (PA
GEND) is output, and subsequently, the signal (HSM) indicating the high-speed page mode processing becomes "L" level.

On the other hand, the / RAS (RAS bar) control circuit 9, / CAS of the control circuit 12 used in the present invention.
(CAS bar) control circuit 10 and address control circuit 11
A specific example of the above will be described with reference to FIGS. That is, the / RAS (RAS bar) control circuit 9 in the present invention
10 may have a configuration in which two inverters INV6 and INV7 as shown in FIG. 10 are arranged in series as shown in FIG.
Output from the operation block (CPU block) 5 of the microcomputer 3 to the input terminal of NV6 / RAS (R
The original signal of the (AS bar) signal is input and the inverter I
The output terminal of NV6 is connected to the input terminal of the inverter INV7.
A signal is output.

In addition, in such a circuit configuration, the inverter I
The NV6 has an internal clock (INC) as shown in FIG.
LOCK inverted signal and address match signal (ADIC)
NAND gate circuit 11 to which the inverted signal of H) is input
1 and an inverter INV8 to which the output of the NAND gate circuit 111 is input, and a RAS output clock CR output from the output of the inverter INV8
And the inverted signal CRX of the RAS output clock CR extracted from the output of the NAND gate circuit 111 is input to the inverter INV6.

Therefore, the address match signal (ADICH)
Is output, the inverted signal of the internal clock is “H”.
During the level period, the / RAS (RAS bar) output clock CR and the inverted signal CRX of the / RAS (RAS bar) output clock CR are not output, and therefore / RA
The S (RAS bar) signal is not output. On the other hand, when the address match signal is not output, the above / RAS
(RAS bar) Output clock CR and / RAS (RAS
Since the inverted signal CRX of the output clock CR) is output, the / RAS (RAS bar) signal changes.

Further, the configuration of the / CAS (CAS bar) signal control circuit 10 is also substantially the same as that of the / RAS (RAS bar) signal control circuit 9 as shown in FIG.
It is composed of an inverter INV9 to which the original signal of the S signal is input and an inverter INV10 connected in series to the inverter INV9, and a CAS signal is output from the output of the inverter INV10.

Further, in the inverter INV9, the CAS output clock C which is the output of the inverter INV12 in the circuit constituted by the two stages of inverters INV11 and INV12 for the internal clock, and the inverter INV11.
Since the inversion signal CX of the CAS output clock C output from is input, the / CAS (CAS bar) signal control circuit 10 is latched and output to the outside every cycle of the internal clock. .

Next, FIG. 13 shows an example of the configuration of the address control circuit 11 used in the present invention. That is, 3
A plurality of inverters INV13 to INV15 are arranged and connected as shown, and a latch circuit 131 and an output of the latch circuit 131 are connected in series to an inverter I.
The output of the NV16 is connected to the input terminal of the inverter INV17 having an address output terminal, and the output of another inverter INV18 is input to the input terminal of the inverter INV17.

A row address signal is input to the input terminal of the latch circuit 131, and a column address signal is input to the input terminal of the inverter INV18. Further, the inverter INV13 and the inverter INV15 of the latch circuit 131 are controlled by the internal clock signal C and its inverted signal similarly to the above-mentioned latch circuit, and the inverter INV16 and the inverter INV18 are the address switching signal AC and its inverted signal. It is configured to be controlled by ACX.

Further, the inverter INV17 has an internal clock signal C indicating an address latch signal and its inverted signal CX.
Are controlled by. Therefore, in the high-speed page mode, the address switching signal AC becomes "H" level, the column address signal is output from the output terminal of the inverter INV17 to the outside, while when the address switching signal AC is "L" level, Latch circuit 131
The row address signal latched by the
Output from the output terminal of NV17 to the outside, and as a result, D
The address information in the multiplex output format is output to the RAM.

The address control circuit 11 may be provided in the arithmetic block (CPU block) of the microcomputer 3 or may be executed by another block. FIG. 14 shows a timing chart of the entire control signal of the semiconductor device according to the present invention.

The timing chart of FIG. 14 is basically the same as that described with reference to FIG. 2 and FIG. 6 or FIG. 9, and a detailed description thereof will be omitted. Each timing chart up to the mode end signal shows each operation waveform in the above-mentioned address comparison circuit 7, and / RAS (RAS bar) 7 in the figure.
Each timing chart from the original signal of the signal to the address output clock signal of 12 shows the operation waveform of each control circuit in the control means 12 described above.
The timing charts from the / RAS (RAS bar) signal of 3 to the address output signal of 15 are respectively / RAS
(RAS bar), / CAS (CAS bar) and output waveforms of the address output terminal.

As is apparent from FIG. 14, in this embodiment, a normal DRAM is used for DRAM access.
Access is executed, and in DRAM access,
High speed page mode signal is output, resulting in / RAS
The (RAS bar) signal is not output, and only / CAS (CAS bar) signal is output. Therefore, the access in the fast page mode is executed, and the access time is shortened during that time. Further, in the DRAM access, by outputting the high speed page mode end signal (PAGEND), the high speed page mode is released and the normal DRAM access is executed.

Next, an example of the operation procedure of the above-described semiconductor device according to the present invention will be described with reference to the flow chart shown in FIG. First, after the start, in step (1), it is determined whether or not the information to be accessed is the DRAM area. If NO, the process proceeds to step (2) to store data in areas other than the DRAM. Although it is accessed, if YES, the internal clock n is selected and the row address signal corresponding to the selected clock is read in step (3). Next, in step (4), the row address signals of the internal clocks n and n + 1 are compared.

In step (5), it is judged whether or not the current row address signal and the previous row address signal match, and if NO, the process proceeds to step (6) and normal DRAM access is performed. If YES, the high speed page mode process is executed in step (7). After the column address signal is output in step (8), the process proceeds to step (9), the address switching signal is output, and in step (10), the internal clock n is set to n + 1, and step (11) At, it is determined whether or not the data has ended, and if NO, the process returns to step (3), and the operation of each process described above is repeated, but if YES, it becomes END.

In the embodiment of the present invention described above, the decision to switch to the high speed page mode is made based on whether the address match signal (ADICH) is output or not. For example, as shown in FIG. 16, the calculation block (C
It is also possible to use the signal indicating the instruction fetch output from the PU block) 5 so that the signal indicating the instruction fetch is input to the high-speed page mode determination circuit 8 and executed. It may be executed by using a signal that does not indicate instruction fetch, which is an inverted signal of the signal shown.

Further, in the present invention, the control of the shortening of the access time by the control means 4 may be executed by using a signal indicating an address jump, and the refresh of the memory may be performed. It may be executed by using the signal shown. Further, in the present invention, the shortening control of the access time by the control means 4 is
It may be executed by using a signal indicating that the column address has overflowed, or may be executed by using an internal interrupt request signal.

Further, also at the end of the high speed page mode operation in the present invention, it is possible to use a signal indicating the high speed page mode determination signal output period instead of using the above signal indicating the address coincidence detection period. .

[0056]

Since the semiconductor device according to the present invention uses the technical configuration as described above, it is necessary to design a microcomputer capable of controlling the DRAM at a higher speed than the conventional arithmetic processing method. It becomes possible to contribute to the high integration of the whole system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 2 is a timing chart of high speed page mode control used in the present invention.

FIG. 3 is a timing chart illustrating the operating principle of the semiconductor device according to the present invention.

FIG. 4 is a block diagram showing a configuration of a specific example of an address comparison circuit used in a semiconductor device according to the present invention.

5 is a block diagram showing an example of an address latch signal generation circuit used in the latch circuit shown in FIG.

FIG. 6 is a timing chart showing an example of driving the semiconductor device according to the present invention.

FIG. 7 is a block diagram showing a configuration of a specific example of a high speed page mode determination circuit used in the semiconductor device according to the present invention.

FIG. 8 is a block diagram showing a configuration of a specific example of a circuit for generating a high speed page mode end signal.

FIG. 9 is a timing chart showing an operation in a high speed page mode in the semiconductor device according to the present invention.

FIG. 10 is a block diagram showing a configuration of a specific example of a / RAS (RAS bar) signal control circuit used in the semiconductor device of the present invention.

FIG. 11 is a diagram illustrating a / RAS (RAS bar) used in the / RAS (RAS bar) signal control circuit shown in FIG. 10;
3 is a block diagram showing an example of an output clock signal generation circuit.

12A is a block diagram showing a configuration of a specific example of a / CAS (CAS bar) signal control circuit used in the semiconductor device of the present invention, and FIG.
2 (B) is used in the / CAS (CAS bar) signal control circuit shown in FIG. 12 (A) / CAS (CAS bar)
3 is a block diagram showing an example of an output clock signal generation circuit.

FIG. 13 is a block diagram showing a configuration of a specific example of an address control circuit used in the semiconductor device of the present invention.

FIG. 14 is a timing chart for explaining the overall operation of the semiconductor device according to the present invention.

FIG. 15 is a flowchart showing an example of the operation procedure of the semiconductor device according to the present invention.

FIG. 16 is a block diagram illustrating another configuration example of the high speed page mode determination means in the semiconductor device according to the present invention.

[Description of Reference Signs] 1 ... Semiconductor device 2 ... Memory means, DRAM 3 ... Microcomputer 4 ... Control means 5 ... Operation block (CPU block) 6 ... Address control circuit 7 ... Address comparison circuit 8 ... High-speed page mode determination circuit 9 ... / RAS (RAS bar) control circuit 10 ... / CAS (CAS bar) control circuit 11 ... Address control circuit 12 ... Control circuit

Claims (12)

[Claims] 1. A semiconductor device comprising a memory means of a type for multiplex inputting an address and a microcomputer, wherein a control means for controlling the operation of the microcomputer is provided in the microcomputer. And in the microcomputer,
A semiconductor device having a function of outputting address information for accessing the memory means. 2. A semiconductor device comprising a memory means of a type for multiplex inputting an address and a microcomputer, wherein a control means for controlling the operation of the microcomputer is provided in the microcomputer. The semiconductor device is characterized in that the control means is configured to control an access time for predetermined information in the memory means based on address information provided inside the microcomputer. 3. The memory means for multiplex inputting the address is a DRAM.
Alternatively, the semiconductor device according to item 2. 4. The control of the access time to the predetermined information in the memory means by the control means is at least one of row address information and column address information from the address information built in the microcomputer. 4. The device according to claim 1, which has a function of controlling a microcomputer so as to shorten access time to predetermined information in the memory means based on one information. Semiconductor device. 5. The control means controls the access time to predetermined information in the memory means, based on address information contained in the microcomputer, either row address information or column address information. Address information that is adjacent to each other and is compared with each other in synchronization with the address clock, and if the address information matches, the access time to the predetermined information in the memory means is shortened. The semiconductor device according to claim 4, wherein the semiconductor device controls a microcomputer. 6. The control according to any one of claims 1 to 5, wherein the control by the control means for shortening the access time to the predetermined information in the memory means is a high speed page mode control. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the control for shortening the access time by the control means is executed by using a signal indicating an instruction fetch. apparatus. 8. The control for shortening the access time by the control means is executed by using a signal which does not indicate instruction fetch. Semiconductor device. 9. The semiconductor device according to claim 1, wherein the control for shortening the access time by the control means is executed by using a signal indicating an address jump. apparatus. 10. The control for shortening the access time by the control means is executed by using a signal indicating a refresh of the memory. Semiconductor device. 11. The control for shortening the access time by the control means is executed by using a signal indicating that a column address has overflowed. The semiconductor device according to. 12. The semiconductor according to claim 1, wherein the control for shortening the access time by the control means is executed by utilizing an internal interrupt request signal. apparatus.