JPH07268663A - Formation of capacitor insulating film, formation of semiconductor memory device and apparatus for producing semiconductor - Google Patents

Abstract

PURPOSE:To easily form a capacitor insulating film in the case of increasing of the capacitance of the capacitor insulating film by forming ruggedness therein without expanding the capacitor area. CONSTITUTION:A silicon film (not shown in Fig.) is formed on a silicon oxidized film 21a by passing gaseous SiH4 at a gas flow rate of 150sccm under a pressure condition of 0.2Torr. The forming temp. is set at 575 deg.C. The sample is annealed at about 600 deg.C in a vacuum atmosphere. Consequently, the rough surface polycrystalline silicon film having surface ruggedness is obtd. The film is subjected to ion implantation of arsenic ion (<75>As<+>) under conditions of acceleration energy of 30KeV and dose quantity of 5X10<15>ion/cm<2>. The silicon oxidized film 21c is selectively etched by using the ion implanted film as an etching mask, by which recessed parts 27 are obtd. The polycrystalline silicon film 29 is formed on the silicon oxidized film 21c already formed with the ruggedness, by which the ruggedness is transferred onto the film 29. The film 29 is subjected to a nitriding treatment after removal of the silicon oxidized film 21c, by which the capacitor insulating film is obtd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor insulating film, a method for forming a semiconductor memory device using the same, and an apparatus suitable for implementing these.

[0002]

2. Description of the Related Art In order to achieve high integration of, for example, a DRAM (Dynamic Random Access Memory) while satisfying desired electrical characteristics, a capacitor exhibiting a desired capacitance can be formed without expanding the plane area of the capacitor. Is important. As a conventional technique that can satisfy this demand, for example, Document I (Extended Abstracts of the 21st Confere
nce on Solid State Devices and Materials, Tokyo, 198
8, pp.137-140).
In this method: A mixture of spin-on-glass (SOG) and a resist is applied on a storage node polysilicon layer as an electrification storage electrode (storage node) which becomes one electrode of a capacitor. : Next, bake this sample at a temperature of 160 ° C. : Next, this sample is placed in a hydrofluoric acid buffer solution to selectively etch SOG.
: In this etching, the resist remains and the part that was SOG becomes a hole. Next, the resist part is used as an etching resistant mask to etch the storage node polysilicon layer by anisotropic etching to form a recess in the layer. Many are formed. As a result, irregularities are formed in the storage node polysilicon layer. Next, the surface of the polysilicon layer having the irregularities is oxidized, for example, to form a capacitor insulating film on the surface. The capacitor insulating film formed in this way has an effective area increased due to the presence of irregularities even if it has the same plane area, so that the capacitance of the capacitor is approximately doubled as compared with the case where there is no irregularity.

[0003]

However, in the above-mentioned conventional method, a mixture of spin-on-glass (SOG) and a resist is applied on the storage node polysilicon layer, then this sample is baked, and then this sample is baked. It is said that the process of obtaining the etching resistant mask is complicated, such that the sample is placed in a hydrofluoric acid buffer solution to selectively etch the SOG, and the resist not removed by this etching is used as the etching resistant mask. There is a problem. Therefore, a new technology to replace this is desired.
As one hint for realizing this new technique, the inventor of the present application discloses, for example, Document II (Journal of Applied Physics, Vol. 61, No. 11 (1992), pp. 1147).
Attention was paid to the technology disclosed in -1151). What is this technology?
By devising the conditions for forming the polycrystalline silicon layer, a polycrystalline silicon film (hereinafter, referred to as "rough-faced polycrystalline It is a technology for forming a "silicon film". And when the base is etched after forming this rough surface polycrystalline silicon film on the base material that is the object to be etched, it is thought that the granular portion of the rough surface polycrystalline silicon film may function as an etching resistant mask,
As a result, it was considered that the irregularities of the rough-surface polycrystalline silicon film might be transferred to the base. Therefore, the inventor of this application forms a rough-surface polycrystalline silicon film on a silicon oxide film, and then uses a dry etching device (specifically, a parallel plate type reactive ion etching device) to form this silicon oxide film. I tried etching the film. But,
In this case, it was not possible to transfer the irregularities of the rough-surface polycrystalline silicon film to the silicon oxide film as expected. It is considered that the thin film portion between the granular portions of the rough-surface polycrystalline silicon film also functions as an etching resistant mask. Therefore, this time, an attempt was made to etch the underlayer under the condition that the selection ratio of the underlying silicon oxide film to the polycrystalline silicon during etching is lowered (that is, under the condition that the rough-surfaced polycrystalline silicon film is easily etched). However, it has been found that under such conditions, even the granular portion of the rough-surface polycrystalline silicon is etched at an extremely high speed. Therefore, it was necessary to further devise the rough surface polycrystalline silicon film as an etching mask. In addition to the method of using the rough-surface polycrystalline silicon film as an etching mask, it is desirable to have a method of easily forming irregularities on the capacitor insulating film.

[0004]

Therefore, according to the first invention of this application, as a method for obtaining a capacitor insulating film,
(A) a step of forming a rough surface polycrystalline silicon film having an uneven surface on an underlayer; (b) a step of irradiating the rough surface polycrystalline silicon film with energetic particles; This rough surface polycrystalline polysilicon film that has been irradiated is used as an etching resistant mask, and a step of etching the base to form irregularities on the base, and (d) separately performing capacitor insulation on the base on which the irregularities are formed. A method including a step of forming a film for forming a film and transferring unevenness of a base to the film for forming a capacitor insulating film to obtain a capacitor insulating film.

Further, according to the second invention of this application, as another method for obtaining the capacitor insulating film, the above-mentioned (a),
Instead of the steps (b) and (C), (i) on the base,
Providing a step of growing tungsten nuclei so that they are scattered on the base, and (ii) using the tungsten nuclei as an etching resistant mask to etch the base to form irregularities on the base. Is characterized by.

[0006]

According to the first invention of this application, it is considered that the surface layer portion of the rough-surface polycrystalline silicon film is modified by the irradiation of energetic particles. Then, the function of the modified portion as an etching resistant mask is considered to deteriorate. Here, since the grain portion of the rough-surface polycrystalline silicon film is thicker in the granular portion than in the portion between the granular portions, the inside of the granular portion still has a property as an etching resistant mask even when the energetic particles are irradiated. While maintaining
It is considered that the portion between the granular portions becomes a modified portion that does not function as an etching resistant mask as a whole.

Further, in the second invention, since the base of the tungsten can be selectively etched by using the scattered tungsten nuclei as an etching resistant mask, unevenness is formed on the base according to the distribution of the scattered tungsten nuclei. .

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a capacitor insulating film according to the present invention, a method for forming a semiconductor memory device using the same, and respective embodiments of a semiconductor device suitable for implementing these will be described below with reference to the drawings. It should be noted that the drawings used in the description merely schematically show the dimensions, shapes, and arrangement relationships of the respective constituent components to the extent that the present invention can be understood. Further, in each of the drawings used for description, the same components are denoted by the same reference numerals. Further, it should be understood that the conditions described in the following description, such as numerical conditions, are examples within the scope of the present invention, and the present invention is not limited to these conditions. In the following embodiments, one switching element (here, a field effect transistor) and one switching element
An example in which the method for forming a capacitor insulating film according to the present invention is applied to the manufacture of a semiconductor memory device in which each memory cell is composed of one capacitor will be described.

1. First Embodiment FIG. 1 to FIG. 3 are process drawings for explaining the first embodiment.
FIG. 6 is a process diagram showing a state of a sample in a main process in a manufacturing process of a semiconductor memory device by a cross-sectional view of one memory cell portion.

First, as shown in FIG. 1A, after a field oxide film 13 is selectively grown on the (100) plane of a P-type silicon substrate 11 by the LOCOS method, a gate is formed on the substrate 11. The oxide film 15 is formed to have a thickness of 100 Å, for example. Next, a polycrystalline silicon film (not shown) for forming a gate electrode is formed on the entire surface of the substrate to a thickness of about 1500 Å. Next, in order to make this polycrystalline silicon film conductive, this film is doped with phosphorus using POCl ₃ as a diffusion source. Next, a photolithography process and an etching process for processing the polycrystalline silicon film into a gate electrode shape are performed on the film to obtain the gate electrode 17.
Next, using the gate electrode 17 as a mask, arsenic ⁷⁵ As ⁺ is ion-implanted into the substrate 11 at an acceleration energy of 40 KeV and a dose amount of 5 × 10 ¹⁵ ion / cm ² , thereby forming source / drain regions 19. Next, as the interlayer insulating film 21, a silicon oxide film 21a of 3000 Å and a silicon nitride film 2 are formed on the sample by the CVD method.
1b of 200Å and a silicon oxide film 21c of about 4000Å are sequentially formed. In the case of this embodiment, the base in the present invention is mainly the silicon oxide film 21c. Next, a contact hole 23 is formed in the interlayer insulating film 21 by performing a predetermined photolithography process and etching process. After that, the rough-surface polycrystalline silicon film 25 according to the present invention is formed on the entire surface of this sample by the LPCVD (low pressure CVD) method (FIG. 1A).

Here, an example of a specific method for forming the rough-surface polycrystalline silicon film 25 and its growth state are shown in FIG.
A more detailed description will be given with reference to (A) to (C). Here, FIGS. 4A to 4C show the rough-surface polycrystalline silicon film 2
5 is a cross-sectional view schematically showing how 5 is formed. FIG.

First, as shown in FIG. 4 (A), a sample in which the interlayer insulating film 21 has been formed is put into a growth chamber of an LPCVD apparatus, and then SiH ₄ gas is added to the growth chamber at 0.2To.
A silicon film (not shown) is formed by flowing a gas flow rate of 150 sccm for 30 minutes under a pressure condition of rr. At this time, the silicon film 25 is grown at a transition temperature at which the silicon film 25 changes from an amorphous state to polycrystalline silicon, for example, 575 ° C. As a result, as shown in FIG. 4A, polycrystalline silicon 2 is formed near the interface (near the surface of the silicon oxide film 21c).
5a grows, but most of amorphous silicon 25b is formed on it. This sample is transferred to another vacuum chamber by a vacuum transfer device and annealed in a vacuum atmosphere at a temperature slightly higher than the temperature at the time of crystal growth, for example, 600 ° C. As a result, as shown in FIGS. 4B and 4C, the amorphous silicon layer 25b in the upper layer is gradually crystallized from the portion where the energy required for the diffusion of silicon atoms is the lowest, that is, the surface of the layer 25b. come. In FIGS. 4B and 4C, the granular portion of the polycrystalline silicon film produced by crystallization is schematically shown as 25c. At the same time, the polycrystalline silicon 25a existing in the vicinity of the interface is gradually crystallized, and finally, as shown in FIG. A rough surface polycrystalline silicon film 25 having irregularities is formed. It is considered that the schematic view of the rough-surface polycrystalline silicon film 25 at this time when viewed in plan is as shown in FIG. A schematic view of the cross section is shown in FIG.
It is considered to be like (A). That is, the granular portion 25c (see FIG.
It is considered that each of them exists independently of each other, and a thin polycrystalline silicon film is provided between them, which is a plan view but shows hatching in (A).

Next, the rough surface polycrystalline silicon film 25 is irradiated with energetic particles. In this embodiment, arsenic ions ( ⁷⁵ As ⁺ ) having a mass number of 75 are ion-implanted on the rough-surface polycrystalline silicon film 25 at an acceleration energy of 30 KeV and a dose amount of 5 × 10 ¹⁵ ion / cm ^2. . As a result, the rough surface polycrystalline silicon film 2
In No. 5, it is considered that a part of the ion-implanted region becomes amorphous. In particular, it is considered that the part where the surface was flat before the ion implantation will be completely amorphized, and the surface part of the granular part 25c will be amorphized, and the inside maintains the state of polycrystalline silicon. It is thought that. This state is schematically shown in FIG. This Figure 6
The amorphous portion in (B) is indicated by 25d. This amorphized portion 25d is etched at an extremely high speed in the subsequent etching of the silicon oxide film 21c, so that it does not have a masking effect, and as a result, the remaining portion 25c without being amorphized (see FIG. 6). (See (B)) becomes a mask. For this reason,
As shown in FIGS. 1B and 6C, since the recess 27 is formed in a part of the silicon oxide film 21c, after all,
Concavities and convexities are formed on the oxide film 21c. Note that another advantage of performing ion implantation here is that adjacent granular portions 25c are bonded together. This state is shown in FIG.
It is shown as a schematic plan view in FIG. FIG. 5 (B)
In FIG. 6, the area where the granular portions 25c are connected is hatched. In this way, it was confirmed that the individual grain-shaped polycrystalline silicon is deformed and bonded to each other, whereby the mask effect during pattern transfer is significantly improved. In order for each of the grain-shaped polycrystalline silicon films to have a shape bonded to each other,
It is known that the formation conditions of the rough-surface polycrystalline silicon film 25, that is, the density of the granular portions 25c in the polycrystalline silicon film and the ion implantation conditions have a great influence. Assuming the above growth conditions, the dose of arsenic ions during ion implantation is 1.0 × 1.
It has been found that the above-mentioned bonding between the granular portions 25c does not occur unless it is set to 0 ¹⁵ ion / cm ² or more.
Furthermore, when the sample is annealed after the above-mentioned ion implantation, the silicon oxide film 2
Rough-surface polycrystalline silicon film 25 during dry etching of 1c
It is also known that the selection ratio as an etching mask of is significantly improved. The annealing condition at this time is, for example, 30 at a temperature of 850 ° C. in a nitrogen gas atmosphere.
Examples include conditions for annealing for a minute.

After forming the concaves and convexes in the silicon oxide film 21c by forming the concave portions 27 in the silicon oxide film 21c as the base, as shown in FIG. 2A, the LPCVD method is performed on the entire surface of the sample. By using silane (SiH ₄ ) as a source gas, a film for forming a capacitor insulating film (however,
This film also serves as a storage electrode forming film. In this case, a polycrystalline silicon film 29 is formed.

Next, in order to make the polycrystalline silicon film 29 conductive, this film 29 is doped with phosphorus using POCl ₃ as a diffusion source (not shown).

Next, the polysilicon film 29 is processed by a lithography technique and an etching technique so as to have a shape conforming to the shape of the capacitor. Next, the underlying silicon oxide film 21c is etched by isotropic etching (FIG. 2B). In this etching, the silicon nitride film 21b functions as an etching stop layer, so that only the silicon oxide film 21c can be removed as desired.
In FIG. 2B, the remaining portion of the rough-surface polycrystalline silicon film is shown as being integrated with the polysilicon film 29.

Next, here, the polycrystalline silicon film 29 (which has been processed into a capacitor shape), which is a film for forming the storage electrode and the capacitor insulating film, is subjected to a nitriding treatment in this case, so that the polycrystalline silicon film 29 is formed. A silicon nitride film 31 as a capacitor insulating film is formed on the surface to a predetermined thickness of, for example, 100 Å or less (FIG. 3A). Incidentally, the portion which is not nitrided even by this nitriding treatment and remains as the polycrystalline silicon film becomes the storage electrode 33 (also in FIG.
(A)).

Next, a polycrystalline silicon film is used as a film for forming a cell plate electrode on the entire surface of this sample, for example, 2
It is formed to a thickness of 000Å, and in order to make it conductive, for example, POCl ₃ is used as a diffusion source and doped with phosphorus.
Then, this polycrystalline silicon film is processed into a cell plate electrode shape to obtain a cell plate electrode 35 (also in FIG.
(A)).

Next, as shown in FIG. 3B, for example, B
The PSG film 37 is formed by a CVD method to have a film thickness of, for example, 8000 Å, and then the BPSG film 37 is formed at 900 ° C.
Flow treatment is performed in a nitrogen atmosphere at the temperature of. Next, a contact hole 39 is formed in a predetermined portion of the BPSG film 37 by a known technique. Next, for example, an aluminum film is formed as a thin film of a wiring forming material on this sample by, for example, a sputtering method to have a film thickness of, for example, 7,000 Å, and then the aluminum film is patterned by a known photolithography technique and etching technique to obtain the wiring 41. .

As mentioned above, according to the method of the present invention,
A structure in which a capacitor insulating film of a capacitor and an electrode in a memory cell of a semiconductor memory device are in contact with each other with unevenness can be easily formed. Therefore, it is possible to easily form a capacitor having a large electrode area, that is, a capacitor having a large capacitance in a limited substrate area having a flat area. Therefore, it is possible to easily manufacture a highly integrated semiconductor memory device that exhibits desired electrical characteristics (for example, a soft error is unlikely to occur and a desired hold time is exhibited).

In the first embodiment, an example in which the ion species used in the modification by ion implantation is As is shown, but the ion species used is not limited to this and other suitable ones may be used.

2. Second Example In the above-described first example, after irradiating the polycrystalline silicon film 25 of the sample (see FIG. 1A) on which the rough-surfaced polycrystalline silicon film 25 is formed with energetic particles, The sample was once exposed to the atmosphere from the apparatus and transferred to a dry etching apparatus for etching treatment. It is preferable that irradiation of energetic particles on the rough-surface polycrystalline silicon film 25 and subsequent etching for forming a recess in the underlying silicon oxide film can be continuously performed, because throughput can be remarkably improved. This second embodiment is such an example.

Therefore, in this second embodiment, for example, argon gas is introduced as an inert gas into the reaction chamber of the dry etching apparatus, and the argon gas is discharged to discharge Ar.
⁺ Ions are generated and the rough surface polycrystalline silicon film 25 is irradiated with the Ar ⁺ ions as energetic particles in the present invention. Then, after the irradiation of Ar ⁺ ions is completed, an etching gas is introduced into the reaction chamber to etch the underlying silicon oxide film 21c.
A specific example of this series of processing will be described below with reference to FIG. 7. Here, FIG. 7 is a diagram schematically showing a configuration example of a dry etching apparatus using ECR (electron cyclotron resonance). The dry etching apparatus has a conventionally known structure.

A microwave of, for example, 2.45 GHz emitted from a magnetron (not shown) is introduced into the reaction chamber 57 through the quartz window 55 after being transmitted through the waveguide 53. The microwave introduced into the reaction chamber 57 as described above
Solenoid coils 59a, 5 installed around 7
It interacts with the magnetic field formed by the current flowing in 9b and promotes the excitation of the argon gas introduced into the reaction chamber 57. In particular, at a point (position) where the magnetic flux density in the reaction chamber 57 is 875 Gauss, electron cyclotron resonance is generated.
^* ) And ionization to Ar ⁺ ions are significantly promoted. On the other hand, since high frequency power of 400 KHz is applied from the high frequency power source 63 to the electrode 61 on which the wafer 59 (sample in the state of FIG. 1A) is placed in the reaction chamber 57, the surface of the wafer 59 is An ion sheath is formed. The magnitude of the sheath electric field can be controlled by the applied voltage of the high frequency power source 63. Due to this sheath electric field, the Ar ⁺ ions generated in the reaction chamber 57 are accelerated and enter the surface of the wafer 59. The etching system of the type described here has the advantage that the ionization of Ar ⁺ ions (that is, the ion current density) in the reaction chamber 57 and the incident ion energy can be controlled independently. When irradiating a wafer with Ar ⁺ ions using this dry etching apparatus, for example, Ar gas of 70 (scc) is used.
m) is introduced into the reaction chamber at a flow rate of 4 mT
Under the pressure of orr, the current values of the solenoid coils 59a and 59b provided above and below the device are set to 19 A and 7 A, respectively, and a microwave of about 0.8 W is introduced. Moreover, the power of the high frequency power of 400 KHz applied to the wafer 59 is set to 400W. At least in the rough-surface polycrystalline silicon film 25 irradiated with Ar ⁺ ions under this condition, the same modification phenomenon as in the case of the first embodiment, that is, a part of amorphization and
It was confirmed that adjacent granular polycrystalline silicon films are bonded to each other.

Next, the silicon oxide film 21c is etched by using the rough-surface polycrystalline silicon film 25 which has been irradiated with Ar ⁺ ions as an etching resistant mask. Therefore, in the case of this embodiment, a mixed gas of CH ₂ F ₂ and CHF ₃ is supplied to the reaction chamber 57 as an etching gas at a flow rate ratio of 14 (sccm) for the former and 50 (sccm) for the latter. Then, the pressure in the reaction chamber 57 is set to 4 mTorr.
And the etching is performed under the condition that the high frequency power is 200 W. As a result of this etching, a recess is formed in the silicon oxide film 21c as the base, and the unevenness of the rough-surface polycrystalline silicon film 25 is satisfactorily transferred.

Although the ECR etching apparatus is used as an example in the above description, the parallel plate type reactive ion etching (RIE) apparatus (not shown) is installed in the reaction chamber of FIG.
Put wafer in the state of (A), further putting argon gas is generated Ar ⁺ ions into the reaction chamber the Ar ⁺
It has been confirmed that, even when the wafer is irradiated with ions, the rough-surface polycrystalline silicon film is modified similarly to the case where the ECR etching apparatus is used. After the modification treatment, an etching gas was continuously introduced into the reaction chamber of the parallel plate type RIE apparatus to etch the underlying silicon oxide film 21c. It has also been confirmed that it is satisfactorily transferred to the oxide film 21c.

As can be understood from the results of the second embodiment, it is understood that the same effect as when the rough surface polycrystalline silicon film 25 is subjected to the ion implantation can be obtained when the dry etching apparatus is used. . Further, particularly in the case of the second embodiment, modification of the rough-surface polycrystalline silicon film 25 and the silicon oxide film 21c using the modified rough-surface polycrystalline silicon film 25 as an etching resisting mask.
It is possible to obtain the advantage that the etching can be continuously performed using the same apparatus. If continuous processing can be performed in this way, throughput can be improved. Further, it is possible to obtain the effect of preventing the formation of an unnecessary natural oxide film on the sample and the effect of further reducing the influence of contamination. Incidentally, when ⁷⁵ As ⁺ ions are used as energetic particles in the first embodiment and Ar in the second embodiment.
^When using ⁺ ions as energetic particles,
Since the rough-surface polycrystalline silicon film 25 has been modified, it is presumed that this modification is a phenomenon induced by physical impact.

In the second embodiment, an example in which the gas used is argon gas is shown, but the gas used is not limited to this and may be another inert gas or another suitable gas. For example, Kr, Xe, N ₂ , He or the like can be used as this gas. However, it is considered that the larger the gas number, the greater the effect.

3. Third Embodiment When applying the method for forming a capacitor insulating film of the present invention in manufacturing a semiconductor device having a capacitor, in practice, only a specific region of a rough-surface polycrystalline silicon film, that is, a region where a capacitor is formed is modified. Then, the uneven transfer to the base is performed. When a capacitor is formed in such a specific region and the method of the first embodiment or the method of the second embodiment is used, a mask for exposing the specific region and covering the other regions, for example, Generally, a resist pattern is formed. However, since the rough-surface polycrystalline film is considered to have very steep irregularities, it may be difficult to form a resist pattern on the surface of such a rough-surface polycrystalline silicon film. For example, there are cases where the photoresist cannot be applied well, or the photoresist enters the irregularities of the rough-surface polycrystalline silicon film, and the resist that should be originally removed in the developing process remains without being removed. Therefore, it is preferable that only a specific region is modified and the uneven transfer to the base can be performed without using a mask. This third embodiment is such an example. This description will be described with reference to FIG. FIG. 8 is a diagram provided for explaining an embodiment of the third invention (semiconductor manufacturing apparatus) of this application. Here, in FIG.
1 is a means 73 for fixing a sample (sample to be processed)
It is a processing room equipped with. Further, 75 is an ion irradiation unit connected to the processing chamber 71, and 77 is an etching unit connected to the processing chamber 71. The ion irradiation unit 75 has means 79 for extracting and accelerating a specific ion.
It comprises a means 81 for focusing the accelerated ions and a means 83 for irradiating the focused ions to a specific region on the sample (ion focusing means 83). In this case, the means 79 for extracting and accelerating the ions comprises a needle 79a, an extraction electrode 79b and an EXB mass separator 79c. The ion focusing means 81 is composed of an aperture 81a, a first lens 81b and a second lens 81c. The means 83 for irradiating the specific region with the ions includes a first deflector 83a and a second deflector 8
3b and the ion beam scanning controller 83c. The ion irradiation unit 75 can basically be composed of a focused ion beam device. Further, the etching unit includes means 77a for supplying an etching gas to the processing chamber 71, an exhaust system 77b for controlling the degree of vacuum in the processing chamber 71, and an electric device for promoting the action of the etching gas on the sample. Includes systems 77c and 73. The specific configuration of the etching section 77 may be that of a known dry etching apparatus, for example.

In the third embodiment, a wafer 59 (shown in FIG. 1 (A)) having a rough surface polycrystalline silicon film formed by the procedure described with reference to FIG. 1 (A) in the first embodiment. Is placed on the electrode 73 which also serves as a sample table in the processing chamber 71. Ions focused on the wafer 59 from the ion irradiation unit 75 are applied to an arbitrary specific area on the wafer 59. Here, As ⁺ will be described as an example of the focused ion beam species. Ions containing As ⁺ ions generated by field ionization at the tip of the needle 79a of the ion irradiation unit 75 are extracted by the extraction electrode 79b and accelerated as an ion beam. This ion beam passes through the two apertures 81a, is once focused by the first lens 81b, and then is introduced into the EXB mass separator 79c where only As ⁺ having a specific mass number is selected. The selected As ⁺ ions are transferred to the second lens 81.
The wafer 5 is converged by c and becomes a focused ion beam.
9 specific areas are irradiated. Irradiation to this specific area is controlled by the ion beam scanning controller 83c and the first and second deflectors 83a and 83b driven according to an electric signal output from this controller for supporting the specific area. As a result of this beam scanning, the rough surface polycrystalline silicon film portion of the specific region irradiated with the As ⁺ ion beam is modified in the same manner as described in the first embodiment and the like. That is, it is considered that the adjacent polycrystalline silicon film portions having grain shapes are bonded to each other, and a part of the polycrystalline silicon film becomes amorphous silicon. Further, since the rough-surface polycrystalline silicon film portion not irradiated with As ⁺ ions is still composed of the granular polycrystalline silicon portion and the polycrystalline silicon portion having a thin film thickness therebetween, the whole thereof is resistant to etching. Maintain the effect of the mask.

After the irradiation of As ⁺ ions is completed, the gas supply means 77a of the etching section 77 causes a mixed gas of, for example, CF ₄ gas, CHF ₃ gas, and argon gas to enter the processing chamber 71. (Sccm), 25 (s
ccm) and mixed gas of 400 (sccm) are supplied. The pressure in the processing chamber is controlled to be, for example, 1.0 Torr by the exhaust system 77b, and
The silicon oxide film 21c (for example, see FIG. 1A) of the wafer 59 is etched by applying a high-frequency power having a frequency of 0 KHz and a power of 300 W to the processing chamber space by the electric systems 77c and 73.

In this etching of the silicon oxide film 21c, desired etching occurs in the silicon oxide film portion below the portion irradiated with As ⁺ ions, so that the unevenness of the rough-surface polycrystalline silicon film is transferred to this portion. On the other hand, the portion of the rough-surface polycrystalline silicon film which has not been irradiated with As ⁺ ions still has the effect as an etching mask, so that the silicon oxide film portion under this portion is not etched at all. . Therefore, desired unevenness can be formed only on the silicon oxide film portion of the specific region.

In the third embodiment, an As ⁺ ion beam is used as the focused ion beam species, but the focused ion beam species can be any suitable one. For example, an Ar ⁺ ion beam is one example.

In the method of the third embodiment, the reforming of the rough-surface polycrystalline silicon film and the etching of the silicon oxide film using this silicon film as an etching resistant mask are carried out continuously by using the same apparatus. In addition to the advantage of the second embodiment that it can be performed, there is an advantage that these processes can be performed only on a specific area. Further, even when only the specific region is processed in this way, there is an advantage that this process can be performed without providing a special mask such as a resist pattern.

4. Fourth Embodiment In each of the above-described first to third embodiments, an example in which a desired etching mask is obtained by irradiating a rough surface polycrystalline silicon film with energetic particles has been described, but a rough surface polycrystalline silicon film is used. It was found from the research by the inventor of this application that the desired unevenness can be formed on the capacitor insulating film by the following method without using the above method. This fourth embodiment is such an example. The main features of the method of the fourth embodiment are: (i) a step of growing tungsten nuclei on the underlayer so that the nuclei of the tungsten are scattered on the underlayer; and (ii) an etching-resistant mask for the tungsten nuclei. And the step of etching the base to form irregularities on the base. Hereinafter, a specific description will be given mainly with reference to FIGS. 9 (A) and 9 (B).

First, among the procedures described with reference to FIG. 1A in the first embodiment up to the step before forming the rough-surface polycrystalline silicon film, the (10
A field oxide film, a gate oxide film, a gate electrode, an interlayer insulating film and a cell contact are formed on the (0) plane.
Next, this sample is put into the growth chamber of the LPCVD apparatus.
And keep the substrate temperature as high as 300 ° C, and
Under a pressure of about 200 mTorr in the growth chamber, SiH ₄ gas is introduced into the growth chamber at a relatively low flow rate of about 5 (sccm) for 30 seconds. In this process, SiH ₄ gas is adsorbed on the sample on which the interlayer insulating film 21 has been formed. Therefore, the SiH ₄ gas is adsorbed on the silicon oxide film 21c which is the main base in the present invention.
The SiH ₄ gas adsorbed on the underlayer becomes an indispensable element for inducing the subsequent nucleus growth of grain-shaped tungsten as described later. Next, a mixed gas of WF ₆ and SiH _{4 in} which the flow rate of SiH ₄ is smaller than that of WF ₆ , for example, SiH ₄ = 1 sccm and WF ₆ = 10 sc.
A mixed gas having a flow rate ratio of cm is supplied to the growth chamber of the LPCVD apparatus under a pressure of 5 mTorr, for example, to grow a tungsten nucleus 91 on the underlayer (FIG. 9A). In this process, a reduction reaction of WF ₆ + SiH ₄ → SiF ₄ + H ₂ occurs, and grain-shaped tungsten nuclei 91 grow on the underlayer. In this way, the flow rate of SiH ₄ is changed to WF
_The reason why the tungsten nucleus 91 grows when the number is less than that of ₆ is that this growth occurs in the region where the supply rate is controlled by SiH ₄ .

Next, the tungsten nucleus 91 is used as an etching resistant mask to form a base (mainly the silicon oxide film 21).
Etch c) with an anisotropic etching technique. In this etching, the underlying portion, which is not covered with the tungsten nucleus 91, is etched, so that the concave portion 27 is formed.
As a result, unevenness can be formed in the base (FIG. 9).
(B)). The etching conditions may be the same as those described in the first embodiment. Then, the tungsten nucleus 91 is removed by introducing SF ₆ gas into the growth chamber (which also serves as an etching chamber).

After that, a polysilicon film which is a film (also a storage electrode forming film) for forming a capacitor insulating film is formed by a procedure similar to that of the first embodiment described with reference to FIGS. 2 and 3. The desired capacitor may be obtained by performing formation or the like.

According to the method of the fourth embodiment, a desired etching mask can be formed on the underlayer without forming a rough-surface polycrystalline silicon film and irradiating it with energetic particles. .

In the fourth embodiment, it has been stated that it is indispensable for the growth of the tungsten nucleus 91 to flow SiH ₄ into the growth chamber to adsorb SiH ₄ on the sample in advance. Instead, it was found from a detailed study by the inventor of the present application that a similar effect can be obtained by subjecting the sample to physical impact such as ion beam irradiation in advance and then growing tungsten. Specifically, as shown in the second embodiment, the physical properties of Ar ⁺ ions are measured by using the device (the sample in which the interlayer insulating film 21 and the contact hole 23 are formed) as described in the second embodiment. After the shock is applied, for example, the conditions described above in the fourth embodiment, that is, the substrate temperature is 300 ° C. and the pressure is 5 mTorr, and SiH ₄ / WF ₆ = 1 (s).
It was found that by growing tungsten under the condition that the flow rate is set to ccm) / 10 (sccm), tungsten nuclei grow on the underlayer. The mechanism of nuclear growth here is considered to be as follows. : By irradiating the silicon oxide film (underlayer) with the above Ar ⁺ ions, the Si—O bond in the silicon oxide film is broken and O is selectively removed by sputtering. As a result, the vicinity of the surface of the silicon oxide film is relatively removed. To Si (Si
(Dangling bond) will be a layer rich in. : This S
Since the i-dangling bond is extremely active for the subsequent adsorption of WF ₆ and SiH ₄ , the growth of granular tungsten nuclei easily occurs.

Here, this technique, in which the nucleus growth of tungsten can be generated only in the region irradiated with the ion beam of the inert gas, is the tungsten film as the etching mask only in the specific region of the sample, that is, the capacitor formation region. Since it means that it is possible to grow, it is an alternative to the third embodiment (a technique that makes it possible to irradiate a specific region with a focused ion beam and continuously perform etching without using a resist pattern). It can also be used as a technique. Also in this point, the modification of the fourth embodiment is highly utilized.

Although the embodiments of the inventions of this application have been described above, the inventions are not limited to the above-mentioned embodiments. For example, in the above-described embodiment, the example of forming the capacitor of the semiconductor memory device is described, but each invention of this application can be applied to the case of forming a general capacitor in a semiconductor device. Further, in the above-described embodiment, after forming the unevenness on the base, a film for forming a capacitor insulating film (a film also serving as a storage electrode forming film in the embodiment) is formed separately, and the base is removed to remove the base. An example of transferring unevenness has been described. That is, the example in which the underlayer itself behaves as a sacrificial layer has been described. However, the inventions of this application can also be applied to the case where the underlying layer itself is used as a film for forming a capacitor insulating film and unevenness is formed on the surface of this film.

[0043]

As is apparent from the above description, according to the method for forming a capacitor insulating film of the present invention, the rough surface polycrystalline silicon film is irradiated with energetic particles and then the rough surface polycrystalline silicon film is masked. The base is etched as. The rough surface polycrystalline silicon film is modified to a suitable state as an etching mask by irradiation of energetic particles, so after the etching of the base is completed, irregularities corresponding to the irregularities of the rough surface polycrystalline silicon film are formed on the surface of the base. To be done. For this reason,
A capacitor insulating film having irregularities can be easily formed. Further, also in the case where the tungsten nuclei are used as the etching mask, irregularities corresponding to the distribution of the scattered tungsten nuclei are formed on the underlying layer after etching.

[Brief description of drawings]

FIG. 1 is a process diagram mainly provided for explaining a first embodiment.

FIG. 2 is a process diagram following FIG. 1 mainly for explaining the first embodiment.

FIG. 3 is a process diagram following FIG. 2 mainly for explaining the first embodiment.

FIG. 4 is a diagram mainly used for explaining the first embodiment and is a diagram used for estimating a formation mechanism of a rough-surface polycrystalline silicon film.

FIG. 5 is a diagram mainly provided for explaining the first embodiment and is a diagram for explaining an effect when the rough surface polycrystalline silicon film is irradiated with energetic particles.

FIG. 6 is a diagram mainly used for describing the first embodiment, and FIG.
Similarly, it is a figure explaining the effect at the time of irradiating a rough surface polycrystalline silicon film with energetic particles.

FIG. 7 is a diagram for explaining a second embodiment.

FIG. 8 is a diagram for explaining a third embodiment.

FIG. 9 is a diagram for explaining a fourth embodiment.

[Explanation of symbols]

11: Silicon substrate 13: Field oxide film 15: Gate insulating film (gate oxide film) 19: Source / drain regions 21: Interlayer insulating film 21a: Silicon oxide film 21b: Silicon nitride film 21c: Silicon oxide film ( 23: Contact hole 25: Rough surface polycrystalline silicon film 25a: Polycrystalline silicon film 25b: Amorphous silicon 25c: Granular portion of rough surface polycrystalline silicon film 27: Recess 29: Capacitor insulation Film for film formation 31: Capacitor insulating film 33: Storage electrode 35: Cell plate electrode 71: Processing chamber 75: Ion irradiation part 77: Etching part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/8242 27/108 H01L 21/302 N 27/10 325 J

Claims (7)

[Claims] 1. A step of: (a) forming a rough surface polycrystalline silicon film having an uneven surface on a base, and (b) a step of irradiating the rough surface polycrystalline silicon film with energetic particles. c) a step of using the rough-surface polycrystalline polysilicon film that has been irradiated with energetic particles as an etching-resistant mask to etch the base to form irregularities on the foundation, and (d) forming the irregularities on the bottom. Forming a film for forming a capacitor insulating film on the ground separately and transferring the irregularities to the film for forming a capacitor insulating film to obtain a capacitor insulating film. . 2. The method for forming a capacitor insulating film according to claim 1, wherein in the step (d), a polycrystalline silicon film as a film for forming a capacitor insulating film is formed on the base on which the unevenness is formed. And a step of forming an insulating film as a capacitor insulating film on the surface of the polycrystalline silicon film by subjecting the polycrystalline silicon film to oxidation treatment and / or nitridation treatment or both. Method for forming capacitor insulating film. 3. The method for forming a capacitor insulating film according to claim 1, wherein a film for forming a capacitor insulating film is formed as the base,
After that, the steps (a) to (c) are carried out, and instead of carrying out the step (d), the base having the irregularities is used as it is as a capacitor insulating film. Forming method. 4. The method for forming a capacitor insulating film according to claim 1, wherein in place of the steps (a), (b) and (C), (i) a tungsten nucleus is formed on the underlayer. A capacitor comprising: a step of growing so as to be scattered on the underlayer; and (ii) a step of forming an unevenness on the underlayer by etching the underlayer using the nucleus of tungsten as an etching resistant mask. Method of forming insulating film. 5. When forming a semiconductor memory device in which a memory cell is composed of a switching element and a capacitor, a capacitor insulating film in the capacitor is formed by the method according to claim 1. A method for forming a semiconductor memory device, comprising: 6. A processing chamber having means for fixing a sample, means connected to the processing chamber for extracting and accelerating a specific ion, and for converging the accelerated ion. Means, and an ion irradiation unit having means for irradiating the focused region to a specific region on the sample; a means connected to the processing chamber for supplying an etching gas to the processing chamber; A semiconductor manufacturing apparatus comprising: an etching system having an exhaust system for controlling the degree of vacuum in the processing chamber and an electrical system for promoting the action of the etching gas on the sample. 7. Instead of the ion irradiation unit according to claim 6, means for extracting and accelerating a specific ion, which is connected to the processing chamber, and the accelerated ion in the form of a shower. A semiconductor manufacturing apparatus, comprising an ion irradiation unit having means for irradiating a semiconductor.