JPH07262790A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To relieve and use a defective memory cell even if such a memory exists by controlling memory cell array with block selection signal. CONSTITUTION:A block selecting circuit 2 determines a selection level from block selection signals BS1 to BS41 according to second address signals AD1, AD2 unless there is the defective memory cell in the memory cell arrays MA1 to MA4. A row selecting circuit RS and a column selecting and amplifying circuit CSA corresponding to the selection signal BS of the selection level are activated. The memory cells of the addresses of the rows and columns assigned by the row address signal ADr and column address signal ADC of a first address signal are selected and reading out and writing of the data from the memory cells are executed. Only the block selection signal corresponding to one of the memory cells where the defective memory cells do not exist is fixed at the selection level by the selecting circuit 2 and the writing and reading out of the data are executed only for this memory cell if the defective memory cell exists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device capable of relieving a defective memory cell when it exists in a memory cell array and improving the manufacturing yield.

[0002]

2. Description of the Related Art In various semiconductor memory devices, when the memory capacity thereof increases, the proportion of defective memory cells present in the memory cell array increases, and the manufacturing yield decreases. Therefore, in addition to the memory cell array, a redundant circuit including a row (column) of redundant memory cells is provided to replace the row (column) in which a defective memory cell exists, to repair the semiconductor memory device and improve the manufacturing yield. Techniques have come to be adopted.

There are various circuits and methods for the redundant circuit of the semiconductor memory device (for example, published by Science Forum, ULSI DRAM technology, pages 67 to 70, Japanese Patent Laid-Open No. Hei 2).
FIG. 7 shows an example (first example) of a semiconductor memory device provided with a most typical and typical redundant circuit.

This semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns, a memory cell array MAx for writing and reading data to and from memory cells in selected rows and columns, and an external memory cell array. An address buffer circuit 1x that receives the address signal AD and outputs a row address signal ADr and a column address signal ADc, a row selection circuit RSx that selects a predetermined row of the memory cell array MAx according to the row address signal ADr, and a column address signal A.
A predetermined column of the memory cell array MAx is selected according to Dc, data read from the memory cell array MAx is amplified, and write data is transferred to the memory cell array Mx.
Column selection / amplification circuit CSAx that transmits to Ax
The output (DTO) of the data amplified by the amplifier circuit CSAx to the outside and the data input / output buffer circuit 3x for transmitting the data DTI for writing from the outside to the column selection / amplifier circuit CSAx and the defective memory cell array MAx. When a memory cell exists, a redundant memory cell row RAMr and a redundant memory cell column RMAc for writing and reading data instead of the row and column in which the defective memory cell exists,
When a defective memory cell exists in the memory cell array MAx, the row address in which the defective memory cell exists is stored and the row address signal ADr specifies the stored row address. Redundant memory cell row RMAr , A redundant row selection circuit RRS for deactivating the row selection circuit RSx and a memory cell array MAx.
When a defective memory cell (different from the defective memory cell described above) exists therein, the column address in which the defective memory cell exists is stored and the redundant memory cell column RMAc is stored.
Column deselecting / amplifying circuit CSAx is deactivated and the data read from the redundant memory cell column RAMc is amplified and transmitted to the data input / output buffer circuit 3x. And a redundant column selecting / amplifying circuit RCSA for transmitting the write data (DTI) from the redundant memory cell column RMAc to the redundant memory cell column RMAc.

In this semiconductor memory device, both the redundant memory cell row RMAr and the redundant memory cell column RMAc are provided, but there are many examples of only one of them.

In this semiconductor memory device, when a defective memory cell exists in the memory cell array MAx,
Data is written and read using the redundant memory cell row RMAr or the redundant memory cell column RMAc instead of the row or column in which the defective memory cell exists, so that the number of defective memory cells in the memory cell array MAx is increased. However, this semiconductor memory device can be repaired as a non-defective product within a range in which the redundant memory cell row RMAr and the redundant memory cell column RAMc can be replaced, and the manufacturing yield can be improved.

A typical circuit example for storing the row address of the defective memory cell of the redundant row selection circuit RRS in such a semiconductor memory device is shown in FIG. 8 (the same applies to the circuit for storing the column address).

This circuit has a row address signal AD at its gate.
True / complementary signals ADr1, ADr1 * of each constituent bit of r
(* Indicates a complementary signal) to ADrn, ADrn * are connected between the source-grounded transistors Q11, Q12 to Qn1 and Qn2 which are turned on / off, respectively, and the drains of these transistors and the output node N1. Fuses F11, F12 to Fn1, Fn2 and output node N1
And a transistor Qp for supplying the power supply voltage VCC.

In this circuit, when a "1" level (high level) row address signal (whether true or complementary) is input to the gate of the transistor connected to the uncut fuse, the output The node N1 is connected to the ground potential point through a fuse and a transistor and has a low potential (inactive level), and the redundant memory cell row RMAr is in a non-selected state. Therefore, by disconnecting all the fuses corresponding to the "1" signal of the true / complementary signals of each constituent bit of the row address signal of the defective memory cell, only at the row address of the defective memory cell. There is no path connecting the output node N1 to the ground potential point, the output contact N1 can be kept at the high level (activation level) of the power supply potential VCC level, and the redundant memory cell row RMAr can be selected.

Since such a defective address storage circuit is required for each row and each column of the redundant memory cell row RMAr and the redundant memory cell column RMAc, the chip area including the redundant memory cell row and the redundant memory cell column is correspondingly increased. Will increase. Therefore, the number of redundant memory cell rows and redundant memory cell columns to be installed is inevitably limited, and this number of installations is determined by the allowable upper limit of chip area, the lower limit of yield, the occurrence state of defective memory cells, and the like. .

When the memory capacity further increases, the number of memory cells connected to one bit line and word line increases, the additional capacity of these bit lines and word lines increases, and the operating speed decreases. Power consumption increases due to potential changes and charging / discharging of bit lines and word lines. Therefore, in a large-capacity semiconductor memory device, the memory cell array is divided into a plurality of memory cells to reduce the number of memory cells connected to one bit line or word line, thereby preventing a decrease in operating speed and reducing power consumption. (For example, published by Science Forum, ULSI DRAM technology, 89-91)
See page).

Even in a semiconductor memory device having a plurality of memory cell arrays (second example), a repair process is naturally performed by a redundant circuit to improve the yield. Also in this case, as in the case of one memory cell array described above,
There is a limit to the number of redundant memory cell rows and redundant memory cell columns that can be installed.

[0013]

In the conventional semiconductor memory device described above, although the repair process is performed by the redundant circuit and the yield is improved, the redundant memory cell row and the redundant memory cell are limited due to the allowable upper limit of the chip area and the like. There is a limit to the number of columns (hereinafter referred to as redundant memory cell rows and columns) installed, and the number of memory cell rows and memory cell columns (hereinafter referred to as memory cell rows and columns) in which defective memory cells exist is redundant memory. When the number of cell rows and columns was exceeded, it was impossible to relieve and was discarded. However, even if a semiconductor memory device having a plurality of memory cell arrays is disposed of as described above, defective memory cells do not remain in all of the plurality of memory cell arrays, and defective memory cells exist. It often includes a memory cell array that does not.
That is, even if the usable memory cell array is included, it is discarded, so that there is a problem that resources are wasted and various manufacturing processes are wasted, resulting in high cost.

Further, in a semiconductor memory device having a plurality of memory cell arrays or a semiconductor memory device having a plurality of divided memory cell arrays, when the memory capacity is relatively small or the chip area has a strict upper limit, etc. ,
Often does not have a redundant circuit. In these semiconductor memory devices, if at least one defective memory cell is present in the memory cell array, it is discarded, but not all of the plurality of memory cell arrays and all of the divided memory cell arrays have defective memory cells, and many defective memory cells are present. In this case, the memory cell array includes no defective memory cells and the divided memory cell array. Even in such a case, as described above,
There is a problem that resources are wasted and manufacturing processes are wasted, resulting in high cost.

An object of the present invention is to provide a semiconductor memory device which can reduce the waste of resources and the various manufacturing steps and can reduce the cost.

[0016]

A semiconductor memory device of the present invention includes a plurality of memory cells, each of which has a plurality of memory cells and which reads out its stored data from a memory cell in a selected state among the plurality of memory cells. A plurality of address selection circuits which are provided corresponding to each of the plurality of memory cell arrays, and which, when the corresponding block selection signal is at the selection level, bring the memory cell of the address designated by the first address signal in the corresponding memory cell array into the selected state; When there is no defective memory cell in each of the plurality of memory cell arrays, a block selection signal corresponding to a memory cell array designated by a second address signal among the plurality of memory cell arrays is set to a selection level, Of those with and without defective memory cells Block selection for fixing only a block selection signal corresponding to a predetermined memory cell array in which no defective memory cell exists among the plurality of memory cell arrays to a selection level irrespective of the designation of the second address signal. And a circuit. In addition, when the block selection circuit includes a plurality of programmable non-volatile memory elements and one of which has a defective memory cell and one of which does not exist, the plurality of non-volatile memory elements are programmed. A selected block setting circuit for generating a programming signal for setting a block selection signal corresponding to a predetermined memory cell array having no defective memory cell among the plurality of memory cell arrays to a selection level; Of the plurality of memory cell arrays having defective memory cells and those having defective memory cells, the nonvolatile memory elements are programmed to generate an active level switching control signal. When the control circuit and the switching control signal are active level According to the programming signal, a block selection signal corresponding to a predetermined memory cell array among a plurality of memory cell arrays is set as a selection level, and when the block level is an inactive level, a block selection signal corresponding to the second address signal designated memory cell array is set as a selection level. Switching to
And a block selection circuit including a plurality of programmable non-volatile memory elements and including a defective memory cell and a non-defective memory cell among a plurality of memory cell arrays. In this case, a fixed block selection signal in which only the block selection signal corresponding to a predetermined memory cell array having no defective memory cell in the plurality of memory cell arrays is fixed to a selection level by programming the plurality of nonvolatile memory elements A generated select block setting circuit, a decode circuit which outputs an addressing block selection signal having a block selection signal corresponding to the second address signal specifying memory cell array as a selection level, and a defective circuit among the plurality of memory cell arrays. When some memory cells exist and some do not The fixed block selection signal is selected, and when there is no defective memory cell in each of the plurality of memory cell arrays, the addressing block selection signal is selected and output as a block selection signal corresponding to each of the plurality of memory cell arrays. And a switching circuit.

Further, in a semiconductor memory device having a redundant circuit including a plurality of redundant memory cells, a plurality of defective memory cells are present in the plurality of memory cell arrays by the redundant circuit. Substituting the plurality of defective memory cells so as to read corresponding stored data in place of the predetermined memory cells when the predetermined defective memory cells are addressed by the first address signal. It is configured as a memory cell array after treatment is performed.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment is provided with a plurality of memory cells (not shown), and the stored data is read from the selected memory cell among the plurality of memory cells and the transmitted data is transferred to the selected memory cell. A plurality of memory cell arrays MA1 to MA4 for writing and storing and an address signal AD from the outside are taken in, and a row address signal ADr and a column address signal ADc of the first address signal and a second
Address buffer circuit 1 for outputting the address signals AD1 and AD2 of the plurality of memory cell arrays MA1 to MA4
When there is no defective memory cell in each, the block selection signals (BS1 to BS4) corresponding to the memory cell array designated by the second address signals AD1 and AD2 of the plurality of memory cell arrays MA1 to MA4 are set to the selection level, When some of the plurality of memory cell arrays MA1 to MA4 include a defective memory cell and one of which does not exist, the plurality of memory cell arrays MA
1 to MA4, a block selection circuit 2 for fixing only a block selection signal corresponding to a predetermined memory cell array having no defective memory cell to a selection level irrespective of designation of the second address signals AD1 to AD2; Of the memory cell arrays MA1 to MA4 respectively, and when the corresponding block selection signals (BS1 to BS4) are at the selection level, the memory cell of the address specified by the first address signal (ADr, ADc) in the corresponding memory cell array. Row selection circuits RS1 to RS4 and column selection / amplification circuits CSA1 to CSA4 for amplifying data read from the selected memory cell and transmitting write data to the selected memory cell. , And outputs the data read and amplified from the memory cell arrays MA1 to MA4 to the outside (D O), has a configuration having a data output buffer circuit 3 for transmitting the data for writing from the outside through the column selection and amplification circuit CSA1~CSA4 the memory cell array MA1～MA4.

Next, the usage and operation of this embodiment will be described. Here, the memory cell arrays MA1 to MA
Reference numeral 4 may be a memory cell array after a defective memory cell is replaced by a redundant circuit (not shown) or a memory cell array in which the replacement process cannot be performed without a redundant circuit.

In any memory cell array, if there is no defective memory cell in these memory cell arrays MA1 to MA4, the block selection circuit 2 operates in accordance with the second address signals AD1 and AD2.
One of S1 to BS4, for example, BS1 is set as the selection level. As a result, the block selection signal BS of the selection level
1 corresponding to the row selection circuit RS1 and the column selection / amplification circuit C
SA1 is activated, the memory cell at the address of the row and column designated by the row address signal ADr and the column address signal ADc of the first address signal is in the selected state, and the data is read from this memory cell and the memory cell is read. Data is written. That is, the memory cell array MA
All of 1 to MA4 are used for writing and reading data.

Among the memory cell arrays MA1 to MA4, there are defective memory cells (for example, MA1 and MA4).
3) and non-existing ones (for example, MA2 and MA4) are included, the block selection circuit 2 causes a block corresponding to one (for example, MA4) of the memory cells (MA2 and MA4) in which the defective memory cell does not exist. Only the selection signal (BS4) is fixed to the selection level. as a result,
Data writing and reading are performed only for one memory cell array (MA4).

Conventionally, in a semiconductor memory device having a redundant circuit, a plurality of memory cell arrays after repair (replacement) processing by the redundant circuit have been performed. If at least one defective memory cell exists in the plurality of memory cell arrays, the semiconductor memory device is discarded as a defective product.
However, in the present invention, even if the memory cell array including the defective memory cell is included, if the memory cell array including no defective memory cell is included, only the memory cell array including no defective memory cell is included. It can be used as a semiconductor memory device with a small memory capacity, and can be discarded without disposal. Therefore, the waste of resources and the waste of various manufacturing processes are reduced, and the cost can be reduced accordingly.

In the case of a semiconductor memory device having a small memory capacity, the memory capacity of the semiconductor memory device usually changes in multiples of 4, so in this embodiment, the memory capacity is generally 1/4. But you don't have to worry about this.

FIGS. 2A and 2B are a circuit diagram showing a concrete circuit example of the block selection circuit 2 of this embodiment and a diagram showing the level of the input signal and the output signal with respect to the fuse blown state.

The block selection circuit 2 includes the constituent bits of the second address signals AD1 and AD2 (that is, AD).
1, AD2) corresponding to the true / complementary signals, one end of which is connected to the power supply potential point, and the fuse Fj (j = 1 to 4, hereinafter the same) as a programmable non-volatile memory element, and the sources thereof, respectively. A transistor Qj (only Q1 is shown), which is connected to the ground potential point, connects the drain to the other end of the corresponding fuse (Fj), and connects the gate to the power supply potential point,
An inverter IVj1 (only IV11 is shown) that detects the level of the connection point between the fuse Fj and the corresponding transistor Qj and outputs a signal of level "1" or "0", and an inverter (IVj1 corresponding to the first input terminal )
2-input NAND type gate circuit Gj (only G1 is shown) which receives the switching control signal SW at its second input terminal, and an inverter IVj2 (only IV12 is shown) which inverts the output signals of these gate circuits Gj. When a defective memory cell exists in the memory cell arrays MA1 to MA4 and a defective memory cell does not exist in the memory cell arrays MA1 to MA4, a plurality of fuses Fj are programmed to detect the defective memory cell in the memory cell arrays MA1 to MA4. Selected block setting circuit 2 for generating a programming signal for setting the block selection signals (BS1 to BS4) corresponding to a predetermined nonexistent memory cell array to the selection level
1, a fuse F5 as a programmable non-volatile memory element whose one end is connected to the ground potential point, a transistor Q5 whose source is connected to the other end of this fuse F5 and whose gate and drain are connected to the power supply potential point, and these fuses F5
"1" is detected at the level of the connection point between the transistor and the transistor Q5.
Or an inverter IV5 that outputs a "0" level signal
1 and an inverter IV52 for inverting the level of the output signal of the inverter IV51, and the memory cell array M
If one of A1 to MA4 includes a defective memory cell and a defective memory cell does not exist, the fuse F5
And a switching control circuit 22 for programming an active level switching control signal SW and an inverter IV for generating a complementary signal of the second address signals AD1 and AD2.
1, IV2, the first input terminal receives the switching control signal SW, and the second input terminal receives the true / false status of the second address signals AD1 and AD2.
Two-input NOR type gate circuits G11 to G14 which receive complementary signals respectively, and a programming signal from the selection block setting circuit 21 is input to the first input terminal and output signals of the gate circuits G11 to G14 are input to the second input terminal. Two-input NOR type gate circuits G15 to G1 which respectively receive
8. A two-input NAND which receives the output signals of these gate circuits G15 to G18 at its first input terminal and receives the internal address activation signal IAE at its second input terminal, respectively.
Type gate circuits G19 to G22 and block selection signals BS1 to BS4 from the output terminals of the gate circuits G19 to G22 which receive the output signals of the gate circuits G19 to G22 at their first and second input terminals and decode them.
Two-input NOR type gate circuits G23 to G26 having one of them as a selection level are provided, and when a switching control signal SW is at an active level, a predetermined memory among a plurality of memory cell arrays MA1 to MA4 is provided according to the programming signal. When the block selection signal corresponding to the cell array is set as the selection level and the inactive level is set, a switching / decoding circuit 23 for setting the block selection signal corresponding to the memory cell array designated by the second address signals AD1 and AD2 as the selection level is included. To be done. In addition, the fuses F1 to F
The fuse circuits 211 to 214 have the same configuration and each of the four circuits outputs the configuration bit of the programming signal.
Is displayed as.

In the block selection circuit 2, when the fuses F1 to F5 are not blown at all, the switching control signal SW becomes inactive level and all bits of the programming signal become low level of inactivation level. , When the true / complementary signals of the second address signals AD1 and AD2 pass through the gate circuits G11 to G14 and G15 to G18, and the internal address activation signal IAE becomes the activation level (high level), the gate circuits G19 to G19 to The block select signal (one of BS1 to BS4) corresponding to the designated address of the second address signals AD1 and AD2 is passed through G22 and decoded by the circuit including the gate circuits G23 to G26, and becomes the selection level.

When some of the memory cell arrays MA1 to MA4 have defective memory cells and some have no defective memory cells, first, the fuse F5 is blown to set the switching control signal SW to the active level (high level). . As a result, the gate circuits G11 to G14 inactivate the second address signals AD1 and AD2 and activate the programming signal. Which of the fuses F1 to F4 is to be cut (C) (programmed) is
It is determined by which block selection signal (BS1 to BS4) is set to the selection level. For example, if the memory capacity is 1
Block selection signal BS1
When the voltage is set to the selection level, the fuses F1 and F3 are blown.

At the cut points of the fuses F1 to F4, the fuse F1 becomes a true signal of the second address signal AD1.
F2 corresponds to the complementary signal of AD1, F3 corresponds to the true signal of the second address signal AD2, F4 corresponds to the complementary signal of AD2, and the true / complement of the second address signals AD1 and AD2. The "low level" of the signal corresponds to the "cutting" of the fuses F1 to F4. Therefore, which fuse should be blown can be extremely easily determined from the relationship between the second address signals AD1 and AD2 and the block selection signals BS1 to BS4.

FIG. 3 is a circuit diagram showing a concrete circuit example of the block selection circuit according to the second embodiment of the present invention.

Block selection circuit 2 in the first embodiment
Then, the transistor Q1 of the fuse circuits 211 to 214
Since ~ Q4 (only Q1 is displayed) is always on, a current path is formed by these transistors Q1 to Q4 and fuses F1 to F4 between the power supply potential point and the ground potential point, and a constant current flows, When the number of memory cell arrays and the number of divided memory cell arrays increase, the power consumption due to this current increases.

Therefore, in the second embodiment, an external address take-in signal EAL (a signal for taking in an external address signal AD to the address buffer circuit 1 or the like) is applied to the gate of the transistor Qj (j = 1 to 4). An inverter IVj3 having a deactivation control signal terminal whose input and output terminals are inversely connected to the inverter IVj1 is provided to form a holding circuit, and a transistor is provided when the external address take-in signal EAL is at an active level (high level). Fuse circuits 211a to 21 configured to turn on Qj and take in the level of the connection point between the transistor Qj and the fuse Fj at this time to the holding circuit formed by the inverters IVj1 and IVj3.
By setting 4a, the external address take-in signal EAL
Except during the active level period, the current path by the fuse Fj and the transistor Qj and the inverters IVj1 and Ij
The current is prevented from flowing to Vj3 to reduce the power consumption.

The power-on signal PON is input to the deactivation control signal terminal of the inverter IVj3, and this signal (PO
When N) is in an active level (high level) in a transient state immediately after power-on, the holding circuit is deactivated to prevent an unstable level from being taken.

The other parts are similar to those of the first embodiment, and similar effects can be obtained. For reference, FIG. 4 shows a timing chart of signals in each part of the second embodiment. In addition,
In these embodiments, the resistance values of the fuses F1 to F5 and the on-resistances and off-resistances of the transistors Q1 to Q5 have clear levels of disconnection and non-disconnection of the fuses F1 to F5 with respect to the threshold voltages of the burners IVj1 and IV51. It is clear that the holding level of the holding circuit is set to a value that does not change when the transistors Q1 to Q5 are turned off.

FIG. 5 is a circuit diagram showing a concrete circuit example of a part of the block selection circuit according to the third embodiment of the present invention.

In the first and second embodiments, which of the block selection signals BS1 to BS4 is set to the selection level is programmed by the fuses F1 to F5, but in the third embodiment, the EPROM is used. Elements MC1 to MC
5 (MC2 to MC4 are not shown) for programming. EPROM elements MC1 to M
To write to C5, a predetermined high voltage (for example, 7V) is applied to the pads PD1 to PD4 and PD51, PD52 is connected to the ground potential point, and a predetermined voltage (for example, 7V) is applied to the external address take-in signal EAL input terminal. Then, the threshold voltage is changed. After programming, pads PD1-P
D4 and PD51 are connected to a predetermined potential point (for example, ground displacement point).

In this embodiment, the memory cell array is EP
If it is composed of ROM elements, there is an advantage that the EPROM elements MC1 to MC5 can be formed in the same step as the memory cell array. Other parts are the same as those of the first and second embodiments, and the same effects as those of these embodiments can be obtained.

FIG. 6 is a circuit diagram showing a concrete circuit example of the block selection circuit according to the fourth embodiment of the present invention.

In the block selection circuit 2b of this embodiment, a programmable nonvolatile memory element fuse Fj (j = 1 to 4) having one end connected to the ground potential and a source connected to the other end of the corresponding fuse Fj. An inverter that detects the level of the transistor Qj (only j = 1 is shown) that connects the gate and drain to the power supply potential point, the connection point of the corresponding fuse Fj and transistor Qj, and outputs a signal of "1" or "0" level. IVj1 (only j = 1 is shown),
And an inverter IVj2 (only j = 1 is shown) for inverting the level of the output signal of the corresponding inverter IVj1.
When some of the plurality of memory cell arrays MA1 to MA4 include defective memory cells and some of which do not exist, the fuse Fj is programmed to determine that the defective memory cells of the memory cell arrays MA1 to MA4 do not exist. Selected block setting circuit 21c for generating a fixed block selection signal in which only the block selection signal (a predetermined one of BS1 to BS4) corresponding to the memory cell array is fixed to the selection level, and the second address signal AD1, Inverters IV1 and IV2 for generating a level inversion signal (complementary signal) of AD2, second address signal AD
2-input NOR for decoding 1, AD2 and its complementary signal
Type gate circuits G23 to G26, and inverters IV3 to IV6 for inverting the levels of the output signals of the gate circuits G23 to G26, respectively.
Decoding circuit 24 that outputs an addressing block selection signal having block selection signals (BS1 to BS4) corresponding to the memory cell arrays specified by D1 and AD2 as selection levels.
A 4-input NOR type gate circuit G27 for inputting all the constituent bits of the fixed block selection signal, an inverter IV7 for inverting the level of the output signal of the circuit G27,
Two-input NOR type gate circuits G11 to G14 each of which receives a corresponding bit of the addressing block selection signal at its first input terminal and each of which receives an output signal of the inverter IV7 at its second input terminal. Two-input NOR type gate circuits G15 to G18 for receiving corresponding bits of the fixed block selection signal and receiving corresponding output signals of the gate circuits G11 to G14 at their second input terminals, and their first input terminals respectively. A 2-input NAND type gate circuit G which receives the corresponding output signals of the gate circuits G15 to G18 and receives the internal address activation signal IAE at the second input terminal.
19 to G22 and memory cell arrays MA1 to MA4
If there is a defective memory cell in the memory cell array, and if there is a defective memory cell in the memory cell array, the fixed block selection signal is selected, and if there is no defective memory cell in each of the memory cell arrays MA1 to MA4, the address designation is performed. Select the block selection signal to select the memory cell arrays MA1 to MA1.
Block selection signals BS1 to B corresponding to the respective MA4
And a switching circuit 25 for outputting as S4. A circuit having the same configuration that outputs the constituent bits of the fixed block selection signal including each fuse Fj is shown as a fuse circuit 21jb.

In this embodiment, when there is no defective memory cell in all the memory cell arrays MA1 to MA4 and all the fuses Fj are not blown, the fixed block selection signal is at the inactive level (all bits). (Low level), the addressing block selection signal passes through the gate circuits G11 to G14 and G15 to G18 and then the gate circuits G19 to G22, and is output as the block selection signals RS1 to BS4.

When the memory cell arrays MA1 to MA4 include defective memory cells and non-defective memory cells, a predetermined memory cell array having no defective memory cells, for example, a fuse F1 corresponding to MA1.
Disconnect. As a result, the addressing block selection signal is inactivated by the output of the inverter IV7, and the constituent bits of the fixed block selection signal of the high level corresponding to the fuse F1 pass through the gate circuits G15 and G19 and the block selection signal BS1. Is the selection level.

In this embodiment, only the fuse corresponding to the selected memory cell array needs to be blown, so that the first
There is an advantage that programming is extremely easy as compared with the above-mentioned embodiment and that there is one fuse and the number of circuit elements is reduced. Other parts are similar to those of the first embodiment, and similar effects can be obtained.

In the above embodiment, the case where the fuse and the EPROM element are used as the programmable non-volatile memory element has been described, but other PROM elements,
For example, it may be a diode element or the like. Further, the fuse circuit of the second embodiment and the PROM circuit of the third embodiment can be applied to the fuse circuit of the fourth embodiment, and other combinations are possible.

As described above, the plurality of memory cell arrays may be repaired by the redundant circuit or may not be repaired without the redundant circuit. Resource saving can be further promoted with the relief processing, and resource saving can be achieved with the resource saving, and the chip area can be reduced by the amount of the redundant circuit and the man-hour required for the relief processing can be reduced. There is an advantage that it can be omitted.

[0046]

As described above, according to the present invention, when there is no defective memory cell in each of the plurality of memory cell arrays, the block corresponding to the second address signal designated memory cell array among the plurality of memory cell arrays. When the selection signal is set to a selection level and one of the plurality of memory cell arrays has a defective memory cell and the other of which does not exist, a predetermined memory cell of the plurality of memory cell arrays does not have a predetermined memory cell. A block selection circuit that fixes only the block selection signal corresponding to the memory cell array to the selection level regardless of the designation of the second address signal is provided, and writing and reading are performed on the memory cell array corresponding to the block selection signal of the selection level. Conventionally, one of the memory cell arrays can be configured It was discarded if there was a memory cell array with defective memory cells, but if there is at least one memory cell array without defective memory cells, it can be used as a good product, which is a waste of resources and manufacturing. There is an effect that the waste of various steps can be reduced and the cost can be reduced accordingly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

2 is a circuit diagram showing a specific circuit example of a block selection circuit of the embodiment shown in FIG. 1 and a diagram showing an input signal thereof and an output signal level with respect to a fuse blown state.

FIG. 3 is a circuit diagram showing a specific circuit example of a block selection circuit according to a second embodiment of the present invention.

FIG. 4 is a timing diagram of signals of respective parts of the second embodiment including the circuit shown in FIG.

FIG. 5 is a partial circuit diagram showing a specific circuit example of a block selection circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific circuit example of a block selection circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a conventional semiconductor memory device.

8 is a circuit diagram showing a specific circuit example of a redundant row selection circuit of the semiconductor memory device shown in FIG.

[Explanation of symbols]

1, 1x address buffer circuit 2, 2a, 2b block selection circuit 3, 3x data input / output buffer circuit 21, 21a, 21b, 21c selection block setting circuit 22, 22a, 22b switching control circuit 23 switching / decoding circuit 24 decoding circuit 25 Switching circuit 211-214, 211a-214a, 211b-21
4b Fuse circuit 215 PROM circuit CSA1 to CSA4, CSAx column selection / amplification circuit F1 to F5, F11, F12 to Fn1, Fn2 Fuse MA1 to MA4, MAx memory cell array MC1 to MC5 EPROM device Q1 to Q5, Q11, Q12 to Qn1, Qn2, Qp
Transistor RCSA Redundant column selection / amplification circuit RMAc Redundant memory cell column RMAr Redundant memory cell row RRS Redundant row selection circuit RS1 to RS4, RSx row selection circuit

Claims (11)

[Claims] 1. A plurality of memory cell arrays each of which has a plurality of memory cells and reads stored data from a memory cell in a selected state among the plurality of memory cells, and a plurality of memory cell arrays provided corresponding to the plurality of memory cell arrays, respectively. A plurality of address selection circuits for selecting a memory cell of an address designated by a first address signal in a corresponding memory cell array when a corresponding block selection signal is at a selection level; and a defective memory cell in each of the plurality of memory cell arrays. Is not present, the block selection signal corresponding to the memory cell array designated by the second address signal among the plurality of memory cell arrays is set to the selection level, and the defective memory cell is present in the plurality of memory cell arrays. If there are some memory cells that do not exist, And a block selection circuit for fixing only a block selection signal corresponding to a predetermined memory cell array in which no defective memory cell exists in the ray to the selection level regardless of the designation of the second address signal. Semiconductor memory device. 2. The plurality of non-volatile circuits when the block selection circuit includes a plurality of programmable non-volatile memory elements and includes one of a plurality of memory cell arrays having a defective memory cell and one having no defective memory cell. A selected block setting circuit for programming a memory element to generate a programming signal for setting a block selection signal corresponding to a predetermined memory cell array in which no defective memory cell exists among the plurality of memory cell arrays to a selection level; When a programmable non-volatile memory element is provided and one of the plurality of memory cell arrays has and does not have a defective memory cell, the non-volatile memory element is programmed and an active level switching control signal is programmed. And a switching control circuit that generates the In the case of, the block selection signal corresponding to a predetermined memory cell array among the plurality of memory cell arrays is set as a selection level according to the programming signal, and when it is inactive level, the block selection signal corresponding to the memory cell array designated by the second address signal is set. 2. The semiconductor memory device according to claim 1, comprising a switching / decoding circuit for setting a selection level. 3. The semiconductor memory device according to claim 2, wherein the programming signal is set to an inactive level in response to the inactive level of the switching control signal. 4. The plurality of non-volatile circuits when the block selection circuit includes a plurality of programmable non-volatile memory elements and includes one of a plurality of memory cell arrays in which a defective memory cell exists and one of which does not exist. Block setting circuit for programming a static memory element to generate a fixed block selection signal in which only a block selection signal corresponding to a predetermined memory cell array among the plurality of memory cell arrays in which no defective memory cell exists is fixed to a selection level A decoding circuit for outputting an addressing block selection signal having a block selection signal corresponding to the second address signal designating memory cell array as a selection level; and a defective memory cell among the plurality of memory cell arrays. And the nonexistent fixed block selection signal And a switching circuit for selecting the addressing block selection signal and outputting it as a block selection signal corresponding to each of the plurality of memory cell arrays when there is no defective memory cell in each of the plurality of memory cell arrays. Claim 1 composed of
The semiconductor memory device described. 5. A programmable non-volatile storage element comprising:
5. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is formed of a fuse element that stores binary information in a conductive state and a non-conductive state. 6. A programmable non-volatile storage element comprising:
EPRO that stores binary information depending on the threshold voltage
The semiconductor memory device according to claim 2, wherein the semiconductor memory device is formed of an M element. 7. The selection block setting circuit includes a plurality of nonvolatile memory elements provided corresponding to the true / complementary signals of the respective constituent bits of the second address signal, and the plurality of nonvolatile memory elements. 3. The semiconductor memory device according to claim 2, wherein is programmed in correspondence with a true / complement signal of each constituent bit of the second address signal. 8. A selected block setting circuit includes a plurality of nonvolatile memory elements provided corresponding to a plurality of memory cell arrays, respectively, and a nonvolatile memory element corresponding to the memory cell array corresponding to a block selection signal to be a selection level. 5. The semiconductor memory device according to claim 4, wherein the memory state of only one is changed. 9. The selected block setting circuit comprises a plurality of nonvolatile memory element circuits each corresponding to each of the plurality of nonvolatile memory elements and including one corresponding nonvolatile memory element, and each of these nonvolatile memory element circuits. Of the nonvolatile memory element connected in series between the reference potential point and the power source potential point and a transistor which is turned on / off in response to an external address take-in signal, and a series connection point of the nonvolatile memory element and the transistor. 5. The semiconductor memory device according to claim 2, further comprising: a holding circuit that detects a level of the external address take-in signal at an active level and holds the level at a predetermined level. 10. A non-volatile memory element in which a switching control circuit is connected in series between a reference potential point and a power source potential point, a transistor which is turned on / off in response to an external address take-in signal, and these non-volatile memory elements. 3. The semiconductor memory device according to claim 2, further comprising: a holding circuit that detects the level of the external address signal fetch signal at the active level of the serial connection point of transistors and holds the level at a predetermined level. 11. A semiconductor memory device having a redundant circuit including a plurality of redundant memory cells, wherein a plurality of defective memory cells are present in the plurality of memory cell arrays by the redundant circuit. Substituting the plurality of defective memory cells so as to read corresponding stored data in place of the predetermined memory cells when the predetermined defective memory cells are addressed by the first address signal. 2. The semiconductor memory device according to claim 1, wherein the memory cell array is processed.