JPH07288465A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a circuit that is resistant to noise and is faster than a fully complementary static CMOS circuit. [Structure] A P-type logical block and an N-type logical block
A completely complementary static CMOS circuit is constructed, and the output of this static CMOS circuit is precharged to the power supply potential by a precharge element. [Effect] Since the signal propagation delay occurs only when the N-type logic block is conductive, the circuit operation becomes faster.
Further, it is possible to suppress the generation of α-ray noise, charge redistribution, or noise due to leak current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a semiconductor integrated circuit device forming a central data processing device, a peripheral device, a memory device and the like which are components of a computer. In particular, the present invention is suitable for devices that require high reliability and high performance, such as parallel processing computers and space semiconductor integrated circuit devices.

[0002]

2. Description of the Related Art In recent years, the performance of computers has improved remarkably. As a typical circuit technology that supports this progress, perfect complementary static CMOS (Complementary metal)
oxide semiconductor) circuit. It consumes less power than a bipolar circuit and is highly integrated.
As is well known, in a fully complementary static CMOS circuit, a P-type logic block composed of P-type MOS transistors and an N-type logic block composed of N-type MOS transistors are connected in series, and two logic blocks operate in a complementary manner. To do. The rise time of the output signal depends on the characteristics of the PMOS transistor, and the fall time of the output signal depends on the characteristics of the NMOS transistor. By the way, generally, the gain coefficient β of the PMOS transistor is smaller than the gain coefficient β of the NMOS transistor. Therefore, when the channel width and the channel length of the PMOS transistor and the NMOS transistor are designed to be equal, the rise time of the output signal is later than the fall time. On the contrary, in order to make the rise time and the fall time of the output signal equal, it is necessary to make the channel width of the PMOS transistor larger than the channel width of the NMOS transistor, which causes an increase in input capacitance and an increase in area.

As an example of a circuit for solving the problem of the completely complementary static CMOS circuit, a CMO is used.
S Domino logic circuit (RHKRAMBECK, CHARLES
M.LEE and HUNG-FAI STEPHEN LAW, "High-Speed Comp
act Circuits with CMOS, "IEEE JOURNAL OF SOLID-STA
TE CIRCUITS, VOL.SC-17, NO.3, JUNE 1982). An example of the CMOS domino circuit is shown in FIG. CMOS domino circuit is NM
It is a dynamic circuit that constitutes logic only by OS transistors. Therefore, the signal propagation delay is NMO.
It depends on the characteristics of the S transistor. There is no problem of increase in delay time due to the P-type logic block, which is a problem in the fully complementary static CMOS circuit. Further, since the logic is configured only by the N-type logic block, the input capacitance and the parasitic capacitance inside the circuit are small, so that the operation speed is high and the area is small.
However, the CMOS domino circuit has the following three problems. First, since the CMOS domino circuit is a dynamic circuit, it is vulnerable to α-ray noise. FIG. 10 shows a circuit diagram and operation waveforms. In the CMOS domino circuit, the precharge operation is performed while the clock signal input to the circuit is low level, and the logic propagates during the high level period. When the input signal is at the low level during the logic determination period when the clock signal is at the high level, the node A point is at the high level and the electric charge at the point A is dynamically retained. At this time, if the α-ray hits the drain of the N-type transistor 100, the electric charge at the point A is discharged and the potential level at the point A is lowered. Since there is no path for charging the discharged electric charge, the potential level once lowered does not return to the original and causes a malfunction. Secondly, since the CMOS domino circuit is a dynamic circuit, it is vulnerable to leak current noise. When the input signal is at the low level during the logic determination period when the clock signal is at the high level, the node A point is at the high level and the electric charge at the point A is dynamically retained. At this time, the electric charge at the point A is discharged by the leak current through the N-type transistor, and the potential level at the point A is lowered.
Since there is no path for charging the discharged electric charge, the potential level once lowered does not return to the original and causes a malfunction. Third,
This is the problem of charge redistribution shown in FIG. The capacitance of the node A of the CMOS domino circuit is CA, and the capacitance of the node B is C.
Let B. When the input signal A is low level and the input signal B is high level in the logic determination period 1, the potential at the node A is high level “Vdd” and the potential at the node B is low level “0V”. Since the NMOS transistors 101 and 102 are off during the precharge period, the node A
The potential at the point is high level “Vdd”, and the node B is “0V”
It remains. Next, in the logic determination period 2, when the input signal A becomes high level, the NMOS transistor A is turned on, the charge is redistributed between the node A and the node B, and the points A and B are distributed. The potential of "(CA / (CA + C
B)) Vdd ”. When the capacitances of CA and CB are almost equal, the potentials at points A and B are approximately“ (1/2) Vd ”.
d ”, which causes malfunction.

A method of adding a feedback pull-up PMOS transistor 103 shown in FIG. 12 has been proposed as a means for solving the problems of α-ray noise, leak current and charge redistribution, which are the problems of the CMOS domino circuit. The point A of the dynamic node is weakly pulled up by the feedback pull-up PMOS 103 to compensate the α-ray noise and the charge discharged by the charge redistribution. However, the N-type logic block 10
The feedback pull-up PMOS transistor 103 prevents this when the node 4 draws the electric charge from the node A to the low level. Not only does the through current flow, power consumption increases, but also the switching speed of the circuit significantly decreases. Therefore,
Since this means impairs high speed, it cannot be applied to a system that requires high speed circuit.

[0005]

As described above, the CMOS domino circuit has been proposed as a higher speed circuit than the completely complementary static CMOS circuit, but there is a problem that it is vulnerable to noise. On the other hand, if a pull-up PMOS transistor is added to make it resistant to noise, high speed performance will be impaired. The problem to be solved by the present invention is to achieve both high noise resistance and high speed. That is, an object of the present invention is to provide a circuit which is resistant to noise and which is faster than a completely complementary static CMOS circuit.

[0006]

Means for Solving the Problems FIG. 1 shows means for solving the problems. The source and the drain are connected in series or in parallel between the first power supply terminal 111 and the first internal terminal 109, and the gate is connected to the input terminal 108. 1
A P-type logic block 105 including one or more P-type field effect transistors, a source and a drain are connected in series or in parallel between the second power supply terminal 112 and the first internal terminal 109, and a gate is the input terminal 108. Connected to
An N-type logic block 106 including one or more N-type field effect transistors, and a P-type logic block 105 and N
The type logic block 106 constitutes a completely complementary static CMOS circuit which operates in a complementary manner. First internal terminal 109
An inverter circuit 138 is connected in series between the output terminal 139 and the output terminal 139. Further, the source and drain are connected to the N-type logic block 106 and the second power supply terminal 112, and the gate is connected to the N-type field effect transistor 137 to which the clock signal CK is input. The first precharge element 107 that precharges the power supply potential of the first power supply terminal 111 and the first internal terminal 1
It is connected to 09. The clock signal CK is input to the control terminal of the precharge element 107.

[0007]

First, the operation of the circuit of the present invention will be described with reference to FIG. The clock signal CK is input to the N-type field effect transistor 137 and the first precharge element 107 of this circuit. Here, the potential of the first power supply terminal 111 is set to Vdd
(Hereinafter referred to as high level), and the second power supply terminal 112
Is set to Vss (hereinafter referred to as low level). While the potential of the clock signal CK is low level, the potential of the first internal terminal 109 is precharged to high level, and the potential of the output terminal 139 is low level. This circuit performs the logic determination operation during the period when the clock signal CK is at the high level. Even if the input signal changes during the precharge period when the potential of the clock signal CK is low level, the potential of the output terminal 139 remains low level. Clock signal CK
The input signal changes from the low level to the high level during the logic determination period in which the potential of the
6 from the first internal terminal 109 to the second power supply terminal 11
The potential of the output terminal 139 changes to a high level when the series path to 2 becomes conductive. That is, the signal propagation delay of this circuit occurs only when the N-type logic block 106 becomes conductive. As described above, since the gain coefficient β of the N-type field effect transistor is higher than the gain coefficient β of the P-type field effect transistor, that is, the N-type logic block 10
The circuit is fast, which causes a signal propagation delay only when 6 is conducting. Further, the P-type field effect transistor forming the P-type logic block only needs to compensate for the leak current and the external noise current of the N-type logic block 106 and does not require a large load driving force. P
The channel width of the N-type field effect transistor can be designed to be sufficiently smaller than about 50% as compared with the channel width of the N-type field effect transistor. On the other hand, in the case of the fully complementary static CMOS circuit of the prior art, in order to make the load driving force of the P-type field effect transistor whose gain coefficient β is smaller than that of the N-type field effect transistor equal to that of the N-type field effect transistor, The field effect transistor channel width is set to 2 of the channel width of the N-type field effect transistor.
Design twice as large. The input capacitance of the circuit of the present invention in which the channel width of the P-type field effect transistor is 50% or less of the channel width of the N-type field effect transistor has a channel width of the P-type field effect transistor that is 2 times that of the N-type field effect transistor. It is as small as 50% of the input capacitance of the fully complementary static CMOS circuit that cannot obtain high speed unless it is designed to be twice as large. Therefore, the fan-out capacitance is smaller than that of the fully complementary static CMOS circuit,
Higher speed can be obtained. Further, since the channel width of the P-type field effect transistor is small, the diffusion capacitance of the P-type field effect transistor is completely complementary static C.
It is smaller than the MOS circuit. This is also an important factor that enables the high speed operation of the circuit of the present invention.

Another effect of the circuit of the present invention is high noise resistance. The circuit of the present invention includes the P-type logic block 105 including the P-type field effect transistor as described above.
N-type logic block 1 including N-type field effect transistor
06 is connected in series between the first power supply terminal 111 and the second power supply terminal 112, and the P-type logic block 105 and the N-type logic block 106 form a completely complementary static CMOS circuit that operates complementarily. . Therefore, the circuit of the present invention does not perform a dynamic operation like the CMOS domino circuit of the above-mentioned prior art example, but performs a static operation. Therefore, even if leak current, α-ray noise, charge redistribution, or noise due to the power supply line or the signal line is generated in the circuit of the present invention, the P-type logic block 105 and the N-type logic block 106 that perform static complementary operation are generated. By always pulling up or pulling down the first internal terminal 109 to the first or second power supply potential, it is possible to minimize the occurrence of noise. Alternatively,
Even if the output potential is inverted due to noise, it can be returned to the correct potential level.

In order to realize higher speed circuit performance, it is preferable that the channel width of the P-type field effect transistor forming the P-type logic block 105 is smaller. On the other hand, in order to improve the noise resistance, it is necessary to set the channel width of the P-type field effect transistor to a certain value or more. Therefore,
The channel width of the P-type field effect transistor needs to be determined from both the high speed and the noise resistance required by the system to which the circuit of the present invention is applied. In a general use-level environment, the channel width of the P-type field effect transistor forming the P-type logic block 105 is about 50% or less of the channel width of the N-type field effect transistor forming the N-type logic block 106. Even if it is designed small, sufficient noise resistance can be obtained. Hereinafter, the circuit of the present invention will be referred to as a static domino type CMOS logic circuit.

[0010]

FIG. 2 shows an example of a parallel computer system constructed according to the present invention. A plurality of central processing units 119 including processors and memories are connected by a connection network 120 to form one computer system. The central processing unit 119 is also connected to the hard desk 121. By connecting a plurality of central processing units 119, it is possible to realize a computer system having a performance that is many times higher than that of a system composed of one central processing unit 119. Here, the central processing unit 119 may be connected to several to several thousands. In order for these central processing units 119 to operate without failure for a long period of time, each central processing unit 119 must have high reliability. Further, in order to realize a higher performance parallel computer system, each central processing unit 119 must have high performance. That is, the central processing unit 119 shown in this parallel computer system example must have high reliability and high speed. As a means for realizing the central processing unit 119 having such characteristics, the circuit of the present invention having high noise resistance and high speed is suitable.

FIG. 3 shows the central processing unit 11 shown in FIG.
9 is an example of the internal configuration, and is composed of one chip or a plurality of chips. The internal components are the floating point register file 122, the floating point adder 123, the floating point multiplier 124, the floating point divider 125, the general registers 126, ALU127, ALU128, the address adder 129, the data cache 130, the data TLB131, The instruction TLB 132, the instruction cache 133, and the like. Floating point register 12
2 and the general-purpose register 126 are used for the data cache 13
Combined with 0, address adder 129 and instruction control unit 135 are combined with instruction cache 133. The data cache 130 and the instruction cache 133 access data from a plurality of external terminals 136. The floating point arithmetic units 122 to 125 are connected by the first local bus or local path. Integer calculator 126-
129 are coupled by the second local bus or local path. Central processing unit 11 having such a configuration
9, the circuit of the present invention is mainly used as an internal circuit which constitutes each unit of 122 to 135. In addition, depending on the case, it is applied to a buffer circuit that couples each unit or an input / output circuit with an external chip.

The circuit of the present invention can be applied not only to computer systems but also to other systems that require high reliability and high speed.

FIG. 4 shows an example in which a plurality of the circuits of the present invention shown in FIG. 1 are connected in series. The circuit operation when a plurality of circuits according to the present invention are connected in series in this manner will be described below. In this embodiment, the precharge element is composed of the P-type field effect transistor 107. During the precharge period, the clock signal CK becomes low level, the N-type field effect transistor 137 is turned off, and the precharge element 107 composed of the P-type field effect transistor is turned on. Therefore, the output terminal 11
6, 117 and 118 are all at low level. Therefore, the static domino type CMOS logic circuits 113, 1
All of the N-type logic blocks 14 and 115 are turned off. During the logic determination period, the clock signal CK becomes high level and N
The type field effect transistor 137 is turned on, and the precharge element 107 made of a P type field effect transistor is turned off. At this time, for example, if the N type logic block of the static domino type CMOS logic circuit 113 is turned on, the output terminal 116 becomes high level. When the N-type logic block of the static domino type CMOS logic circuit 114 is turned on according to the input signal, the output terminal 117 becomes high level. In this way, signals propagate one after another like dominoes. Since the signal propagates by the operation of the N-type logic block having a large gain coefficient β, high speed can be obtained.

FIG. 5 shows an example in which the logic shown in FIG. 5A is shown in a transistor level circuit diagram in FIG. Figure 5 (a)
The OR circuits 161, 162, 163 shown in FIG.
Corresponding to the circuits 161, 162, 163 shown in
The buffer circuit 164 shown in FIG. 5A corresponds to the circuit 164 shown in FIG.

Static domino type CM according to the present invention
The OS logic circuit has a problem that it cannot execute the logic judgment operation during the precharge operation, but it will be explained that the OS logic circuit can perform continuous logic judgment operations by adopting the following configuration. FIG. 6 shows a configuration example of a static domino type CMOS logic circuit which operates in one clock cycle. The clock signal shows the case where a two-phase clock of CK1 and CK2 is used. Logic circuit is static domino type C
A preceding logic circuit group 168 composed of MOS logic circuits;
Similarly, it is composed of a logic circuit group 169 in the subsequent stage which is composed of a static domino type CMOS logic circuit. Latch circuits 165 and 167 that operate in synchronization with the clock signal CK2 are connected to the start point and the end point of the 1-cycle logic, respectively. A latch circuit 16 that operates in synchronization with the clock signal CK1 is provided between the logic circuit group 168 in the front stage and the logic circuit group 169 in the rear stage.
Connect 6 The static domino CMOS logic circuit of the logic circuit group 168 in the front stage is connected to the clock signal CK1, and the static domino CMOS logic circuit of the logic circuit group 169 in the rear stage is connected to the clock signal CK2.
Clock signal CK1 is high level, clock signal CK2
Is low level, the logic circuit group 168 in the previous stage is in the logic determination period and the signal is propagating, the logic circuit group 169 in the subsequent stage is in the precharge period, and all the output terminals in the subsequent stage are at the low level. On the other hand, when the clock signal CK1 is low level and the clock signal CK2 is high level,
The preceding logic circuit group 168 is in the precharge period, all output terminals are at the low level, and the following logic circuit group 1
69 is a logic determination period in which a signal propagates. In this way, by dividing the logic of one cycle into the front stage and the rear stage and alternately performing the precharge operation and the logic determination operation every half cycle, it becomes possible to execute the continuous logic determination operation for one cycle.

Next, the static domino type CMOS logic circuit according to the present invention and the conventional complete complementary type CM.
An embodiment in which OS circuits are mixed and configured will be described. FIG. 7 shows a block diagram of a logical block that operates in one clock cycle. First, the logic block in the preceding stage is composed of a logic block 170 composed of a completely complementary CMOS circuit,
The subsequent logic block is composed of a logic block 171 composed of a completely complementary CMOS circuit. Latch circuits 165 and 167 connected to the clock signal CK1 are connected to the start point and the end point, respectively. A latch circuit 166 connected to the clock signal CK2 is connected between the preceding logic block 170 and the following logic block 171. Previous logic block 1
A logic block 172 composed of a static domino type CMOS logic circuit according to the present invention is connected between 70 and the logic block 171 in the subsequent stage. Logic block 17
The latch circuit 173 is connected between 2 and the logic block 171, and the logic block 172 and the latch circuit 173 are connected to the clock signal CK2. In such a configuration, the logic block 172 performs a precharge operation when the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, and the logic block 172 performs a logic determination operation when the clock signal CK1 is at a low level and the clock signal CK2 is at a high level. To do. In the path from the logic block 170 in the preceding stage to the logic block 172, the clock signal CK
It is necessary to determine the input signal of the logic block 172 within the period in which 2 is low level. In the path from the logic block 172 to the logic block 171, the input signal of the latch circuit 173 needs to be determined within the period when the clock signal CK2 is at the high level.

FIG. 8 shows a static domino type CMOS logic circuit according to the present invention and a fully complementary C type circuit of the prior art.
Another embodiment in which MOS circuits are mixed and configured will be described. FIG. 8 shows a block diagram of a logic block that operates in one clock cycle. First, the logic block in the former stage is composed of a logic block 172 formed by the static domino type CMOS logic circuit according to the present invention and a CMOS block 170 composed of a completely complementary CMOS circuit, and the latter logic block is composed of a completely complementary CMOS circuit. It is composed of a CMOS block 171. A latch circuit 165 is connected between the preceding logic block 172 and the logic block 170,
The logic block 172 and the latch circuit 165 are connected to the clock signal CK1. A latch circuit 166 is connected between the logic block 170 and the logic block 171, and a latch circuit 167 is connected to the end point of the 1-cycle logic. The latch circuit 166 is connected to the clock signal CK2, and the latch circuit 1
67 is connected to the clock signal CK1. In such a configuration, when the clock signal CK1 is at the high level and the clock signal CK2 is at the low level, the logic block 172 executes the logic determination operation, and the clock signal CK1 is at the low level.
Logic block 1 when clock signal CK2 is at high level
72 performs a precharge operation. The input signal of the logic block 172 needs to be determined within the period of low level of the clock signal CK1, and the input signal of the latch circuit 166 needs to be determined within the period of high level of the clock signal CK1.

FIG. 13 shows an embodiment of a 4OR circuit using a static domino type CMOS logic circuit according to the present invention. The circuit configuration will be described based on the correspondence between the components shown in FIGS. The P-type logic block 105 shown in FIG.
Four-stage P-type field effect transistor 140 connected in series
Corresponding to. The N-type logic block 106 in FIG. 1 corresponds to the N-type field effect transistor 141 connected in parallel in four stages in FIG. The N-type field effect transistor 137 of FIG. 1 corresponds to the N-type field effect transistor 137 of FIG. 13, and the precharge element 107 of FIG. 1 corresponds to the P-type field effect transistor 107 of FIG. 108 is an input terminal, 13
9 is an output terminal. In the 4OR circuit, since the P-type field effect transistors are connected in series in four stages, the low gain coefficient β of the P-type field effect transistors has a large effect on the switching speed and the rise delay time of the internal terminal 109 is large. Therefore, in an OR system circuit in which P-type field effect transistors are connected in series in multiple stages like a 4OR circuit,
The effect of increasing the speed of the static domino type CMOS logic circuit of the present invention is remarkable. FIG. 14 shows a layout diagram of this circuit. The numbers indicating the parts in the circuit diagram of FIG. 13 are the same as the corresponding parts in FIG. The scale on the vertical and horizontal axes is indicated by the layout pitch. In FIG. 14, the vertical and horizontal unit pitch lengths are drawn differently for the sake of easy viewing of the drawing, but it is assumed that the actual vertical and horizontal unit pitch lengths are the same. According to this layout, the width is 9 pitches,
The height is 14 pitches, and the cell area is 126 square pitches. The same logic as the 4OR circuit by the static domino type CMOS logic circuit shown in FIG.
FIG. 15 shows an example of an S static circuit, and FIG. 16 shows an example of its layout. According to this layout, the width is 7 pitches and the height is 18 pitches, and the cell area is 12
It is 6 square pitch. Static domino type C of FIG.
The 4OR circuit composed of MOS logic circuits is a completely complementary CMO.
Although the number of transistors is two more than that of the S static circuit, the layout areas can be equalized. This is because in the static domino type CMOS logic circuit, higher speed can be achieved by designing the channel width of the P-type field effect transistor to be sufficiently small. It is offset by reducing the size.

FIG. 17 shows a static domino type CMOS.
It is an example of a 4-bit adder using a logic circuit. 14
0 is a P-type logical block, 141 is an N-type logical block, 1
Reference numeral 07 is a P-type electric field transistor for precharging, 137 is an N-type electric field transistor for preventing a through current at the time of precharging, 110 is a precharge signal input terminal, and 139 is an output terminal. The logical meaning of input signal and output signal is
“Neil HE Weste and Kamran Eshraghian: Princip
It is represented as follows as disclosed in "les of CMOS VLSI Design".

The i-th carry Ci is expressed by the following equation.

C _i = G _i + P _i × C _i-1 Here, G _i = A _i × B _i (generated signal) P _i = A _i + B _i (propagation signal).

In the case of 4 bits, the following term is obtained.

C ₁ = G ₁ + P ₁ C ₀ C ₂ = G ₂ + P ₂ G ₁ + P ₂ P ₁ C ₀ C ₃ = G ₃ + P ₃ G ₂ + P ₃ P ₂ G ₁ + P ₃ P ₂ P ₁ C ₀ C ₄ = G ₄ + P ₄ G ₃ + P ₄ P ₃ G ₂ + P ₄ P ₃ P ₂ G ₁ + P ₄ P ₃
Focusing on P ₂ P ₁ C ₀ C ₄ , it can be expressed as the following equation.

C ₄ = G ₄ + P ₄ (G ₃ + P ₃ (G ₂ + P ₂ (G ₁ + P ₁ C ₀ ))) FIG. 17 shows a circuit implementation of this function. This function is a P-type logic block 140, an N-type logic block 14
1, an output inverter 138. 4 of this embodiment
When the bit adder is composed of a completely complementary static CMOS circuit, the first power supply terminal 111 to the internal terminal 109
Up to this, five P-type field effect transistors are connected in series. Therefore, the rising delay time of the internal terminal 109 becomes extremely long. Since the 4-bit adder using the static domino type CMOS logic circuit raises the voltage of the internal terminal 109 in advance by the precharge operation,
Internal terminal 1 as a fully complementary static CMOS circuit
There is no problem that the rise time of 09 is long, and high speed can be obtained.

The basic circuit configuration of the embodiment shown in FIG. 18 is the same as that of the embodiment of FIG. In the embodiment of FIG. 18, N
The nodes 142 to 145 and 109 of the N-type field effect transistor which form the N-type logic block are precharged by the respective P-type field effect transistors to speed up the precharge time and at the same time to affect the circuit performance by the charge redistribution. I'm making it small.

FIG. 19 is a diagram in which the number of transistors in the embodiment shown in FIG. 18 is reduced. In the embodiment of FIG. 18, the P-type logic block is configured by the completely complementary logic, but in the present embodiment, the P-type field effect of the P-type logic block is obtained by using the node 145 and the logic signal of the input signal P4. The number of transistors has been reduced to 33%.

[0027]

In FIG. 1, the potential of the internal terminal 109 is precharged to a high level by the precharge element 107 during the precharge period. When the input signal changes from the low level to the high level during the logic determination period and the N-type logic block 106 makes the series path from the internal terminal 109 to the second power supply terminal 112 conductive, the internal terminal 109 is closed.
Potential changes to low level. On the other hand, when the input signal does not change to the low level during the logic determination period and the series path from the internal terminal 109 to the first power supply terminal 111 is conducted by the P-type logic block 105, the internal terminal 1
The potential of 09 remains high level and does not change. That is,
The signal propagation delay of this circuit occurs only when the N-type logic block 106 becomes conductive. As described above, the gain coefficient β of the N-type field effect transistor is higher than the gain coefficient β of the P-type field effect transistor, that is, the signal propagation delay occurs only when the N-type logic block 106 becomes conductive. This circuit is fast. Further, the P-type logic block has the purpose of compensating for the noise current and does not require a large load driving force. Therefore, the channel width of the P-type field effect transistor forming the P-type logic block is N.
50 compared to the channel width of a field effect transistor
It can be designed to be sufficiently small, such as about 10% or less. In the case of a completely complementary static CMOS circuit aiming at high speed, the channel width of the P-type field effect transistor may be designed to be twice as large as the channel width of the N-type field effect transistor. Even if the channel width of the P-type field effect transistor is designed to be about 50% of the channel width of the N-type field effect transistor, high speed can be obtained. If the design is made to be twice as large as the channel width of the type field effect transistor, high speed cannot be obtained, which is as small as 50% of the input capacitance of the fully complementary static CMOS circuit. Therefore, the fan-out capacitance becomes smaller than that of the fully complementary static CMOS circuit, and higher speed can be obtained. Furthermore, P
Since the channel width of the p-type field effect transistor is small, the diffusion capacitance of the p-type field effect transistor is smaller than that of the fully complementary static CMOS circuit. This also
The high speed operation of the circuit of the present invention is possible.

Another effect of the circuit of the present invention is high noise resistance. The circuit of the present invention includes the P-type logic block 105 including the P-type field effect transistor as described above.
N-type logic block 1 including N-type field effect transistor
06 is connected in series between the first power supply terminal 111 and the second power supply terminal 112, and the P-type logic block 105 and the N-type logic block 106 form a completely complementary static CMOS circuit that operates complementarily. . Therefore, the circuit of the present invention does not perform a dynamic operation like the CMOS domino circuit of the above-mentioned prior art example, but performs a static operation. Therefore, even if α ray noise, charge redistribution, or noise due to the power supply line or the signal line is generated in the circuit of the present invention,
P-type logic block 105 that performs static complementary operation
Since the N-type logic block 106 and the N-type logic block 106 always pull up or pull down the internal terminal 109 to the first or second power supply potential, noise generation can be minimized. Alternatively, even if the output potential is inverted due to noise, it can be returned to the correct potential level.

In order to realize higher speed circuit performance, it is preferable that the channel width of the P-type field effect transistor forming the P-type logic block 105 is smaller. On the other hand, in order to improve the noise resistance, it is necessary to set the channel width of the P-type field effect transistor to a certain value or more. Therefore,
The channel width of the P-type field effect transistor needs to be determined from both the high speed and the noise resistance required by the system to which the circuit of the present invention is applied. In a general use-level environment, the channel width of the P-type field effect transistor forming the P-type logic block 105 is about 50% or less of the channel width of the N-type field effect transistor forming the N-type logic block 106. Even if it is designed small, sufficient noise resistance can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a circuit to which the present invention is applied and its operation.

FIG. 2 is a diagram showing an embodiment of a parallel computer system to which the present invention is applied.

FIG. 3 is a diagram showing an embodiment of a central processing unit of the system shown in FIG.

FIG. 4 is a diagram showing an example in which a plurality of circuits to which the present invention is applied are connected in series.

FIG. 5 is a diagram showing another example using a plurality of circuits to which the present invention is applied.

FIG. 6 is a static domino type CMO to which the present invention is applied.
An example of an S logic circuit is shown.

FIG. 7 is a diagram showing a configuration example of a logic block operating in one clock cycle to which the present invention is applied.

FIG. 8 is a diagram showing another configuration example of a logic block that operates in one clock cycle to which the present invention is applied.

FIG. 9 is a diagram showing a conventional CMOS domino circuit.

FIG. 10 is a diagram showing a problem of the circuit shown in FIG.

FIG. 11 is a diagram showing another problem of the conventional CMOS domino circuit.

FIG. 12 is a diagram showing another conventional circuit example.

FIG. 13 is a diagram showing an example of a 4OR circuit to which the present invention is applied.

14 is a diagram showing a layout example of the circuit shown in FIG.

FIG. 15 is a diagram showing an example of a conventional 4OR circuit.

16 is a diagram showing a layout example of the circuit shown in FIG.

FIG. 17 is a diagram showing an embodiment of a 4-bit adder to which the present invention is applied.

FIG. 18 is a diagram showing another example of a 4-bit adder to which the present invention has been applied.

FIG. 19 is a diagram showing another example of a 4-bit adder to which the present invention has been applied.

[Explanation of symbols]

100 to 102 ... NMOS transistor, 103 ... PM
OS transistor, 104 ... N-type logic block, 105
... P-type logic block, 106 ... N-type logic block, 10
7 ... Precharge element, 108 ... Input terminal, 109 ... Internal terminal, 110 ... Precharge signal input terminal, 111 ... First power supply terminal, 112 ... Second power supply terminal, 113, 11
4, 115 ... Static domino type CMOS logic circuit,
116 to 118 ... Input / output terminals, 119 ... Central processing unit, 120 ... Coupling network, 121 ... Hard desk, 122 ... Register file, 123 ... Adder, 12
4 ... Multiplier ... 125 ... Divider, 126 ... Register, 12
7, 128 ... ALU, 129 ... Address adder, 130 ...
Data cache, 131, 132 ... TLB, 133 ... Instruction cache, 134 ... Memory control unit, 135 ...
Command control unit, 136 ... External pin, 137 ... N-type field effect transistor, 138 ... Inverter, 139 ... Output terminal, 140 ... P-type logic block, 141 ... N-type logic block, 142-145 ... Internal node, 147 ... Inverter , 161, 162, 163, 164 ... Static domino type CMOS logic circuit, 165, 166, 167
... Latch circuit, 168, 169 ... Logic block composed of static domino type CMOS logic circuit, 170, 17
1 ... Logic block composed of a completely complementary CMOS circuit, 1
72 ... Logic block composed of static domino type CMOS logic circuit, 173 ... Latch circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiromichi Yamada Inventor Hiromichi Yamada 1-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having a plurality of field effect transistors formed on the same semiconductor substrate, wherein a source and a drain are connected in series or in parallel between a first power supply terminal and a first internal terminal. A first P-type logic block having one or more P-type field effect transistors whose gate is connected to an input terminal, and a source and a drain between the second power supply terminal and the first internal terminal. A first N-type logic block, which is connected in series or in parallel and has one or more N-type field effect transistors whose gates are connected to an input terminal, the first N-type logic block and the first P-type logic block; The N-type logic block constitutes a complementary logic circuit, and has a gate connected to the first internal terminal and a source and a drain connected between the first power supply terminal and the output terminal.
And a first N-type field effect transistor having a gate connected to the first internal terminal and a source and a drain connected between a second power supply terminal and an output terminal, The first P-type field effect transistor and the first N-type field effect transistor form an inverter circuit, and a first precharge element that precharges the first internal terminal to a first power supply potential is a first precharge element. A semiconductor having a static domino type CMOS logic circuit connected between a first power supply terminal and the first internal terminal, and the first precharge element is controlled by a first precharge signal. Integrated circuit device. 2. The source and drain are connected in series between the first N-type logic block and a second power supply terminal, and the gate is controlled by the first precharge signal. Static domino CMO characterized by connecting a second N-type field effect transistor
A semiconductor integrated circuit device having an S logic circuit. 3. The first precharge element according to claim 1, wherein a source and a drain of the first precharge element are connected between a first power supply terminal and the first internal terminal, and a gate of the first precharge element is connected to the first internal terminal. A semiconductor integrated circuit device having a static domino type CMOS logic circuit, which is a second P type field effect transistor controlled by a precharge signal. 4. The channel width of the P-type field effect transistor forming the first P-type logic block is the channel width of the N-type field effect transistor forming the first N-type logic block. A semiconductor integrated circuit device having a static domino CMOS logic circuit characterized by being smaller. 5. A data processor having a plurality of static domino type CMOS logic circuits according to claim 1, which operates in synchronization with a first clock signal, wherein the first precharge signal is used. Is a first clock signal or an inverted signal of the first clock signal. 6. The first precharge element according to claim 1, wherein a source and a drain of the first precharge element are connected between a first power supply terminal and the first internal terminal, and a gate of the first precharge element is connected to the first internal terminal. A semiconductor integrated circuit device having a static domino CMOS logic circuit, which is a third N-type field effect transistor controlled by a precharge signal. 7. The first precharge element according to claim 1, wherein the first precharge element is arranged between a plurality of N-type field effect transistors which form the first N-type logic block in parallel with the first internal terminal. A semiconductor integrated circuit device having a static domino type CMOS logic circuit, characterized in that the semiconductor integrated circuit device is connected to one or more internal terminals of the. 8. The first P-type logic block according to claim 1, wherein the first P-type logic block and the first N-type logic block do not form a complete complementary logic circuit but form the first P-type logic block. A semiconductor integrated circuit device having a static domino CMOS logic circuit, wherein the number of P-type field effect transistors to be used is smaller than the number of N-type field effect transistors forming the first N-type logic block. 9. A static domino type CMOS logic circuit as claimed in claim 1 and a plurality of completely complementary static CMOS logic circuits, the static domino type CMOS logic circuit and a completely complementary static CM.
In a data processing device having a mixture of OS logic circuits, a first latch circuit is connected between an output terminal of the static domino CMOS logic circuit and an input terminal of the completely complementary static CMOS logic circuit, A semiconductor integrated circuit device, wherein the same clock signal is connected to the static domino type CMOS logic circuit and the first latch circuit. 10. A static domino type CMOS logic circuit according to claim 1 and a plurality of completely complementary static CMOS logic circuits, the static domino type CMOS logic circuit and a completely complementary static C circuit.
In a data processing device having a mixture of MOS logic circuits, a second latch circuit is connected between an output terminal of a completely complementary static CMOS logic circuit and an input terminal of the static domino CMOS logic circuit, A semiconductor integrated circuit device, wherein a first clock signal connected to the static domino type CMOS logic circuit and a second clock signal connected to the second latch circuit are mutually inverted signals.