JPH07321227A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device having a structure capable of easily detecting an alignment mark and a method for manufacturing the same. The semiconductor device comprises a memory cell region, a peripheral circuit region and an alignment mark region. The alignment mark A is formed on the N semiconductor substrate 11 by a gate oxide film 21a,
It is composed of three layers of a gate electrode layer 22a and a silicon oxide film 23a. The upper part of the alignment mark A is the BPSG film 24.
It is exposed without being covered by.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment mark in a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor integrated circuit comprises a memory cell region, a peripheral circuit region and an alignment mark region. Below, trench type DRAM (Dynamic Random Access Mem
FIG. 4 shows a semiconductor integrated circuit when a memory cell is a memory cell
Will be described with reference to.

First, the memory cell area will be described. A P well 42 is formed in the N type semiconductor substrate 41. P well 42
A trench is provided in the trench, an N type diffusion layer 45 to be a source region is formed in the P well 42 from the wall surface of the trench, a capacitance insulating film 46 is formed on the inner wall of the trench, and then the inside of the trench is formed into a polysilicon layer 47. To embed. An N-type diffusion layer 48 to be a drain region is formed in the P well 42. In addition, the P well 42 between the N-type diffusion layer 48 and the trench capacitor
A gate oxide film 51, a gate electrode layer 52, and a first insulating film 53 are formed on top.

Next, the peripheral circuit area is shown. The peripheral circuit is a CMOS transistor. P on the N-type semiconductor substrate 41
The well 43 is formed, and the N well 44 is formed in the P well 43. An N-type diffusion layer 49 to be the source / drain region of the NMOS is formed in the P well 43. Also, P
A P-type diffusion layer 50 to be a source / drain region of the MOS is formed in the N well 44. A gate oxide film 51, a gate electrode layer 52, and a first insulating film 53 are formed on each of the NMOS and the PMOS.

In the alignment mark region, a gate oxide film 51a and a gate electrode layer 52a are formed on the N-type semiconductor substrate 41.
And an alignment mark A composed of the first insulating film 53a.
Is formed. This alignment mark A is a DRAM
And at the same time as the gate electrodes provided in the CMOS.

After the memory cell, the peripheral circuit and the alignment mark A are formed as described above, the second insulating film 54 is formed on the entire surface.
And reflow. Next, a contact hole is provided on the N-type diffusion layer 48. At that time, the contact hole is formed through the following steps. After applying a resist on the second insulating film 54, lithography is performed using the alignment mark A, the resist pattern is patterned, and the resist pattern is used as a mask to form the second insulating film 54. Is etched to form the contact hole.

However, as shown in the figure, the alignment mark A is covered with the second insulating film 54, which deteriorates the mask alignment accuracy in lithography. When the misalignment occurs, the contact hole is not formed on the N-type diffusion layer 48 and the gate electrode portion is also exposed. Therefore, in order to prevent misalignment, it is necessary to form the N-type diffusion layer 48 in a size including an alignment margin. However, increasing the size of the N-type diffusion layer 48 increases the size of the entire memory cell region, which increases the chip size, which is a problem.

[0008]

As described above, the DRA
In the semiconductor integrated circuit having M, the alignment mark used for forming the contact hole on the drain diffusion layer of the DRAM is covered with the insulating film, which deteriorates the mask alignment accuracy. Therefore, it is necessary to increase the area of the drain diffusion layer. But D
A semiconductor integrated circuit such as a RAM is required to be highly integrated, and it is a problem to form the drain diffusion layer large.

Therefore, it is an object of the present invention to provide a semiconductor device having a structure in which an alignment mark used for forming a contact hole on a drain diffusion layer of a DRAM is exposed, and a manufacturing method thereof. To do.

[0010]

A semiconductor device according to the present invention comprises an N-type semiconductor substrate, a P well provided in the substrate, a trench provided in the P well, and a trench wall surface extending from the trench wall surface to the P well. A first N-type diffusion layer serving as a source region is provided, a capacitive insulating film provided on the wall surface of the trench, a polysilicon layer filling the trench, and the first N-type film in the P well. A gate formed between the second N-type diffusion layer, which is a drain region formed adjacent to the type diffusion layer, and the first N-type diffusion layer and the second N-type diffusion layer. An oxide film, a gate electrode layer, and a first insulating film, and an alignment provided on the semiconductor substrate and provided at the same time as the gate oxide film, the gate electrode layer, and the first insulating film. Marks are provided on the main surface of the semiconductor substrate. It consists of a second insulating film, at least the alignment mark - click without being covered with the second insulating film, its surface is exposed.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate insulating film on a semiconductor substrate, forming a conductive film on the gate insulating film, and forming the conductive film. At least a gate electrode layer and an alignment mark are formed by simultaneously patterning the step of forming a first insulating film on the film and the first insulating film, the conductive film, and the gate insulating film. Selectively forming a second insulating film having a faster etching rate than the first insulating film on the entire surface of the semiconductor substrate; polishing the second insulating film; Forming an upper portion of the alignment mark higher than the second insulating film.

[0012]

According to the semiconductor device, the upper portion of the alignment mark is exposed, which facilitates detection of the alignment mark during lithography and improves mask alignment accuracy.

Further, according to the above manufacturing method, the alignment mark is exposed due to the difference in etching rate between the first insulating film and the second insulating film which are the uppermost layer of the alignment mark. . Compared with the usual process, only a polishing process is added and no complicated technique is required. Further, by polishing, not only the alignment mark is exposed, but also the surface can be made flat.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. According to FIG. 1A, the semiconductor device according to the present invention includes a memory cell region in which a DRAM is formed,
It is composed of a peripheral circuit region in which CMOS and the like are formed and an alignment mark region.

The memory cell region is formed as a source region by forming a P well 12 provided in the N type semiconductor substrate 11, a trench formed in the P well 12, and the P well 12 from the wall surface of the trench. N-type diffusion layer 15, capacitance insulating film 16 formed on the wall surface of the trench, polysilicon layer 17 filling the trench, N-type diffusion layer 18 serving as a drain region, N-type diffusion layer 15 and N-type diffusion layer 15. Diffusion layer 18
And a gate oxide film 21, a gate electrode layer 22, and a silicon oxide film 23 which are sequentially provided on the P well 12.

The peripheral circuit region includes a P well 13 provided in the N type semiconductor substrate 11 and an N well formed in the P well 13.
Well 14 and N-type diffusion layer 1 provided in P well 13
9, a P-type diffusion layer 20 provided in the N well 14,
It is composed of a gate oxide film 21, a gate electrode layer 22 and a silicon oxide film 23 provided on each of the MOS and the NMOS. The alignment mark region is provided with a gate oxide film 21a and a gate oxide film 21a, which are sequentially provided on the N-type semiconductor substrate 11.
The alignment mark A is composed of three layers, namely, a gate electrode layer 22a and a silicon oxide film 23a. Furthermore, BP on the main surface
The SG film 24 is formed. At that time, the silicon oxide film 23,
23a is exposed without being covered by the BPSG film 24.

As described above, in the semiconductor device according to the present invention, the alignment mark A is not covered with the BPSG film 24, and the upper portion of the alignment mark A is exposed. This makes it easier to detect the alignment mark A during lithography and improve the mask alignment accuracy.

After forming the BPSG film 24, a resist (not shown) is applied on the entire surface, and a resist pattern is formed by using a lithography technique or the like. Using the resist pattern as a mask, the BPSG film 24 is etched to form a contact hole 2 on the N-type diffusion layer 18 as shown in FIG.
5 is formed. At the time of this lithography, the alignment mark A is used, and the exposure can be performed with high accuracy.
Therefore, it is possible to design the N-type diffusion layer 18 to have a minimum size without considering misalignment.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. However, FIG. 2 simply shows the alignment mark A and the gate electrode of the DRAM shown in FIG. 1, and the diffusion layer and the like are omitted.

According to FIG. 1A, the N-type semiconductor substrate 11
A gate oxide film 21, a gate electrode layer 22 and a silicon oxide film 23 are sequentially formed on it. The three layers are simultaneously etched to form the gate electrode portion, the gate oxide film 21a, and the gate.
An alignment mark A made of a silicon oxide film 23a and an electrode layer 22a is simultaneously formed. Next, B on the entire surface
A PSG film 24 is deposited and reflowed in a high temperature furnace ((b) of the same figure). After that, the BPSG film 24 is flattened by polishing or the like, and the silicon oxide films 23 and 23a are exposed (FIG. 7C). Since the etching rate of the BPSG film is faster than that of the silicon oxide film, the silicon oxide film 2
3,23a can be exposed.

In this way, the alignment mark A is
It is formed at the same time as the contact electrode and is aligned by polishing.
Expose the upper part of KU A. For example, the alignment mark A is higher than the BPSG film 24 by about 200 angstroms.

Next, another semiconductor device according to the present invention is shown in FIG.
Will be explained. However, only different points of the semiconductor device shown in FIG. 1 will be described. As shown in FIG. 6A, the alignment mark A is formed on the insulating film 26 provided on the N-type semiconductor substrate 11. Thereby, the alignment mark A of this embodiment can make the exposed portion higher than that of the previous embodiment. Incidentally, the insulating film 26 may be a conductive film.

Therefore, it is possible to detect more clearly than the alignment mark A during lithography. Of course, it serves as an alignment mark in lithography necessary for forming a contact hole on the N-type diffusion layer 18,
It can be used as an alignment mark in lithography required for forming the wiring layer 27 thereafter.

The BPSG film 24 is not limited to this, and a PSG film may be used. Further, although the present invention is a case where a trench type DRAM is formed, a stack type DRAM
It goes without saying that the same can be done even if.

[0025]

According to the present invention, it is possible to improve the mask alignment accuracy of lithography by making it easier to detect the alignment mark. Therefore, an extra area for preventing misalignment is not required, and miniaturization can be achieved.

[Brief description of drawings]

1A is a sectional view schematically showing a semiconductor device according to the present invention, and FIG. 1B is a view in which a contact hole is provided.

FIG. 2 is sectional views (a) to (c) schematically showing a method for manufacturing an alignment mark according to the present invention.

3A is a cross-sectional view schematically showing another semiconductor device according to the present invention, and FIG. 3B is a view in which a contact hole and a wiring layer are formed.

FIG. 4 is a sectional view schematically showing a conventional semiconductor device.

[Explanation of symbols]

11 ... N type semiconductor substrate, 12 ... P well, 13 ... P well 14 ... N well, 15 ... N type diffusion layer, 16 ... Capacitance insulating film 17 ... Polysilicon layer, 18 ... N type diffusion layer, 19 ... N type Diffusion layer 20 ... P-type diffusion layer, 21 ... Gate oxide film, 22 ... Gate electrode layer 23 ... Silicon oxide film, 24 ... BPSG film, 25 ... Contact hole 26 ... Insulating film, A ... Alignment mark

Claims (5)

[Claims] 1. A semiconductor substrate of one conductivity type, a semiconductor region of opposite conductivity type provided in the semiconductor substrate, a trench provided in the semiconductor region, and a trench provided in the semiconductor region from the wall surface of the trench. A conductive type first diffusion layer,
A capacitive insulating film provided on the wall surface of the trench, a polysilicon layer filling the trench, and a second diffusion layer of one conductivity type formed adjacent to the first diffusion layer in the semiconductor region. A gate oxide film, a gate electrode layer, and a first insulating film formed between the first diffusion layer and the second diffusion layer, and the gate oxide film, the gate electrode layer, and the first insulating film formed on the semiconductor substrate. A semiconductor device comprising an alignment mark provided at the same time as a gate oxide film, the gate electrode layer and the first insulating film, and a second insulating film provided on the main surface of the semiconductor substrate. A semiconductor device, wherein at least the alignment mark is exposed without being covered with the second insulating film. 2. The semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film, and the second insulating film is a BPSG film or a PSG film. 3. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a conductive film on the gate insulating film, and a step of forming a first insulating film on the conductive film. And the process of
A step of simultaneously patterning the first insulating film, the conductive film, and the gate insulating film to selectively form at least a gate electrode layer and an alignment mark, and the entire surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of depositing a second insulating film; and a step of planarizing the second insulating film to expose at least the alignment mark. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the second insulating film is polished to form an upper portion of the alignment mark higher than the second insulating film. . 5. The method of manufacturing a semiconductor device according to claim 3, wherein the second insulating film has a faster etching rate than the first insulating film.