JPH0736787A - Flash memory device - Google Patents

Abstract

(57) [Summary] [Construction] The control signal generation circuit 104 collectively issues a write command to the plurality of flash memories 105 and 106 in response to a write command from the CPU 101. The CPU 101 diagnoses, for each of the flash memories, whether or not the data has been correctly written after the writing is executed. The information holding circuit 108 holds the diagnosis result. When the writing cannot be performed correctly, the control signal generation circuit 104 issues another writing instruction in response to the writing instruction from the CPU 101 again. The write prohibition circuit 113 invalidates the write command again for the flash memory that has been successfully written based on the diagnosis result held in the information holding circuit 108. [Effect] Since it is possible to prevent overwriting to a flash memory that has been successfully written, it is possible to reduce power consumption and prevent shortening of life.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory storage device which is a storage device using a flash memory, and more particularly to reducing the power consumed by the flash memory in a write process.

[0002]

2. Description of the Related Art In recent years, a flash memory has attracted attention as a rewritable nonvolatile memory. Since the flash memory can hold data without a backup battery, it is expected as a storage medium replacing conventional hard disks and floppy disks. Here, the operation of the flash memory will be described based on the description of the 1991 edition Hitachi IC Memory Data Book 1 from page 868 to page 881. Unlike DRAM, SRAM, and the like, in order to read, write, and erase the flash memory, it is necessary to send a control command corresponding to each operation to the flash memory in advance. Table 1 shows an example of the flash memory control command.

[0003]

[Table 1]

For example, in a read operation, the flash memory sends command data "00H" via a data terminal (in this example, the same data terminal is used for input and output).
(“H” indicates that the data is in hexadecimal notation), and then it starts when both the chip enable signal and the output enable signal become active, and when a predetermined time has elapsed after the start, The contents of the address indicated by the terminal are output to the data terminal. To get the command to flash memory,
At the same time as inputting the code corresponding to the command shown in Table 1 to the data terminal, both the chip enable signal and the output enable signal are activated for the read command, and the chip enable signal for the other commands in Table 1, Both write enable signals may be activated. Note that commands other than the read command among the commands in Table 1 are commands for writing, and for example, the reset command is for canceling writing during writing.

The write operation is started when the command data "40H" is received and then the chip enable signal and the write enable signal are both activated, and the flash memory stores the data input to the data terminal at the address indicated by the address terminal. . However, flash memory cannot be overwritten. That is, the write operation can be performed only on the address after the erase operation is performed. Therefore, when rewriting the data already stored in the flash memory, it is necessary to perform the erasing operation before the writing operation.

By the way, the flash memory has a feature that data cannot always be written by one writing operation. This is due to the memory cell structure of the flash memory. Therefore, in order to accurately write data in the flash memory, it is necessary to perform the write operation according to the procedure shown in FIG.

The write operation procedure of FIG. 2 will be described below. FIG. 2 shows a case where writing is performed in an area where writing has not been performed even once. When writing to an area where writing has already been performed, an erasing step is required between step 201 and step 202 in FIG.

First, the program power supply terminal Vpp is boosted to the program voltage 12 [V] (process 201). Then, the write command "40H" is sent to the data terminal (process 20).
2) When the chip enable signal and the write enable signal are activated, the control circuit inside the flash memory shifts to the write cycle. The flash memory which has shifted to the write cycle becomes writable, and when the chip enable signal and the write enable signal are activated next, the data on the data terminal is fetched into the address indicated by the address terminal (process 203). After the lapse of the required writing time specified for the flash memory to be used, the verify command "C0H" is transferred to confirm the memory contents (process 204). After that, the memory contents are read out and compared with the write data transferred in the process 203 (processes 205 and 206). If they match, the voltage supplied to the program power supply terminal Vpp is reduced to 5 [V] (process 207). The write operation ends. If they do not match, the process returns to the process of transferring the write command (process 202) again, and the processes 202 to 206 are repeated until the writing is successful.

The data width of the microcomputer has been expanded from 8 bits to 16 bits and 32 bits in accordance with the high performance of the microcomputer. On the other hand, a general flash memory has a data width of 8 bits. Therefore, in order to configure a memory system corresponding to the data width of a microcomputer using a flash memory, if the width is 16 bits, two , It is necessary to use a plurality of flash memories, such as four if the width is 32 bits. This is the same as the case where the memory device is configured by using the 8-bit width DRAM. And
As in the case of the DRAM, when a memory system having a 16-bit data width is configured by using two flash memories, the circuit shown in FIG. 3 is obtained.

The memory system of FIG. 3 will be described below.
In the figure, the operation procedure shown in FIG. 2 is stored in the ROM 103 as a program. A flash memory 105 stores the lower 8 bits of the 16-bit data bus D0 to D15. D0 to D7 are provided to eight data terminals.
Are connected. A flash memory 106 stores high-order 8-bit data, and data terminals D8 to D15.
Are connected. The chip enable signal, the write enable signal, and the output enable signal of the flash memories 105 and 106 are connected in common and simultaneously activated.

The address decoder 102 decodes the address signal sent from the CPU 101 to the address bus and sends the decoded signal to the control signal generation circuit 104. Control signal generation circuit 1
Reference numeral 04 denotes the flash memory 105, 106 based on the decode signal sent from the address decoder 102 and, if necessary, the control signal sent from the CPU 101.
Control signal (CE: Chip enable signal, OE: Output enable signal, WE: Write enable signal), Vp
A latch enable signal for the p voltage control register 108 is generated. Specifically, when the latch enable signal of the Vpp voltage control register 108 is generated, when the CPU 101 accesses the Vpp voltage control register 108, the address decoder 102 has accessed the Vpp voltage control register 108 from the address. Is transmitted to the control signal generation circuit 104. When generating CE, OE and WE, the CPU 101 causes the flash memory 105, 10
When 6 is accessed, a decode signal indicating that the address decoder 102 has accessed the flash memories 105 and 106 is sent from the address to the control signal generation circuit 104, and the CPU 101 controls the memory read or the memory write. The signal is sent to the control signal generation circuit 104. From this, the control signals (CE, OE, WE) of the flash memories 105 and 106 and the latch enable signal of the Vpp voltage control register 108 are generated.

Reference numeral 107 denotes a power supply switching circuit using a relay, which switches the program voltage supplied to the program power supply terminal Vpp of the flash memory. The power switching circuit 107 is controlled by setting the Vpp voltage control register 108. This is shown in Table 2.

[0013]

[Table 2]

As can be seen from the table, the Vpp voltage control register is the I / O address of the CPU 101 (for example, C004H address).
Assigned to.

In the configuration of FIG. 3, if the write operation is performed according to the operation procedure shown in FIG. 2, the flash memory system can be accessed with a 16-bit data width.

[0016]

As described in the above-mentioned prior art, the flash memory does not always write data in one write operation. If the write operation fails, the write operation is performed again in the flash memory. Need to let. 16-bit data can be written by performing a write operation in the operation procedure shown in FIG. 2 with respect to the memory system having the configuration shown in FIG. However, if one of the upper 8 bits or the lower 8 bits of the flash memory is unsuccessful in writing, the rewriting operation is performed on the successfully written flash memory in the operation procedure shown in FIG. I will end up. At this time, the flash memory that has been successfully written will perform excessive writing (hereinafter referred to as overwriting), resulting in wasted power consumption. The amount of increase in power consumption when boosting to 12 V and waiting before the write command is actually executed or after the command is executed is different depending on the chip.
It may increase by about 00 mW. Further, when the write command is actually performed, it may increase by about 250 mW.

Further, considering that there is a limit to the number of times of rewriting, which is a drawback of the flash memory, the life is shortened by wasteful rewriting of overwriting. The memory system of FIG. 3 does not consider such waste of power and shortening of life.

According to the present invention, in a write operation for a memory system using a plurality of flash memories, by preventing overwriting to the flash memory, the power consumed by the flash memory is reduced and the life of the flash memory is prevented from being shortened. The purpose is to provide a device.

[0019]

In order to achieve the above object, according to the present invention, in response to a plurality of flash memories and external write commands, write commands are collectively written to the plurality of flash memories. In the flash memory device having a control means for issuing a write command again, after writing the data by the write command from the control means to each of the flash memories. ,
For the diagnostic means for diagnosing whether or not the data has been correctly written, and for the flash memory judged to have been able to be written by the diagnostic means, the write command is issued when the write command is issued again from the control means. It has a write invalidating means for invalidating, and rewrites only the flash memory for which writing has failed.

[0020]

The diagnosing means diagnoses whether or not the data has been correctly written in each flash memory after the writing is executed. Then, when the writing has failed, it is diagnosed which flash memory has failed the writing. The write invalidating means invalidates the write processing based on the above result when the rewrite processing is unnecessary. As a result, only the flash memory for which writing has failed will be written.

As described above, the rewriting process is performed only on the flash memory that has failed to be written and needs to be rewritten. Therefore, it is possible to prevent overwriting to the flash memory that has been successfully written, so that it is possible to reduce the power consumption of the flash memory and prevent the life from being shortened.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a 16-bit data width flash memory system according to the present invention, in which an information holding circuit 112 and a write inhibit circuit 113 are added to the memory system shown in FIG. In addition, FIG.
ROM 103, which is a diagnostic means for changing the write operation of
It is stored as a program in.

In this embodiment, the two I / O registers shown in Table 2 are used.

The Vpp voltage control register corresponds to 108 in FIG. 1 and is a register used by the CPU 101 to control the program power supply of the flash memory. The rewrite information register corresponds to the information holding circuit 112 of FIG.
U101 is a register for writing the result of the write success / failure diagnosis to the flash memory. The CPU 101 stores the diagnosis result in the register as data shown in Table 2. still,
The I / O addresses shown in Table 2 need to be changed depending on the computer system used.

The configuration of the memory system shown in FIG. 1 will be described below. This flash memory system is C
PU 101, coder 102 by address, control signal generation circuit (control means) 104, information holding circuit 112,
ROM 103, Vpp voltage control register 108, power supply switching circuit 107, write inhibit circuit 113,
It has flash memories 105 and 106.

The address decoder 102 decodes the address signal of the CPU 101 and sends the decoded signal to the control signal generation circuit 104. The control signal generation circuit 104 uses the decode signal sent from the address decoder 102 and the control signal sent from the CPU 101 to control the flash memory 1
05 and 106 control signals (CE: chip enable signal,
OE: output enable signal, WE: write enable signal) and a control signal (latch enable signal) for the information holding circuit 112. When the latch enable signal of the information holding circuit 112 is generated, when the CPU 101 accesses the information holding circuit 112, a decode signal indicating that the address holding circuit 112 has been accessed from the address decoder 102 is a control signal. It is sent to the generation circuit 104.

Information holding circuit (rewrite information register)
Reference numeral 112 includes data latch circuits 114 and 115. When the CPU 101 accesses the rewrite information register 112 (that is, accesses the I / O address “6H” shown in Table 2), the control signal generation circuit 10
4, the latch signals of the data latch circuits 114 and 115 become active, and the information holding circuit 112 fetches the write success / failure diagnostic information sent to the data bus. Also,
The write inhibit circuit 113 includes gate circuits 116 and 117.
The write enable signal (WE) is selectively cut off based on the electric signal sent from the information holding circuit 112. For example, the Q output of the data latch circuit 114 is "
When L ", the gate circuit 116 cuts off the write enable signal (WE) generated by the control signal generation circuit 104. As a result, the write enable signal (WE) is transmitted only to the WE2 signal, and only the flash memory 106 performs the write operation. It will be possible.

The Vpp voltage control register 108 is provided in the CPU 101.
When the Vpp voltage control register 108 is accessed by the control signal generation circuit 104,
The latch signal of 8 becomes active, and the control data on the data bus is taken in. Q of the Vpp voltage control register 108
When the output is "L", the switch 111 is as shown in FIG.
It is connected to the 5 [V] side. When the Q output of the Vpp voltage control register 108 becomes "H", the output of the inverter 109 connected to the Q output becomes "L". At this time, a current flows through the coil 110 of the power supply switching circuit 107 and the switch 11
1 switches to the 12 [V] side, and the program voltage 12 [V] is supplied to the Vpp terminal of the flash memory.

Next, the entire operation will be described with reference to FIG. Two flash memories 10 for the first write
5, 106 is executed. The diagnostic means stored as a program in the ROM 103 diagnoses whether or not the data is read out after the writing is executed and the data is correctly written in each flash memory. If the writing fails, whether the flash memory 106 assigned to the upper 8 bits has failed to write, the flash memory 105 assigned to the lower 8 bits has failed to write, or both have failed. To diagnose. The diagnosis result is stored in the information holding circuit 112 as an electric signal of "L" when each flash memory succeeds and "H" when it fails. The write invalidation circuit 113 controls the rewriting process based on the electric signal sent from the information holding circuit 112. For example, if the flash memory 106 assigned to the upper 8 bits fails to write, the write enable signal is sent only to the flash memory and the write enable signal to the flash memory 105 assigned to the lower 8 bits is sent. Cut off. As a result, only the flash memory 106 assigned to the upper 8 bits for which the first writing has failed will receive the re-transferred write command and write data.

As described above, in a memory system using a plurality of flash memories, a diagnostic means for diagnosing whether or not writing has succeeded, an information holding circuit for holding the diagnosis result, and a rewriting for the successfully written flash memory. If a write invalidation circuit that prohibits writing is provided, rewriting processing is performed only for the flash memory that has failed writing and needs to be rewritten. Therefore, it is possible to prevent overwriting to the flash memory that has been successfully written, and it is possible to reduce the power consumed by the flash memory.

The diagnostic means shown in FIG. 4 will be described below.
The diagnostic means shown in FIG. 4 is the same as the writing operation procedure shown in FIG.
5, 410, 411, 412 are added.

First, the CPU 101 executes the processing 401 to store the data "03H" as the initial value in the rewrite information register.
To set. This allows the write enable signal in FIG. 1 to pass through the gate circuits 116 and 117. Next, the data "01H" is set in the Vpp voltage control register to apply the program voltage 12 [V] to the Vpp terminal of the flash memory (process 402). Then, the write command "4040H" is input to the data terminal (process 40).
3). Each flash memory that has received the command shifts to the write cycle and stores the write data sent in step 404 at the address indicated by the address terminal.
The data "03H" is set in the rewrite information register to transfer the verify command (process 405), and the verify command "C0C0H" is set after the predetermined write time elapses.
Is input to the data terminal (process 406). Then, the data stored in the address written in the process 404 is read (process 407). It is confirmed whether the read data and the data transferred to the flash memory in process 404 match (process 408). If they match, the data "00H" is set in the Vpp voltage control register to set the Vpp terminal voltage to 5 The voltage is lowered to [V] (process 409),
Data "00H" is written as the end value in the rewrite information register (process 410), and the write operation to the flash memory ends. If they do not match, the process 40
Based on the memory data read in step 7, which of the flash memories 105 and 106 has failed to write is diagnosed (process 411), and the diagnostic result is rewritten as the setting data shown in the rewrite information register section of Table 2. Write to the information register (process 412). After that, the writing process is repeated from the process 403 until the writing is successful.

A second embodiment of the present invention is shown in FIG. The memory system shown in FIG. 5 is obtained by changing the configuration of the write inhibit circuit 113 in the memory system shown in FIG.

The write inhibit circuit 501 will be described below. The write inhibit circuit 501 is composed of power supply switching circuits 502 and 503 using relays. The power supply switching circuits 502 and 503 are controlled by the output signal of the information holding circuit 112. For example, when the Q output of the data latch circuit 114 becomes “H”, the switch of the power supply switching circuit 502 switches to the 12 [V] side, and the flash memory 105. V
Program voltage 12 [V] is supplied to the pp pin. As a result, only the flash memory 105 can be written.

Next, the diagnostic means of the memory system shown in FIG. 5 will be described with reference to FIG. Introduction CPU10
In step 1, the data "03H" is set as the initial value in the rewrite information register by the process 601. As a result, the Q outputs of the data latch circuits 114 and 115 become "H", and the program voltage 12 [V] is supplied to the Vpp terminals of the flash memories 105 and 106. Thereafter, the process 40 shown in FIG.
The processing similar to the processing 408 from 3 is performed. When the write command "4040H" is input to the data terminal (process 60
2), the flash memory shifts to the write cycle,
The write data sent in step 603 is stored in the address indicated by the address terminal. Data "03H" is set in the rewrite information register to transfer the verify command (process 604), and the verify command "C0C0H" is input to the data terminal after a predetermined write time has elapsed (process 605). Then, the data stored in the address written in the process 603 is read (process 606). It is confirmed whether the read data and the data transferred to the flash memory in the process 603 match (process 607), and if they match, the data "00H" is written as the end value in the rewrite information register (process 6).
08), the write operation to the flash memory ends. By the process 608, the Vpp terminal voltage of the flash memory is lowered to 5 [V]. On the other hand, if they do not match, the process 60
Based on the memory data read in 6, it is diagnosed which one of the flash memories 105 and 106 has failed to write (process 609), and the diagnosis result is rewritten as the setting data shown in the rewrite information register section of Table 2. Write to the information register (process 610). By the process 610, the program voltage 12 [V] is supplied only to the flash memory that needs the rewriting process. After that, the writing process is repeated from the process 602 until the writing is successful. If the write inhibit circuit is configured as shown in FIG. 5, the program voltage supplied to the program power supply of the flash memory can be controlled by setting the write success / failure diagnosis result in the rewrite information register. Therefore, it is not necessary to access the Vpp voltage control register to control the program voltage of the flash memory.
The write operation procedure is simplified. Although the write operation of the flash memory is prohibited by controlling the program voltage in this embodiment, the chip power supply terminal (Vcc)
The write operation can be prohibited even by controlling the voltage supplied to 0V to 0V.

A third embodiment of the present invention is shown in FIG. This achieves the object of the present invention only by adding software without adding hardware to the conventional example shown in FIG. The diagnostic means shown in FIG. 7 is shown in FIG.
This is effective when performing a write operation on the memory system shown in. The circuit configuration of the memory system shown in FIG. 3 cannot prohibit the write operation of the flash memory that has been successfully written. Therefore, by performing the write operation according to the write operation procedure as shown in FIG. 7, the write operation to the successfully written flash memory is prohibited.

Hereinafter, FIG. 7 will be described. First, CPU1
01 supplies data "01H" to the Vpp control register in order to supply the program voltage to the Vpp terminal of the flash memory (process 701). In process 702, "4040H" is transferred as a write command in the first write process. Flash memory 105 that received the command,
106 shifts to the write cycle and stores the write data sent in the process 703 at the address indicated by the address terminal. The verify command "C0C0H" is input to the data terminal after a predetermined write time has elapsed (process 70).
4). Then, the data stored in the address written in the process 703 is read (process 70).
5) It is confirmed whether the read data and the data transferred to the flash memory in process 703 match (process 706). When they match, data "00" is written in the Vpp control register.
H "is set (process 707), and the write operation to the flash memory ends. If they do not match, process 7 is performed.
Based on the memory data read in 05, which of the flash memories 105 and 106 has failed in writing is diagnosed (process 708), and the write command and the write data are converted based on the diagnosis result (process 709). After the processing 709 is executed, the writing processing is performed again from the processing 702 until the writing is successful.

Conversion of the write command and the write data is performed as follows. For example, when the flash memory 106 assigned to the upper 8 bits fails to write, the command data is set to "4011H". However, the value "11H" of the lower 8 bits may be another value as long as it is a value other than the command data (see Table 1) specified in the flash memory to be used. Further, the conversion of the write data is performed in the same manner as the conversion of the write command, and the lower 8 bits of the write data are converted to "11H". When the write command is converted to "4011H" and the lower 8 bits of the write data is converted to "11H" by the process 709, the process 70
2, the flash memory 105 stores the command data “1
Since 1H "is received, the flash memory 105 does not shift to the write cycle even after the processing 702 is executed.
Also in the next process 703, the data received by the flash memory 105 is "11H", so the flash memory 105
Does no action.

If the write operation is performed according to the operation procedure shown in FIG. 7, it is not necessary to provide a circuit for prohibiting the write in the memory system shown in FIG. 3, so that the substrate area required for mounting the memory system is saved. can do.

A fourth embodiment of the present invention is shown in FIG. The write inhibit circuit of the memory system shown in FIG.
This is a combination of the write inhibit circuits of the memory system shown in FIGS. 1 and 5.

The write inhibit circuit 801 will be described below. The write inhibit circuit 801 is the power supply switching circuit 8
02, 803 and gate circuits 804, 805. Each power supply switching circuit and each gate circuit is controlled by the output of the information holding circuit 112. For example, when the Q output of the data latch circuit 114 becomes “H”, the switch of the power supply switching circuit 802 switches to the 12 [V] side, and the program voltage 12 [V] is supplied to the Vpp terminal of the flash memory 105. Further, the gate circuit 804 is the control signal generation circuit 1
The write enable signal (WE) generated by 04 is transmitted to the WE1 signal.

Each power supply switching circuit and each gate circuit shown in FIG. 8 are controlled by the output of the information holding circuit 112. Therefore, if predetermined data is set in the rewriting information register, switching control of the program voltage and selective cutoff of the write enable signal (WE) can be performed at the same time. Therefore,
The diagnostic means of the memory system shown in FIG. 8 may be exactly the same as the diagnostic means shown in FIG.

If the write inhibit circuit is configured as shown in FIG. 8, it is possible to more reliably inhibit the write to the flash memory that has been successfully written.

FIG. 9 is a block diagram showing the fifth embodiment of the present invention. In this embodiment, counting means 901 is added to the first embodiment (FIG. 1). The counting means 901 monitors the WE1 signal and the WE2 signal during the rewriting process. Specifically, during the rewriting process, WE1
The number of times that the signal and the WE2 signal have become active is counted respectively, and when either of them exceeds a predetermined number, the NMI signal 9
02 is output to the CPU 101. The specified number of times depends on the chip, but at the current technical level, 10,000 to 10
The life of the chip is said to be 10,000 times. In this way, when the flash memory 105 or the flash memory 106 becomes unwritable, the memory access process is stopped and the RO
The NMI routine stored in M103 can be activated.

[0045]

According to the present invention, in a write operation for a memory system using a plurality of flash memories, it is possible to prevent overwriting of a flash memory that has been successfully written, so that the power consumed by the flash memory is reduced. In addition, it is possible to prevent shortening of life.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart of a write operation on a flash memory.

FIG. 3 is a block diagram showing a 16-bit data width flash memory system.

FIG. 4 is a flowchart of a write operation for the flash memory system shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a flowchart of a write operation for the flash memory system shown in FIG.

FIG. 7 is a flowchart showing a third embodiment of the present invention.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a fifth embodiment of the present invention.

[Explanation of symbols]

101 ... CPU, 103 ... ROM, 105 ... Flash memory, 106 ... Flash memory, 112 ... Information holding circuit, 113 ... Write prohibition circuit, 901 ... Counting means.

Claims (9)

[Claims] 1. In response to a plurality of flash memories and a write command from the outside, a write command is collectively issued to the plurality of flash memories, and when the writing cannot be performed correctly, another write command is issued again. In a flash memory device having a control means for issuing a write command, in each of the flash memories, a diagnostic means for diagnosing whether or not data has been correctly written after execution of writing by a write command of data from the control means, The flash memory, which has been determined to be writable by the diagnostic means, has a write invalidating means for invalidating the write command when the write command is issued again from the control means. A feature characterized in that the rewriting process is performed only for the failed flash memory. Sshumemori apparatus. 2. The flash memory device according to claim 1, wherein a data processing unit is a data width larger than a data width of each of the plurality of flash memories, and the control means sets the data processing unit. A flash memory device, which issues a write command to a plurality of flash memories that constitute the device collectively. 3. The flash memory device according to claim 1 or 2, further comprising: information holding means for holding a diagnosis result of said diagnosing means, wherein said write invalidating means is responsive to a signal output by said information holding means. A flash memory device characterized by invalidating the above-mentioned write command for a flash memory that has been successfully written. 4. In response to a plurality of flash memories and a write command from the outside, a write command is issued to the plurality of flash memories at once, and if the writing cannot be performed correctly, another write command is issued again. In a flash memory device having a control unit that issues a write command, a diagnostic result indicating whether or not the data has been correctly written is received for each of the flash memories after receiving a data write command from the control unit and executing writing. For the information holding means that receives the diagnosis result from the outside and the flash memory that is judged to have been written based on the diagnosis result, the write operation is performed when the write instruction is issued again from the control means. A flash memory having write invalidation means for invalidating an instruction and writing has failed Flash memory device which is characterized in that only the re-writing process for. 5. The flash memory device according to claim 1, 2, 3 or 4, wherein the write invalidating means has a circuit for invalidating a write enable signal for each of the flash memories, A flash memory device, wherein a write enable signal is sent only to a flash memory that needs to be rewritten. 6. The flash memory device according to claim 1, 2, 3 or 4, wherein the write disabling means sets a voltage supplied to a program power supply terminal of the flash memory for each flash memory as a standby voltage and a program. A flash memory device having a switching circuit capable of switching to a voltage, and supplying a program voltage only to a program power supply terminal of a flash memory in which writing has failed and rewriting is required. 7. The flash memory device according to claim 1, 2, 3 or 4, wherein the write invalidating means includes a gate circuit for invalidating a write enable signal for each flash memory, and each flash memory, It has a switching circuit that can switch the voltage supplied to the program power supply terminal of the flash memory between the standby voltage and the program voltage, and sends the write enable signal only to the flash memory that has failed to write and needs to be rewritten. With
A flash memory device characterized by supplying a program voltage. 8. A flash memory device having a plurality of flash memories and control means for collectively transferring a write command and write data to the plurality of flash memories in response to an external write command. For each of the flash memories, there is a diagnostic means for diagnosing whether or not the data has been correctly written after execution of the writing by the data write instruction from the control means, and the control means issues a different instruction for each flash memory. The write command and the write data are transferred again to the flash memory that can be issued in a batch and it is judged that the writing could not be performed by the above diagnostic means, and the operation of the flash memory is not triggered for the written flash memory. Write by transferring command Flash memory device which is characterized in that only the rewriting processing for the failed flash memory. 9. The flash memory device according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein the number of times a write command is issued is counted, and the number of times exceeds a predetermined number. A flash memory device, characterized in that a counting means is provided for outputting a signal indicating that the time has been exceeded to the outside.