JPH0758065A - Chamfering method for semiconductor wafer - Google Patents
Chamfering method for semiconductor waferInfo
- Publication number
- JPH0758065A JPH0758065A JP20079493A JP20079493A JPH0758065A JP H0758065 A JPH0758065 A JP H0758065A JP 20079493 A JP20079493 A JP 20079493A JP 20079493 A JP20079493 A JP 20079493A JP H0758065 A JPH0758065 A JP H0758065A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor wafer
- chamfering
- grindstone
- peripheral edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract description 28
- 238000005498 polishing Methods 0.000 claims description 11
- 235000012431 wafers Nutrition 0.000 abstract 10
- 239000004575 stone Substances 0.000 abstract 4
- 238000005299 abrasion Methods 0.000 abstract 1
- 238000003672 processing method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Landscapes
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体ウエハの面取方
法に係り、特に半導体ウエハの周縁を回転する砥石に当
接して面取り加工する半導体ウエハの面取方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for chamfering a semiconductor wafer, and more particularly to a method for chamfering a semiconductor wafer by abutting a peripheral edge of the semiconductor wafer against a rotating grindstone.
【0002】[0002]
【従来の技術】スライシングマシンによって切断された
半導体ウエハは、その表面がラップ加工されると共に、
その周縁も面取加工がなされてクラック防止及び塵埃の
付着並びに発生を防止している。即ち、図3に示すよう
に、ウエハ保持台1に保持された半導体ウエハ2の周縁
を、回転する溝付き砥石3の上傾斜面3Aに押し当て、
半導体ウエハ2の上縁部を研磨したのち、ウエハ保持台
1を図中二点鎖線で示すように所定量下降して半導体ウ
エハ2の下縁部を溝付き砥石3の下傾斜面3Bに押し当
て研磨する。2. Description of the Related Art A semiconductor wafer cut by a slicing machine has its surface lapped and
The peripheral edge is also chamfered to prevent cracks and prevent dust from adhering. That is, as shown in FIG. 3, the peripheral edge of the semiconductor wafer 2 held by the wafer holder 1 is pressed against the upper inclined surface 3A of the rotating grooved grindstone 3,
After polishing the upper edge of the semiconductor wafer 2, the wafer holder 1 is lowered by a predetermined amount as shown by the chain double-dashed line in the figure to push the lower edge of the semiconductor wafer 2 against the lower inclined surface 3B of the grooved grindstone 3. Apply polishing.
【0003】従来の半導体ウエハの面取方法は、溝付き
砥石3の上傾斜面3Aと下傾斜面3Bとに研磨されるX
1、X2寸法(図4参照)を設定することによって行わ
れている。この結果、面取りされた半導体ウエハ2の周
縁には、前記上傾斜面3Aと下傾斜面3Bとによって傾
斜面2A、2Bが形成されると共に、溝付き砥石3の平
坦面3Cの上下に形成された曲面3D、3EによってR
面2C、2Dが形成され、更に、R面3CとR面3Dと
の間に平坦部2Eが形成される。In the conventional method for chamfering a semiconductor wafer, the upper and lower inclined surfaces 3A and 3B of the grindstone 3 with grooves are polished by X.
This is done by setting the 1 and X2 dimensions (see FIG. 4). As a result, at the peripheral edge of the chamfered semiconductor wafer 2, inclined surfaces 2A and 2B are formed by the upper inclined surface 3A and the lower inclined surface 3B, and are formed above and below the flat surface 3C of the grooved grindstone 3. R by curved surface 3D, 3E
The surfaces 2C and 2D are formed, and further, the flat portion 2E is formed between the R surface 3C and the R surface 3D.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、従来の
半導体ウエハの面取方法は、前述したようにX1、X2
寸法を設定して行っているので、半導体ウエハ2の厚さ
tが基本寸法よりも薄い場合、又は溝付き砥石3の曲面
3D、3Eの曲率が基本寸法よりも大きい場合には、半
導体ウエハ2の平坦部2Eが図5に示すように無くなっ
てしまい、本来、平坦部2Eが形成される部分2Fが尖
鋭状になるという欠点がある。However, the conventional chamfering method of the semiconductor wafer is the same as that of X1, X2 as described above.
Since the dimensions are set, if the thickness t of the semiconductor wafer 2 is thinner than the basic dimension, or if the curvatures of the curved surfaces 3D and 3E of the grooved grindstone 3 are larger than the basic dimension, the semiconductor wafer 2 The flat portion 2E is lost as shown in FIG. 5, and the portion 2F where the flat portion 2E is originally formed has a drawback that it is sharp.
【0005】本発明は、このような事情に鑑みてなされ
たもので、半導体ウエハの厚さに影響されることなく半
導体ウエハの面取り形状を同じにすることができる半導
体ウエハの面取方法を提案することを目的とする。The present invention has been made in view of the above circumstances, and proposes a method for chamfering a semiconductor wafer that can make the chamfered shape of the semiconductor wafer the same without being affected by the thickness of the semiconductor wafer. The purpose is to do.
【0006】[0006]
【課題を解決するための手段】本発明の第1発明は、前
記目的を達成する為に、周縁の中央部に平坦面が形成さ
れると共に、該平坦面の上端、及び下端に上曲面、下曲
面を介して上傾斜面、下傾斜面が形成された溝付き砥石
を回転させ、該溝付き砥石にウエハ保持台に保持された
半導体ウエハの周縁を当接して面取り加工する半導体ウ
エハの面取方法に於いて、前記溝付き砥石に形成された
前記平坦面と上曲面との境界部の水平方向延長線上に、
前記ウエハ保持台の上面が同一面上に位置するようにウ
エハ保持台を移動し、予め測定された半導体ウエハの厚
さの1/2と、面取り加工によって半導体ウエハの周縁
の中央部に形成される平坦部の厚さの1/2とを加算し
た寸法分だけ前記ウエハ保持台を下降し、前記ウエハ保
持台を水平移動させて半導体ウエハの上縁部を溝付き砥
石の上傾斜面に当接させて上縁部を研磨し、前記溝付き
砥石の平坦面の幅から前記半導体ウエハの平坦部の厚さ
を減算した寸法分だけ前記ウエハ保持台を下降させて半
導体ウエハの下縁部を溝付き砥石の下傾斜面で研磨する
ことを特徴とする。In order to achieve the above object, the first invention of the present invention is such that a flat surface is formed in the central portion of the peripheral edge, and upper curved surfaces are formed at the upper and lower ends of the flat surface. A surface of a semiconductor wafer to be chamfered by rotating a grooved grindstone having an upper inclined surface and a lower inclined surface formed through a lower curved surface and abutting the peripheral edge of the semiconductor wafer held on a wafer holding table to the grooved grindstone. In the taking method, on the horizontal extension line of the boundary between the flat surface and the upper curved surface formed on the grooved grindstone,
The wafer holder is moved so that the upper surface of the wafer holder is located on the same plane, and is formed in the center of the peripheral edge of the semiconductor wafer by ½ of the thickness of the semiconductor wafer measured in advance and by chamfering. The wafer holding table is lowered by a size obtained by adding 1/2 of the thickness of the flat portion, and the wafer holding table is horizontally moved so that the upper edge of the semiconductor wafer contacts the upper inclined surface of the grooved grindstone. The upper edge of the semiconductor wafer is polished by contacting it, and the lower edge of the semiconductor wafer is lowered by lowering the wafer holder by a dimension obtained by subtracting the thickness of the flat portion of the semiconductor wafer from the width of the flat surface of the grooved grindstone. It is characterized by polishing on the lower inclined surface of a grindstone with a groove.
【0007】本発明の第2発明は、前記目的を達成する
為に、周縁の中央部に平坦面が形成されると共に、該平
坦面の上端、及び下端に上曲面、下曲面を介して上傾斜
面、下傾斜面が形成された溝付き砥石を回転させ、該溝
付き砥石にウエハ保持台に保持された半導体ウエハの周
縁を当接して面取り加工する半導体ウエハの面取方法に
於いて、面取り加工により前記ウエハの周縁の中央部に
形成される平坦部の幅寸法、溝付き砥石の前記上曲面と
下曲面の曲率半径値、及び前記上傾斜面と下傾斜面の傾
斜角度を入力して、ウエハの面取りを行うことを特徴と
する。According to a second aspect of the present invention, in order to achieve the above-mentioned object, a flat surface is formed at the center of the peripheral edge, and an upper curved surface and a lower curved surface are formed on the upper and lower ends of the flat surface. In a chamfering method of a semiconductor wafer, a chamfering process is performed by rotating a grindstone with a groove on which an inclined surface and a lower inclined surface are formed, and abutting the peripheral edge of the semiconductor wafer held on a wafer holding table to the grooved grindstone. Enter the width dimension of the flat part formed in the central part of the peripheral edge of the wafer by chamfering, the radius of curvature of the upper curved surface and the lower curved surface of the grindstone with grooves, and the inclination angle of the upper inclined surface and the lower inclined surface. Then, the wafer is chamfered.
【0008】[0008]
【作用】本発明の第1発明によれば、先ず、溝付き砥石
に形成された平坦面と上曲面との境界部の水平方向延長
線上に、ウエハ保持台の上面を同一面上に位置させる。
次に、予め測定された半導体ウエハの厚さの1/2と、
面取り加工によって半導体ウエハの周縁の中央部に形成
される平坦部の厚さの1/2とを加算した寸法分だけ前
記ウエハ保持台を下降させる。次いで、ウエハ保持台を
水平移動させて半導体ウエハの上縁部を溝付き砥石の上
傾斜面に当接し、上縁部を研磨する。According to the first aspect of the present invention, first, the upper surface of the wafer holder is positioned on the same plane on the horizontal extension line of the boundary between the flat surface and the upper curved surface formed on the grooved grindstone. .
Next, ½ of the thickness of the semiconductor wafer measured in advance,
The wafer holder is lowered by a dimension obtained by adding 1/2 of the thickness of the flat portion formed in the central portion of the peripheral edge of the semiconductor wafer by the chamfering process. Then, the wafer holder is horizontally moved to bring the upper edge of the semiconductor wafer into contact with the upper inclined surface of the grooved grindstone to polish the upper edge.
【0009】半導体ウエハの上縁部の研磨が終了する
と、溝付き砥石の平坦面の幅から半導体ウエハの平坦部
の厚さを減算した寸法分だけウエハ保持台を下降し、半
導体ウエハの下縁部を溝付き砥石の下傾斜面で研磨す
る。本発明の第2発明によれば、面取り加工によりウエ
ハの周縁の中央部に形成される平坦部の幅寸法、溝付き
砥石の上曲面と下曲面の曲率半径値、及び上傾斜面と下
傾斜面の傾斜角度を入力して、ウエハの面取りを行う。
これにより、半導体ウエハの厚さに影響されることなく
半導体ウエハの面取り形状を同じにすることができる。When the polishing of the upper edge portion of the semiconductor wafer is completed, the wafer holding table is lowered by the dimension of the width of the flat surface of the grooved grindstone minus the thickness of the flat portion of the semiconductor wafer, and the lower edge of the semiconductor wafer is lowered. The part is ground on the lower inclined surface of the whetstone with a groove. According to the second aspect of the present invention, the width dimension of the flat portion formed in the central portion of the peripheral edge of the wafer by the chamfering process, the radius of curvature of the upper curved surface and the lower curved surface of the grooved grindstone, and the upper inclined surface and the lower inclined surface. The chamfering of the wafer is performed by inputting the inclination angle of the surface.
As a result, the chamfered shape of the semiconductor wafer can be made the same without being affected by the thickness of the semiconductor wafer.
【0010】また、前記平坦部の幅寸法の値をゼロ入力
して、ウエハの周縁面を曲面状に形成しても良い。Further, the value of the width of the flat portion may be zeroed to form the peripheral surface of the wafer into a curved surface.
【0011】[0011]
【実施例】以下、添付図面に従って本発明に係る半導体
ウエハの面取方法の好ましい実施例を詳説する。図1に
示す半導体ウエハ10は、該半導体ウエハ10の保持機
構であるウエハ吸着台12の上面12Aに吸着保持され
ている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a chamfering method for a semiconductor wafer according to the present invention will be described in detail below with reference to the accompanying drawings. The semiconductor wafer 10 shown in FIG. 1 is suction-held on an upper surface 12A of a wafer suction table 12 which is a holding mechanism of the semiconductor wafer 10.
【0012】一方、砥石14は、その周縁の中央部に平
坦面16が形成されると共に、該平坦部16の上端、及
び下端に上曲面18A、下曲面18Bを介して上傾斜面
20A、下傾斜面20Bが形成された溝付き砥石として
形成され、前記傾斜面20A、20Bは研磨面として構
成されている。また、この砥石14は、回転軸P−Pに
よって所定の回転数で回転される。前記回転軸P−Pは
図2に示すように、半導体ウエハ10の保持中心軸Q−
Qに対し、鉛直方向に於いて平行に配置されている。On the other hand, the grindstone 14 has a flat surface 16 formed at the center of the peripheral edge thereof, and the upper and lower ends of the flat portion 16 are provided with an upper curved surface 18A and a lower curved surface 18B through an upper inclined surface 20A and a lower surface. It is formed as a grindstone with a groove in which the inclined surface 20B is formed, and the inclined surfaces 20A and 20B are configured as polishing surfaces. Further, the grindstone 14 is rotated at a predetermined rotation speed by the rotation axis PP. As shown in FIG. 2, the rotation axis P-P is the central axis Q- for holding the semiconductor wafer 10.
It is arranged parallel to Q in the vertical direction.
【0013】次に、前記砥石14による半導体ウエハ1
0の面取方法について説明する。先ず図1に示すよう
に、砥石14に形成された平坦面16と上曲面18Aと
の境界部sの水平方向延長線上に、ウエハ吸着台12の
上面12Aを同一面上に位置させる。次に、予め測定さ
れた半導体ウエハ10の厚さtの半分(t/2)と、面
取りによって半導体ウエハ10の周縁の中央部に形成さ
れる平坦部10Cの厚さX3(図2参照)の半分(X3
/2)とを加算した寸法分だけ、前記ウエハ吸着台12
を図1中二点鎖線で示すように下降させる。Next, the semiconductor wafer 1 using the grindstone 14
The chamfering method of 0 will be described. First, as shown in FIG. 1, the upper surface 12A of the wafer suction table 12 is located on the same plane on the horizontal extension line of the boundary portion s between the flat surface 16 formed on the grindstone 14 and the upper curved surface 18A. Next, half (t / 2) of the thickness t of the semiconductor wafer 10 measured in advance and the thickness X3 (see FIG. 2) of the flat portion 10C formed in the central portion of the peripheral edge of the semiconductor wafer 10 by chamfering. Half (X3
/ 2) and the wafer suction table 12
Is lowered as indicated by the chain double-dashed line in FIG.
【0014】次いで、ウエハ吸着台12を砥石14に近
づく方向に水平移動させて半導体ウエハ10の上縁部1
0Aを砥石14の上傾斜面20Aに当接し、上縁部10
Aを研磨する。上縁部10Aの研磨が終了すると、砥石
14の平坦面16の幅wから半導体ウエハ10の平坦部
10Cの厚さX3を減算した寸法分だけ、ウエハ吸着台
12を下降し、半導体ウエハ10の下縁部10Bを図2
中二点鎖線で示すように下傾斜面20Bで研磨する。Next, the wafer suction table 12 is horizontally moved in a direction approaching the grindstone 14 to move the upper edge portion 1 of the semiconductor wafer 10.
0A is brought into contact with the upper inclined surface 20A of the grindstone 14, and the upper edge 10
Polish A. When the polishing of the upper edge portion 10A is completed, the wafer suction table 12 is lowered by the size obtained by subtracting the thickness X3 of the flat portion 10C of the semiconductor wafer 10 from the width w of the flat surface 16 of the grindstone 14 and the semiconductor wafer 10 The lower edge 10B is shown in FIG.
Polishing is performed on the lower inclined surface 20B as indicated by the middle two-dot chain line.
【0015】これにより、本実施例では、従来の面取加
工方法よりも簡単な加工方法で、且つ、半導体ウエハ1
0の厚さtに影響されることなく半導体ウエハの面取り
形状を確実に同じにすることができる。即ち、半導体ウ
エハ10の平坦部10Cの厚さX3を一定寸法で得るこ
とができる。尚、本実施例では、半導体ウエハ10の上
縁部10Aを研磨したのち、下縁部10Bを研磨するよ
うにしたが、他の面取り方法として、下縁部10Bを研
磨したのち、上縁部10Aを研磨しても良い。この場
合、先ず、砥石14に形成された平坦面16と下曲面1
8Bとの境界部の水平方向延長線上に、ウエハ吸着台1
2の上面12Aを同一面上に位置させ、次に、予め測定
された半導体ウエハ10の厚さtの半分(t/2)と、
半導体ウエハ10の平坦部10Cの厚さX3の半分(X
3/2)とを加算した寸法分だけ、ウエハ吸着台12を
下降させる。次いで、ウエハ吸着台12を水平移動させ
て半導体ウエハ10の下縁部10Bを砥石14の下傾斜
面20Bに当接し、下縁部10Bを研磨する。下縁部1
0Bの研磨が終了すると、砥石12の平坦面16の幅w
から半導体ウエハの平坦部10Cの厚さX3を減算した
寸法に、前記(t/2)と(X3/2)とを加算した寸
法分だけウエハ吸着台12を上昇し、半導体ウエハ10
の上縁部10Aを上傾斜面20Aで研磨すれば良い。As a result, in the present embodiment, the processing method is simpler than the conventional chamfering processing method, and the semiconductor wafer 1 is
The chamfered shape of the semiconductor wafer can be surely made the same without being influenced by the thickness t of 0. That is, the thickness X3 of the flat portion 10C of the semiconductor wafer 10 can be obtained with a constant dimension. In this embodiment, after polishing the upper edge 10A of the semiconductor wafer 10 and then polishing the lower edge 10B, another chamfering method is to polish the lower edge 10B and then the upper edge. 10A may be polished. In this case, first, the flat surface 16 formed on the grindstone 14 and the lower curved surface 1
The wafer suction table 1 is placed on the horizontal extension line of the boundary with 8B.
The upper surface 12A of the second wafer 2 is located on the same plane, and then half the thickness t of the semiconductor wafer 10 measured in advance (t / 2),
Half the thickness X3 of the flat portion 10C of the semiconductor wafer 10 (X
3/2) is added, and the wafer suction table 12 is moved down by the size. Next, the wafer suction table 12 is horizontally moved to bring the lower edge portion 10B of the semiconductor wafer 10 into contact with the lower inclined surface 20B of the grindstone 14 to polish the lower edge portion 10B. Lower edge 1
When the polishing of 0B is completed, the width w of the flat surface 16 of the grindstone 12
Then, the wafer suction table 12 is raised by a size obtained by adding the above (t / 2) and (X3 / 2) to the size obtained by subtracting the thickness X3 of the flat portion 10C of the semiconductor wafer from the semiconductor wafer 10
The upper edge portion 10A may be polished with the upper inclined surface 20A.
【0016】また、本実施例では、半導体ウエハ10を
停止した状態で面取りするとしたが、回転させて面取り
するようにしても良い。更に、本実施例では、半導体ウ
エハ10を砥石14に押し当てるとしたが、砥石14を
半導体ウエハ10に押し当てるようにしても良い。一
方、本発明の他の実施例として、面取り加工により半導
体ウエハ10の周縁の中央部に形成される平坦部16の
幅寸法w、溝付き砥石14の上曲面18Aと下曲面18
Bの曲率半径値、及び上傾斜面20Aと下傾斜面20B
の傾斜角度を入力して、ウエハの面取りを行うようにし
たので、半導体ウエハ10の厚さに影響されることなく
半導体ウエハ10の面取り形状を同じにすることができ
る。In the present embodiment, the chamfering is performed while the semiconductor wafer 10 is stopped, but the chamfering may be performed by rotating the semiconductor wafer 10. Furthermore, in this embodiment, the semiconductor wafer 10 is pressed against the grindstone 14, but the grindstone 14 may be pressed against the semiconductor wafer 10. On the other hand, as another embodiment of the present invention, the width dimension w of the flat portion 16 formed in the central portion of the peripheral edge of the semiconductor wafer 10 by the chamfering process, the upper curved surface 18A and the lower curved surface 18 of the grooved grindstone 14.
B curvature radius value, and upper inclined surface 20A and lower inclined surface 20B
Since the chamfering of the wafer is performed by inputting the inclination angle of, the chamfered shape of the semiconductor wafer 10 can be made the same without being affected by the thickness of the semiconductor wafer 10.
【0017】また、前記平坦部16の幅寸法wの値をゼ
ロ入力して、本来平坦部が形成されるウエハの周縁面1
0Cを図3に示すように曲面状に形成しても良い。Further, by inputting the value of the width dimension w of the flat portion 16 as zero, the peripheral surface 1 of the wafer where the flat portion is originally formed is
0C may be formed in a curved shape as shown in FIG.
【0018】[0018]
【発明の効果】以上説明したように本発明の第1発明に
係る半導体ウエハの面取方法によれば、半導体ウエハの
厚さに影響されることなく半導体ウエハの面取り形状を
同じにすることができる。本発明の第2発明に係る半導
体ウエハの面取方法によれば、面取り加工によりウエハ
の周縁の中央部に形成される平坦部の幅寸法、溝付き砥
石の上曲面と下曲面の曲率半径値、及び上傾斜面と下傾
斜面の傾斜角度を入力して、ウエハの面取りを行うよう
にしたので、半導体ウエハの厚さに影響されることなく
半導体ウエハの面取り形状を同じにすることができる。As described above, according to the chamfering method for a semiconductor wafer according to the first aspect of the present invention, the chamfered shape of the semiconductor wafer can be made the same without being influenced by the thickness of the semiconductor wafer. it can. According to the chamfering method for a semiconductor wafer according to the second aspect of the present invention, the width dimension of the flat portion formed in the central portion of the peripheral edge of the wafer by the chamfering process, the radius of curvature values of the upper and lower curved surfaces of the whetstone with a groove. Since the chamfering of the wafer is performed by inputting the inclination angles of the upper inclined surface and the lower inclined surface, the chamfered shape of the semiconductor wafer can be made the same without being affected by the thickness of the semiconductor wafer. .
【0019】また、前記平坦部の幅寸法の値をゼロ入力
して、ウエハの周縁面を曲面状に形成しても良い。Further, the value of the width of the flat portion may be zeroed to form the peripheral edge of the wafer into a curved surface.
【図1】本発明に係る面取方法のウエハ保持台の初期設
定位置を示す側面図FIG. 1 is a side view showing an initial setting position of a wafer holding table in a chamfering method according to the present invention.
【図2】本発明に係る面取方法の面取状況を示す要部拡
大図FIG. 2 is an enlarged view of an essential part showing a chamfering condition of a chamfering method according to the present invention.
【図3】本発明に係る面取方法の他の実施例で面取りさ
れたウエハ面取形状の要部拡大図FIG. 3 is an enlarged view of an essential part of a chamfered wafer chamfered by another embodiment of the chamfering method according to the present invention.
【図4】従来の面取方法の面取状況を示す側面図FIG. 4 is a side view showing a chamfering condition of a conventional chamfering method.
【図5】半導体ウエハの基本となる面取形状を示す要部
側面図FIG. 5 is a side view of an essential part showing a basic chamfered shape of a semiconductor wafer.
【図6】面取り部分の中央部に尖鋭部が形成された半導
体ウエハの要部側面図FIG. 6 is a side view of a main portion of a semiconductor wafer in which a sharp portion is formed in the center of a chamfered portion.
10…半導体ウエハ 12…ウエハ吸着台 14…砥石 16…平坦面 20A、20B…傾斜面 DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer 12 ... Wafer adsorption | suction table 14 ... Whetstone 16 ... Flat surface 20A, 20B ... Inclined surface
Claims (3)
に、該平坦面の上端、及び下端に上曲面、下曲面を介し
て上傾斜面、下傾斜面が形成された溝付き砥石を回転さ
せ、該溝付き砥石にウエハ保持台に保持された半導体ウ
エハの周縁を当接して面取り加工する半導体ウエハの面
取方法に於いて、 前記溝付き砥石に形成された前記平坦面と上曲面との境
界部の水平方向延長線上に、前記ウエハ保持台の上面が
同一面上に位置するようにウエハ保持台を移動し、 予め測定された半導体ウエハの厚さの1/2と、面取り
加工によって半導体ウエハの周縁の中央部に形成される
平坦部の厚さの1/2とを加算した寸法分だけ前記ウエ
ハ保持台を下降し、 前記ウエハ保持台を水平移動させて半導体ウエハの上縁
部を溝付き砥石の上傾斜面に当接させて上縁部を研磨
し、 前記溝付き砥石の平坦面の幅から前記半導体ウエハの平
坦部の厚さを減算した寸法分だけ前記ウエハ保持台を下
降させて半導体ウエハの下縁部を溝付き砥石の下傾斜面
で研磨することを特徴とする半導体ウエハの面取方法。1. A grooved grindstone in which a flat surface is formed at the center of the peripheral edge, and an upper sloped surface and a lower sloped surface are formed on the upper and lower ends of the flat surface through upper and lower curved surfaces, respectively. In a chamfering method of a semiconductor wafer, which is rotated, and a peripheral edge of a semiconductor wafer held on a wafer holding table is brought into contact with the grooved grindstone, the flat surface and the upper curved surface formed on the grooved grindstone. The wafer holder is moved so that the upper surface of the wafer holder is located on the same plane on the horizontal extension line of the boundary with the chamfering process. By lowering the wafer holder by a dimension obtained by adding 1/2 of the thickness of the flat portion formed in the central portion of the peripheral edge of the semiconductor wafer, and horizontally moving the wafer holder to move the upper edge of the semiconductor wafer. Abutting the upper part of the grindstone with grooves The upper edge portion is polished, and the wafer holding table is lowered by the dimension of the flat surface of the grooved grindstone minus the thickness of the flat portion of the semiconductor wafer to lower the lower edge of the semiconductor wafer to the grooved grindstone. A method for chamfering a semiconductor wafer, which comprises polishing the lower inclined surface.
に、該平坦面の上端、及び下端に上曲面、下曲面を介し
て上傾斜面、下傾斜面が形成された溝付き砥石を回転さ
せ、該溝付き砥石にウエハ保持台に保持された半導体ウ
エハの周縁を当接して面取り加工する半導体ウエハの面
取方法に於いて、 面取り加工により前記ウエハの周縁の中央部に形成され
る平坦部の幅寸法、溝付き砥石の前記上曲面と下曲面の
曲率半径値、及び前記上傾斜面と下傾斜面の傾斜角度を
入力して、ウエハの面取りを行うことを特徴とする半導
体ウエハの面取方法。2. A grooved grindstone in which a flat surface is formed at the center of the peripheral edge, and an upper sloped surface and a lower sloped surface are formed on the upper and lower ends of the flat surface through an upper curved surface and a lower curved surface, respectively. In a chamfering method of a semiconductor wafer, which is rotated, and a peripheral edge of a semiconductor wafer held on a wafer holding table is brought into contact with the grooved grindstone to form a chamfer, which is formed in a central portion of the peripheral edge of the wafer by chamfering. A semiconductor wafer characterized by performing chamfering of a wafer by inputting a width dimension of a flat portion, radius-of-curvature values of the upper curved surface and the lower curved surface of a whetstone with grooves, and an inclination angle of the upper inclined surface and the lower inclined surface. Chamfering method.
平坦部の幅寸法の値をゼロ入力して、ウエハの周縁面を
曲面状に形成することを特徴とする請求項2記載の半導
体ウエハの面取方法。3. The semiconductor device according to claim 2, wherein the value of the width dimension of the flat portion formed in the central portion of the peripheral edge of the wafer is zero-input to form the peripheral surface of the wafer into a curved surface. Wafer chamfering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20079493A JPH0758065A (en) | 1993-08-12 | 1993-08-12 | Chamfering method for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20079493A JPH0758065A (en) | 1993-08-12 | 1993-08-12 | Chamfering method for semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0758065A true JPH0758065A (en) | 1995-03-03 |
Family
ID=16430304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20079493A Pending JPH0758065A (en) | 1993-08-12 | 1993-08-12 | Chamfering method for semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758065A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6685539B1 (en) | 1999-08-24 | 2004-02-03 | Ricoh Company, Ltd. | Processing tool, method of producing tool, processing method and processing apparatus |
| KR101277460B1 (en) * | 2010-07-30 | 2013-07-05 | (주) 태양기전 | Chamfer Tool |
-
1993
- 1993-08-12 JP JP20079493A patent/JPH0758065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6685539B1 (en) | 1999-08-24 | 2004-02-03 | Ricoh Company, Ltd. | Processing tool, method of producing tool, processing method and processing apparatus |
| KR101277460B1 (en) * | 2010-07-30 | 2013-07-05 | (주) 태양기전 | Chamfer Tool |
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