JPH0759012A - Solid-state image pickup device and its drive method - Google Patents

Abstract

PURPOSE:To eliminate production of deviation of a picture even when a shutter is driven at a high speed by attaining interlace reading and the operation of a full frame electronic shutter regardless of full picture element simultaneous reading. CONSTITUTION:Signal charges 1-4, 9-12 of an odd number line in a light receiving section 1 are respectively read by vertical transfer registers 2B1, 2B2 of an even number column respectively and signal charges 5-8, 13-16 of an even number line in the light receiving section 1 are respectively read by vertical transfer registers 2A1, 2A2, 2A3 of an odd number column respectively. Thus, the register 2B1 reads the signal charges 1, 2, 9, 10 from the light receiving sections at both sides, the register 2B. reads the signal charges 3, 4, 11, 12, the register 2A1 reads the signal charges 5, 14, the register 2A2 reads the signal charges 6, 7, 14, 15, and the register 2A3 reads the signal charges 8, 16. Only the registers 2B1, 2B2 of an even number column from which the charges are read are driven in a 1st field, the charges of an odd number line are transferred to a horizontal transfer register 3, and an output section 4 provides an output of a CCD signal. The CCD signal is outputted similarly in a 2nd filed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a driving method thereof.

[0002]

2. Description of the Related Art As CCD solid-state image pickup devices, CCD solid-state image pickup devices such as interline transfer (IT) type and frame interline transfer (FIT) type are known.

The IT type CCD solid-state image pickup device includes a plurality of light receiving portions arranged in a matrix, a plurality of vertical transfer registers of CCD structure arranged on one side of each light receiving portion row, and a horizontal transfer register of CCD structure. The signal charge photoelectrically converted by the light receiving section is read into the vertical transfer register in the vertical blanking period, and then the signal charge for each horizontal line is transferred from the vertical transfer register to the horizontal transfer register in the horizontal blanking period. , Is output through the horizontal transfer register.

In the FIT CCD solid-state image pickup device, a plurality of light receiving parts are arranged in a matrix, and a vertical transfer register having a CCD structure is arranged on one side of each light receiving part row, and a vertical transfer of the image pickup parts. It comprises a storage unit having a plurality of vertical transfer registers of CCD structure corresponding to the registers and a horizontal transfer register of CCD structure. After the vertical blanking period, the signal charge of the light receiving unit is read out to the vertical transfer register. , A high-speed transfer from the image pickup unit to the storage unit (so-called frame shift transfer) to temporarily store the signal charge in the storage unit, and then transfer the signal charge for each horizontal line to the horizontal transfer register (so-called line shift) in the horizontal blanking period. Transfer) and output through the horizontal transfer register.

Typical signal charge reading methods include field reading and frame reading.
The field readout is a method in which all pixels are read out simultaneously for each field, and the signal charges of two different horizontal lines in the odd field and the even field are added and output.

In frame reading, light is received and charges are accumulated for one frame period, and only the signal charges of the light receiving portions of the odd lines and only the signal charges of the light receiving portions of the even lines are alternately read out for each field. So-called interlaced reading is performed.

In addition, in the FIT type CCD solid-state image pickup device, the frame read method is used, and immediately after the signal charge of the first field is read and the frame shift transfer is performed, the signal charge of the second field is read to perform the interlaced read. The method of doing is also proposed.

Further, the CCD solid-state image pickup device has a structure in which storage units are arranged on both sides of the image pickup unit and horizontal transfer registers are arranged in each of the storage units, and an odd number is used during frame shift transfer from the image pickup unit to the storage unit. Frame shifts the signal charges of one line to the one storage unit and the signal charges of the even line to the other storage unit, reads only the signal charges of the odd lines of one storage unit in the odd field, and stores the other in the even field. A method has also been proposed in which only the signal charges of even-numbered lines of a part are read out.

[0009]

By the way, as a method of realizing a so-called full-frame electronic shutter in which a shutter is operated at an arbitrary time point within a frame period in a CCD solid-state image pickup device, all-pixel reading is performed. However, interlaced reading cannot be performed with a normal structure such as an IT type or FIT type.

Further, in the FIT type CCD solid-state image pickup device which reads the second field immediately after the frame shift transfer (high speed transfer) of the first field described above, the frame electronic shutter and the interlaced read can be artificially performed.
However, since the read times of the first field and the second field are slightly different from each other, image misalignment occurs during high-speed shuttering.

Further, in the double-sided frame shift transfer type CCD solid-state image pickup device in which the storage portions are arranged on both sides of the image pickup portion, interlacing is possible by reading all pixels, but there is a drawback that the structure is complicated.

In view of the above points, the present invention provides a solid-state image pickup device having a simple structure and capable of interlace reading with a full-frame electronic shutter, and a driving method thereof.

[0013]

A first aspect of the present invention is directed to a plurality of light receiving portions 1 arranged in a matrix and a first vertical transfer portion 2B arranged between every other row of the light receiving portions 1. [2B ₁ , 2
B ₂ ], and a second vertical transfer section 2 A [2 A ₁ , 2 A ₂ , 2 A ₃ ], which is arranged between the remaining columns of the light receiving section 1.
In a method for driving a solid-state imaging device having a horizontal transfer unit 3 that horizontally transfers charges from the first and second vertical transfer units 2B and 2A, a signal charge of a first light receiving unit group located every other row. To the first vertical transfer section 2B, and the signal charges of the second light receiving section groups located every other row are read out to the second vertical transfer section 2A.

According to a second aspect of the present invention, in the above driving method, the solid-state image pickup device is a FIT (frame interline transfer) type solid-state image pickup device.

A third aspect of the present invention is the driving method described above,
The signal charges of the first light receiving unit group and the signal charges of the second light receiving unit group are read simultaneously.

A fourth aspect of the present invention is the drive method as described above.
During the signal charge transfer period of the first vertical transfer unit 2B, the signal charge transfer of the second vertical transfer unit 2A is stopped, and during the signal charge transfer period of the second vertical transfer unit 2A, the first vertical transfer unit 2B. The signal charge transfer is stopped.

A fifth aspect of the present invention is the drive method as described above,
The first or second vertical transfer unit 2 during the horizontal blanking period.
Two vertical bits of B or 2A are transferred to the horizontal transfer unit 3.

In a sixth aspect of the invention, a plurality of light receiving portions 1 arranged in a matrix and a first vertical transfer portion 2B [2B ₁ , 2B ₂ arranged between every other row of the light receiving portions 1 are arranged. ] And a second vertical transfer unit 2A disposed between the other columns of the light receiving unit 1
In the solid-state imaging device having [2A ₁ , 2A ₂ , 2A ₃ ] and the horizontal transfer unit 3 that horizontally transfers the charges from the first and second vertical transfer units 2B and 2A, To the vertical transfer unit 2 [2A, 2B], the read gate unit is provided to the first vertical transfer unit 2B side in the light receiving unit 1 located in the odd row, and the second vertical transfer in the light receiving unit 1 located in the even row. It is provided on the side of the section 2A and configured.

A seventh aspect of the present invention is the solid-state image pickup device as described above, comprising a storage section 34 between the first and second vertical transfer sections 2B and 2A and the horizontal transfer section 3.

An eighth aspect of the present invention is the solid-state image pickup device as described above, wherein the first and second vertical transfer sections 2B and 2 are provided in the storage section 34.
Each column of A has one accumulation and transfer unit 42, and the accumulation unit 3
4 and the first and second vertical transfer units 2B and 2A, the charge of the first and second vertical transfer units 2B and 2A is alternately distributed to the adjacent storage / transfer unit 33 for each vertical unit bit. A gate 43 is provided and configured.

A ninth aspect of the present invention is the solid-state image pickup device according to the seventh aspect, wherein the storage section 34 has one storage / transfer section 52 for every two columns of the first and second vertical transfer sections 2B and 2A. To configure.

A tenth aspect of the present invention is the solid-state image pickup device as described above, wherein the first and second vertical transfer sections 2B and 2A are the first and second.
One bit is formed by the second and third three electrodes 7, 8 and 9.

An eleventh invention is the solid-state image pickup device according to the tenth invention, wherein the first and second electrodes 7 and 8 are wired in the horizontal direction, and the third electrode 9 is wired in the vertical direction. The third electrode 9 is configured to be electrically independent of the first vertical transfer section 2B and the second vertical transfer section 2A.

[0024]

In the method of driving the solid-state image pickup device according to the first aspect of the present invention, the signal charges of the first light receiving unit group located in every other row (for example, in an odd number of lines) are read out to the first vertical transfer unit 2B and the rest. The signal charges of the second light receiving unit group (for example, even-numbered lines) located every other row are transferred to the second vertical transfer unit 2A.
Then, if the first vertical transfer unit 2B and the second vertical transfer unit 2A are selectively driven for each field thereafter, all-pixel simultaneous read and interlaced read can be performed. Since all pixels can be read simultaneously, a full frame electronic shutter is possible.

In the driving method according to the second aspect of the present invention, the solid-state image pickup device is of the FIT type, whereby the difference between the odd field and the even field of smear and dark current can be reduced.

In the driving method according to the third aspect of the present invention, the signal charges of the first light receiving unit group located every other row and the signal charges of the remaining second light receiving unit group located every other line are simultaneously and simultaneously respectively. First vertical transfer unit 2B and second vertical transfer unit 2A
By reading out all pixels, all pixels are read out, and the full-frame electronic shutter operation can be performed. Moreover,
After that, since the first vertical transfer unit 2B and the second vertical transfer unit 2A can be selectively driven for each field, all-pixel simultaneous reading and interlaced reading can be performed.

In the driving method according to the fourth aspect of the present invention, the signal charge transfer of the second vertical transfer section 2A is stopped during the signal charge transfer period of the first vertical transfer section 2B, and the second vertical transfer section is stopped. During the signal charge transfer period of 2A, the first vertical transfer unit 2B
Since the signal charge transfer of 1 is stopped, all-pixel reading and interlaced reading are performed.

In the driving method according to the fifth aspect of the invention, the first or second vertical transfer section 2B is provided during the horizontal blanking period.
Alternatively, by transferring the signal charges for 2 vertical bits of 2A to the horizontal transfer unit 3, the signal charges are transferred in the same arrangement order as the arrangement of the light receiving units 1 located in the odd row or the even row with respect to the horizontal transfer unit 3. can do.

In the solid-state image pickup device according to the sixth aspect of the present invention, the read gate section 6 for reading out the electric charge of the light receiving section 1 to the vertical transfer section 2 is arranged so that the light receiving section 1 located in an odd row has the first vertical transfer section side 2B. In the light receiving parts 1 located in even rows,
When the signal charges of the respective light receiving units 1 are simultaneously read out, the signal charges of the light receiving units 1 located in the odd rows are read out to the first vertical transfer unit 2B by being provided on the vertical transfer unit 2A side. The signal charges of the light receiving sections 1 located in even rows are read out to the second vertical transfer section 2A. Therefore, thereafter, if the first vertical transfer unit 2B and the second vertical transfer unit 2A are selectively driven for each field, interlaced reading (scanning) can be performed.

In the solid-state image pickup device according to the seventh aspect of the present invention, since the storage unit 34 is provided between the horizontal transfer unit 3 and the first and second vertical transfer units 2B and 2A, all pixels can be read simultaneously. A FIT type solid-state imaging device capable of interlaced reading can be configured.

In the solid-state image pickup device according to the eighth aspect of the present invention, one accumulation / transfer unit is provided for each column of the first and second vertical transfer units 2B and 2A in the storage unit 34 of the FIT type solid-state image pickup device. 42, and between the storage unit 34 and the first and second vertical transfer units 2B and 2A, the charges of the first and second vertical transfer units 2B and 2A are adjacently stored for each vertical unit bit. A control gate 43 for alternately allocating to the dual transfer unit is provided. Therefore, in all-pixel reading, the signal charges of the light receiving units 1 located in odd rows are read to the first vertical transfer unit 2B, and the signal charges of the light receiving units 1 located in even rows are second.
Of the first vertical transfer unit 2B, the signal charge of each first vertical transfer unit 2B is first transferred by the control gate 43 to the adjacent storage / transfer unit 42 of the storage unit 34 alternately. Subsequently, the control gate 43 transfers the signal charges of each second vertical transfer section 2A to the adjacent storage / transfer section 42 of the storage section 34 alternately. Therefore, the signal charges are arranged in the accumulating section 34 in the same arrangement order as the light receiving sections 1, and the lower half of the accumulating section 34 accumulates the signal charges in the odd rows and the upper half accumulates the signal charges in the even rows. Thereafter, the signal charges of the odd-numbered rows are read from the storage section 34 to the horizontal transfer section 3 in the first field period, and the signal charges of the even-numbered rows are read in the next second field period. In this configuration, the period in which the driving of the first and second vertical transfer units 2B and 2A in the image pickup unit 32 is stopped is extremely short only during high-speed transfer (so-called frame shift transfer) in which the image pickup unit 32 transfers to the storage unit 34. Since it is time, it is possible to avoid the occurrence of dark current unevenness together with the smear component.

In the solid-state image pickup device according to the ninth aspect of the invention, the storage section 34 includes the first and second vertical transfer sections 2B and 2B.
Since this is a storage unit having one storage / transfer unit 52 for every two columns of A, in all pixel reading, the signal charges of the light receiving units 1 located in odd rows are read to the first vertical transfer unit 2B, After the signal charges of the light receiving portions 1 located in the even rows are read out to the second vertical transfer portions 2A, first, the signal charges of the respective first vertical transfer portions 2B are stored and transferred in the storage portions 34 respectively. Then, the signal charges of the second vertical transfer units 2A are transferred to the same unit / storage unit 52 of the storage unit 34 as described above. Therefore, in the accumulation unit 34, the signal charges corresponding to the odd rows are accumulated in the lower half and the signal charges corresponding to the even rows are accumulated in the upper half. After that, the signal charges of the odd-numbered rows are read out from the horizontal transfer unit 3, and then the signal charges of the even-numbered rows are read out.
The signal charges are transferred to the horizontal transfer unit 3 every two lines and read out in the horizontal transfer unit 3 in an arrangement order corresponding to the arrangement order of the light receiving units. In this configuration, the vertical transfer unit 52 in the storage unit 34 is provided as one vertical transfer unit 52 for the two vertical transfer units 2 in the image capturing unit 32, so that the transfer efficiency of the vertical transfer unit 52 in the storage unit 34 can be improved. it can. The structure is also simplified.

In the solid-state image pickup device according to the tenth aspect of the present invention, the first and second vertical transfer sections 2B and 2A constitute one bit by the first, second and third electrodes 7, 8 and 9. Therefore, the three-phase drive system can be adopted.

In the solid-state image pickup device according to the eleventh invention, the first and second electrodes 7 and 8 are wired in the horizontal direction,
Wire the third electrode 9 in the vertical direction, and connect the third electrode 9 to the first electrode.
By making the vertical transfer section 2B and the second vertical transfer section 2A electrically independent of each other, the third electrode 9 allows
The vertical transfer unit 2B and the second vertical transfer unit 2A can be separated from each other, and interlaced reading can be performed.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 6 show a first embodiment of the present invention applied to an interline transfer (IT) type solid-state image pickup device.

As shown in FIG. 1, the IT type solid-state image pickup device 11 of the present embodiment has a plurality of light receiving portions 1 arranged in a matrix and a CCD arranged so as to sandwich each light receiving portion row (n rows). Multiple (n + 1) vertical transfer registers 2 [2A, 2B] of structure
And a horizontal transfer register 3 having a CCD structure connected to the final stage of each vertical transfer register 2 and an output unit 4 connected to the final stage of the horizontal transfer register 3. At the time of driving, the signal charges [1, 2, 3, ... 15, 16] from all the light receiving portions (pixels) 1 of the odd line and the even line are read out to the vertical transfer register 2 at the same time. The signal charges of the light receiving unit 1 corresponding to each even line are distributed and read out to the vertical transfer registers 2A or 2B in the odd columns or the even columns.

That is, in the example shown in the figure, the light receiving portion 1 of the odd line
Signal charge [1, 2, 3, 4, 9, 10, 11, 12]
To the vertical transfer registers 2B ₁ and 2B ₂ in the even columns, and the signal charges [5, 5
6, 7, 8, 13, 14, 15, 16] are read to the vertical transfer registers 2A ₁ , 2A ₂ and 2A ₃ of odd-numbered columns, respectively.
Thus, the signal charges from both sides of the light receiving portion in the vertical transfer register 2B ₁ [1, 2, 9, 10] is, both sides of the signal charges from the light receiving portion 1 to the vertical transfer register 2B ₂ [3,4,1
1, 12] are read out, and the signal charges [5, 13] from the light receiving section 1 on one side are stored in the vertical transfer register 2A, and the signal charges [6, 6 from the light receiving section 1 on both sides are stored in the vertical transfer register 2A ₂ .
7, 14, 15], the signal charges [8, 16] from the light receiving section 1 on one side are read out to the vertical transfer register 2A ₃ (see FIG. 1).

After that, in the first field, as shown in FIG. 2, only the vertical transfer registers 2B ₁ and 2B ₂ in the even columns from which the signal charges of the odd lines are read are driven, and only the signal charges of the odd lines are driven. To the horizontal transfer register 3 and the output unit 4 outputs the CCD signal of the first field. Then, in the second field, as shown in FIG. 3, only the vertical transfer registers 2A ₁ , 2A ₂ and 2A _{3 of} the odd-numbered columns from which the signal charges of the even lines are read are driven, and the signal charges of the even lines are driven. Only the signal is transferred to the horizontal transfer register 3 and the CCD signal of the second field is output from the output unit 4.

FIG. 4 is an enlarged view of an image pickup portion including pixels in the solid-state image pickup device 11. Shaded lines 5 indicate channel stop regions that partition the respective light receiving portions 1, and 10 indicates embedded channel regions that configure the respective vertical transfer registers 2. The readout gate unit 6 of the light receiving unit 1 is arranged such that, for example, in the light receiving unit 1 located on an odd line, the vertical transfer registers 2B ₁ and 2B of even columns are arranged.
On the B ₂ side, in the light receiving section 1 located on the even line, for example, it is provided on the vertical transfer registers 2A ₁ , 2A ₂ , 2A _{3 in the} odd columns. The read gate portions 6 on both sides provided on the same vertical transfer register 2 side (that is, the read gate portions of the light receiving portions on the same lines) are formed at positions vertically displaced from each other.

On the other hand, the vertical transfer register 2 [2A, 2B]
1 bit is formed by the first transfer electrode 7 made of the first layer polycrystalline silicon, the second transfer electrode 8 made of the second layer polycrystalline silicon, and the third transfer electrode 9 made of the third layer polycrystalline silicon. Is composed of.

The first transfer electrode 7 is wired so as to extend in the horizontal direction, and is tilted on the vertical transfer register 2 so as to straddle the read gate portion 6 of the light receiving portion on the one side, for example, a right triangle shape. It is formed in the portion 7a.

The second transfer electrode 8 is also wired so as to extend in the horizontal direction, and on the vertical transfer register 2, the right triangular portion 7a of the first transfer electrode 7 and the third transfer electrode 9 are opposed to each other. Further, the same right-angled triangular portion 8a is formed so as to be inclined and to straddle the readout gate portion 6 of the light receiving portion on the other side.

The third transfer electrodes 9 [9A, 9B] are wired so as to extend in the vertical direction. The third transfer electrodes 9 are electrically independent of the vertical transfer registers 2A in the odd columns and the vertical transfer registers 2B in the even columns.

[0045] Then, the first transfer electrode 7 is a vertical transfer clock pulse .phi.V _1, third transfer electrodes 9A to the second transfer electrodes 8 is a vertical transfer clock pulse .phi.V _2, corresponding to the vertical transfer registers 2A the odd column vertical transfer clock pulse _{.phi.V. 3O} to is the third transfer electrodes 9B corresponding to the vertical transfer register 2B of the even columns vertical transfer clock pulse .phi.V _3E are respectively applied. Therefore, the vertical transfer register 2 is driven by a so-called three-phase drive pulse.

FIG. 5 is a timing chart of the vertical transfer clock pulses φV ₁ , φV ₂ , φV _3E , φV _3O , the shutter pulse, the vertical blanking pulse V-BLK, and the horizontal blanking pulse H-BLK according to this embodiment. Indicates.

FIG. 6 shows an enlarged timing chart of FIG. Note that the timings in FIG. 5 and the timings in FIG. 6 correspond to each other.

Next, the operation of the IT type solid-state image pickup device 11 according to the first embodiment will be described in more detail with reference to FIGS.

First, in the vertical blanking period T ₁ , by the read pulse 12 applied to the first transfer electrode 7 and the second transfer electrode 8, the signal charges photoelectrically converted in each light receiving unit 1 are received by all the pixels at the same time. It is read from 1 to the vertical transfer register 2. At this time, the third transfer electrodes 9A and 9B
Vertical transfer clock pulse _{.phi.V. 3O} applied to, by the .phi.V _3E to a low level, as shown in FIG. 4, the light receiving unit 1, for example, the left signal charges of the light receiving portion 1 of the even-numbered lines (6)
Is below the second transfer electrode 8a of the vertical transfer register 2A _2, the right signal electrodes (7) of the light receiving portion 1 of each read under the first transfer electrode 7a in the same vertical transfer register 2A _2, on the other hand,
In the light receiving unit 1 of the odd line, for example, the signal charge of the left light receiving unit 1

[9] is the second transfer electrode 8 of the vertical transfer register 2B ₁ .
The signal charges [10] of the light receiving section 1 on the right side are read under the first transfer electrodes 7a of the same vertical transfer register 2B ₁ under a, and the signal charges of two pixels on the same line correspond to the corresponding vertical transfer. The registers 2A and 2B are read so as to be bisected in the vertical direction.

Next, in the first field, the vertical transfer pulse φV _3E applied to the third transfer electrode 9A of the vertical transfer registers 2A [2A ₁ , 2A ₂ , 2A ₃ ] in odd columns is set to the highest level of three values. Fixed to this vertical transfer register 2
Vertical transfer of even columns is performed by vertical transfer pulses φV ₁ , φV ₂ , and φV _3O applied to the first transfer electrode 7, the second transfer electrode 8, and the third transfer electrode 9B while the charge transfer at A is stopped. Only the register 2B [2B ₁ , 2B ₂ ] is driven, and only the signal charges of the odd lines are transferred from the vertical transfer register 2B to the horizontal transfer register 3 line by line in the horizontal blanking period T ₂ .

Since the signal charges of the two pixels on the same line are vertically present in the vertical transfer register 2B in the upper and lower two stages, the horizontal transfer from the vertical transfer register 2B is performed in the horizontal blanking period T ₂ . Transfer for two stages to the register 3 is performed. As a result, in the horizontal transfer register 3, signal charges [1, 2, 3, 4],
An array order of [9, 10, 11, 12] is obtained, and thereafter,
After the transfer in the horizontal transfer register 3, the CCD signal of the first field is output from the output unit 4.

Next, in the second field, on the contrary, even columns
Vertical transfer register 2B [2B₁, 2B₂] Third transfer
Vertical transfer pulse φV of electrode 9B_3OIs the highest of the three values
Fixed to a certain level and the vertical transfer registers 2B in the even columns
The first transfer electrode 7 and the second transfer in the state where the charge transfer is stopped.
Vertical transfer φ applied to the electrode 8 and the third transfer electrode 9A
V ₁, ΦV₂, ΦV_3EDepending on the vertical transfer register
Star 2A [2A₁, 2A₂, 2A₃] Only drive water
Flat blanking period T₂Only the signal charge of the even lines
For each line, the horizontal transfer register from the vertical transfer register 2A
Transfer to Star 3.

In this case as well, the vertical transfer register 2A to the horizontal transfer register 3 within the horizontal blanking period T ₂ .
The signal charges of two stages are transferred to the signal charges [5, 6, 7, 8], [13, 14, 15,] in the order of arrangement corresponding to the same line in the horizontal transfer register. 1
6] is obtained, and thereafter, the data is transferred in the horizontal transfer register and the CCD signal of the second field is output from the output unit 4.

According to the IT type solid-state image pickup device 11 described above,
It is possible to perform interlace scanning (reading) while the light receiving and accumulating period is one frame period and simultaneous reading is performed for all pixels. Further, since all pixels are simultaneously read and interlaced reading is performed, the shutter pulse 13 is read at a specific time point within the frame period (light reception accumulation period).
A full-frame electronic shutter is possible by applying an electric shutter (see FIG. 5) to sweep out electric charges to the substrate side. The timing of reading out the signal charges from the light receiving unit 1 is
Since the odd-numbered field and the even-numbered field are at the same time, the image shift does not occur even at the high speed shutter.

In FIG. 4, if the pattern of the channel stop region 5 is changed so that each read gate section 6 of each light receiving section row is provided only on one vertical transfer register side, all pixels are read out and two horizontal rows are read out. 2 from transfer register
It is possible to perform so-called progressive scanning in which the signal charges of each horizontal line are independently read.

Also, with the structure of FIG. 4 described above, progressive scanning is naturally possible by devising driving.

A problem in the case where the solid-state image pickup device is configured by the IT type is that the driving of the vertical transfer register 2 is stopped for one field period, so that unnecessary charges of the smear component and the dark current component are generated in the vertical transfer register 2. Is accumulated in the vertical transfer register 2 and becomes uneven due to variations in each vertical transfer register 2. To avoid this, the FIT type may be used.

FIGS. 7 to 13 are the second to fourth embodiments in which the present invention is applied to a FIT type solid-state image pickup device, respectively.

In the FIT type solid-state image pickup device 31 according to the second embodiment shown in FIG. 7, a plurality of light receiving parts 1 are arranged in a matrix, and a plurality of CCD structures are arranged so as to sandwich each light receiving part row (n rows). An image pickup section 32 in which (n + 1) vertical transfer registers 2 [2A, 2B] are arranged, and a plurality of (n + 1) vertical transfer registers of CCD structure corresponding to the vertical transfer registers 2 of the image pickup section 32, that is, storage and storage A storage unit 34 having a vertical transfer register 33 [33A, 33B] for transfer, and a CCD
It has a horizontal transfer register 3 having a structure and an output section 4 connected to the final stage of the horizontal transfer register 3. The vertical transfer register 33 of the storage unit 34 is formed by extending the vertical transfer register 2 of the imaging unit 32.

In the image pickup section 32, as in the case of FIG. 4, for example, the signal charges of the light receiving section 1 located on the odd line are read out to the vertical transfer registers 2B [2B ₁ , 2B ₂ ] of the even column, and are located on the even line. The signal charges of the light receiving section 1 are read out to the vertical transfer registers 2A [2A ₁ , 2A ₂ , 2A ₃ ] of odd columns.

The transfer electrodes in the vertical transfer registers 2 and 33 of the image pickup section 32 and the storage section 34 are formed in the same manner as shown in FIG. That is, the first layer of the first-layer polycrystalline silicon
The transfer electrode 7 and the second transfer electrode 8 of the second-layer polycrystalline silicon are formed so as to extend in the horizontal direction, and the third transfer electrode 9 of the third-layer polycrystalline silicon is formed in both vertical transfer registers 2 and 22. It is formed by extending in the vertical direction so as to be common.

Then, for example, the third transfer electrodes 9A in odd columns
The vertical transfer pulse φIM _3O is applied to the third transfer electrode 9B in the even-numbered column, and the vertical transfer pulse φIM _3E is applied to the third transfer electrode 9B in the even-numbered column.
The vertical transfer pulses φIM ₁ and φIM ₂ are applied to the first transfer electrode 7 and the second transfer electrode 9 of the image pickup unit 3, respectively.
In No. ₂ , the three-phase drive system is used with φIM ₁ , φIM ₂ and φIM _3O or φIM _3E . In addition, the first in the storage unit 34
Vertical transfer clock pulses φST ₁ and φST ₂ are applied to the transfer electrode 7 and the second transfer electrode 8, and φS is applied to the storage section 32.
It is a three-phase drive system using T ₁ , φST ₂ and φIM _3O or φIM _3E .

FIG. 9 shows a FIT type solid-state imaging device according to the second embodiment.
Vertical transfer pulse φIM of image device 31 ₁, ΦIM₂, ΦS
T₁, ΦST₂, ΦIM_3E, ΦIM_3OAnd vertical blanket
7 shows a timing chart of the ing pulse V-BLK.

In the second embodiment, the vertical blanking period
Interval T₁ΦIM ₁And φIM₂Reading
By the projecting pulse 12, the signal charge of each light receiving section 1 is completely
The pixels are read out to the corresponding vertical transfer register 2 at the same time.
It That is, the signal charges [1, 2,
3, 4, 9, 10, 11, 12] correspond to even columns
Vertical transfer register 2B₁, 2B₂To receive even lines
Signal charge [5, 6, 7, 8, 13, 14, 15,
16] corresponds to the vertical transfer registers 2 of the odd-numbered columns
A₁, 2A₂, 2A₃Read out.

Next, the signal charge is the vertical transfer pulse φI.
M₁, ΦIM₂, ΦIM_3O, ΦIM _3E, ΦST₁, ΦS
T₂The frame shift transfer pulse 36 at
Lame shift transfer period T₃From the imaging unit 32 to the storage unit 3
4 high-speed transfer to the vertical transfer register 33 [33A, 33B]
Will be sent.

Next, in the line shift transfer period T _{4 of} the first field, the vertical transfer pulse φI in the storage section 34 is
By fixing M _3E to the highest level 37 of the three values, the vertical transfer registers 33A [33A ₁ , 33A ₂ , 3 of odd-numbered columns are fixed.
3A ₃ ] while the charge transfer of 3A ₃ ] is stopped, the vertical transfer registers 33B in even columns are driven by the line shift transfer pulse 38 in the vertical transfer pulses φST ₁ , φST ₂ and φIM _3O .
Only the signal charges of ₁ , 33B ₂ are transferred to the horizontal transfer register 3 (see FIG. 7).

Also at this time, similarly to the above example, the signal charges of, for example, [1, 2], [3, 4] of two pixels on the same line in the vertical direction in the vertical transfer registers 33B ₁ and 33B ₂ are horizontally blanked. Within the period, the vertical transfer register 33
Two stages are transferred from B ₁ and 33B ₂ to the horizontal transfer register 3, and the arrangement order of signal charges corresponding to the same line in the horizontal transfer register 3 [for example, 1, 2, 3, 4].
In this way, the two-phase horizontal transfer pulses φH ₁ and φH ₂ are transferred in the horizontal transfer register 3 so that the output section 4 outputs the first signal.
The CCD signal of the field is output.

Next, in the line shift transfer period T _{5 of} the second field, the vertical transfer pulse φI in the storage section 34 is transferred.
Line shift in vertical transfer pulses φST ₁ , φST ₂ and φIM _{3E with} M _3O fixed at the highest level 37 of the three values and charge transfer of vertical column transfer registers 33B ₁ and 33B _{2 in} even columns being stopped. By the transfer pulse 38, the vertical transfer registers 33A ₁ , 33A ₂ , 33A of odd-numbered columns
₃ the signal charge only to the horizontal transfer register 3 (see FIG. 8).

Also at this time, the vertical transfer registers 33A ₁ ,
The signal charges of 33A ₂ and 33A ₃ are transferred from the vertical transfer registers 33A ₁ , 33A ₂ , 33A ₃ to the horizontal transfer register 3 for two stages within the horizontal blanking period, and correspond to the same line in the horizontal transfer register 3. The signal charges are arranged in the order [5, 6, 7, 8]. In this way, the CCD signal of the second field is output from the output unit 4 through the horizontal transfer register 3.

Thereafter, in the surplus charge sweep-out transfer period T ₆ , each vertical transfer pulse φIM ₁ , φIM ₂ , φST.
Excessive charges such as smear component and dark current component remaining in the vertical transfer register 2 of the imaging unit 32 are swept to the storage unit 34 by the surplus charge sweep-out transfer pulse 39 in ₁ , φST ₂ , φIM _3E , and φIM _3O , and further, FIG. Although not shown, it is swept out to the drain region arranged below the horizontal transfer register through the horizontal transfer register 3 and the gate portion.

The vertical transfer pulses φIM and φST can be made common (φIM ₁ = φST ₁ , φIM ₂ = φST ₂ ). Further, in φIM ₁ and φIM ₂ , the line shift transfer pulse 38 in the line shift transfer periods T ₄ and T ₅ is used.
May be eliminated and fixed at a fixed level.

In the FIT type solid-state image pickup device 31 according to the second embodiment, all pixels can be simultaneously read out and interlaced scanning (reading) can be performed similarly to the upper side, and a full frame electronic shutter can be realized. And FIT
Since it is configured as a mold, smear components can be reduced compared to the IT type. However, since the storage unit 34 stops the transfer for one field period, the vertical transfer register 33 [33
A, 33B] dark current is generated.

10 and 11 show a FIT type solid-state image pickup device 41 according to the third embodiment of the present invention.

In this example, as shown in FIG. 10, a plurality of (n + 1) vertical transfer registers having a CCD structure in which a plurality of light receiving portions 1 are arranged in a matrix and each light receiving portion row (n rows) is sandwiched therebetween. 2 [2A, 2B] are arranged, and a plurality of (substantially n) CCD vertical transfer registers corresponding to the vertical transfer registers 2 of the imaging unit 32, that is, storage and transfer. Vertical transfer register 42 [42A, 4
2B], the image pickup unit 32, and the storage unit 3
4 and each one vertical transfer register 2 of the image pickup unit 32.
Control gate section 43 for allocating the signal charges of the above to the two adjacent vertical transfer registers 42A and 42B of the storage section 34, the horizontal transfer register 3 of CCD structure, and the output section connected to the final stage of the horizontal transfer register 3. 4 and.

The image pickup section 32 can be constructed in the same manner as in the second embodiment, and the vertical transfer clock pulses φIM ₁ and φI are respectively applied to the first transfer electrodes and the second transfer electrodes thereof.
M ₂ is applied, and vertical transfer clock pulses φIM _3O and φIM _3E are applied to the third transfer electrodes in the odd and even columns, respectively.

A control gate pulse φ _cont is applied to the control gate section 43.

The vertical transfer register 42 of the storage section 34 has, for example, first, second and third transfer electrodes made of polycrystalline silicon in the first, second and third layers, respectively. Three-phase vertical transfer clock pulses φST ₁ , φST _2, and φST ₃ are applied to the first, second, and third transfer electrodes.

Two-phase horizontal transfer clock pulses φH ₁ and φH ₂ are applied to the horizontal transfer register 3.

FIG. 11 shows vertical transfer pulses φIM ₁ and φI of the FIT type solid-state image pickup device 41 according to the third embodiment.
7 shows a timing chart of M ₂ , φIM _3E , φIM _3O , control gate pulse φ _cont, and vertical blanking pulse V-BLK.

In the third embodiment, in the vertical blanking period
Interval T₁ΦIM ₁, ΦIM₂Reading
All pixels at the same time by the output pulse 12, that is, odd lines
The signal charges of the light receiving section 1 of
₁, 2B₂And the signal charge of the light receiving unit 1 on the even line is odd
Column vertical transfer register 2A₁, 2A₂, 2A₃Read to each
To be found.

Next, the read signal charges of the vertical transfer register 2 are transferred to the vertical transfer pulses φIM ₁ , φIM ₂ , φIM _3O , φIM _3E and φST during the frame shift transfer period T _3.
1 , φST ₂ , φST ₃ and the frame shift transfer pulse 36 in the control gate pulse φ _cont
High-speed transfer from the image pickup unit 32 to the vertical transfer register 42 of the storage unit 34.

At this time, the frame shift transfer period T₃of
Vertical transfer pulse φIM in the first half_3EIs the highest of the three values
Fixed to level 37 and vertical transfer register 2B for even columns
₁, 2B₂Transfer only the signal charge of
Vertical transfer register 2B₁, 2
B₂2 of the same line that is vertically separated inside
The signal charge of the pixel is stored in the storage unit 34 in two adjacent columns.
Direct transfer register 42A ₁And 42B₁, 42A₂And 42B
₂High-speed transfer so as to distribute to. Accumulated by this
Vertical transfer register 42A of unit 34₁~ 42B₂Lower half
The signal charges of odd lines are arranged horizontally in each
State [1, 2, 3, 4], [9, 10, 11, 12]
Accumulated in.

Subsequent frame shift period T₃In the second half of
Vertical transfer pulse φIM_3OThe highest of the three values
Fixed to 37, vertical transfer register 2A in odd-numbered columns₁, 2A
₂, 2A₃Transfer only the signal charge of
For example, the vertical transfer register 2A
₂2 of the same line that is vertically separated inside
The signal charge of the pixel is stored in the storage unit 34 in two adjacent columns.
Direct transfer register 43B ₁And 42A₂To distribute to
Transfer at high speed. As a result, the vertical transfer record of the storage unit 34 is
Dista 42A₁~ 42B₂Even line signal in the upper half
The state where the charges are arranged horizontally for each line [5, 6,
7, 8], [13, 14, 15, 16].

Then, in the line shift transfer period T ₄ of the first field, the vertical transfer pulse φST ₁ of the storage section 34 is transferred.
The signal charges of the odd lines are transferred to the horizontal transfer register 3 by the line shift transfer pulse 38 of ˜φST ₃ , the CCD signal of the first field is output through the output unit 4, and then in the line shift transfer period T ₅ of the second field. The signal charges of the even lines are transferred to the horizontal transfer register 4, and the CCD signal of the second field is output through the output unit 4.

During the line shift transfer, the image pickup unit 3
Two vertical transfer pulses φIM ₁ , φIM ₂ , φIM _3E , φ
IM _3O and the control gate pulse φ _cont are fixed to the constant potential shown in FIG. 11, but may be operated.

After that, during the surplus charge sweep-out transfer period T ₆ within the vertical blanking period T ₁ , the surplus charge in the vertical transfer register 2 of the image pickup section 32 is swept out to the accumulating section 34 by the surplus charge sweep-out transfer pulse ₃₉ .

In the third embodiment, all pixels can be read and interlaced scanning (reading) can be performed as in the above example, and a full frame electronic shutter can be realized.

Further, the smear component can be reduced, and in particular, the period of stopping the signal charges in the vertical transfer register 2 is only a frame shift transfer period (during high-speed transfer) and is extremely short, so that a problem of dark current occurs. Absent.

Furthermore, since the control gate unit 43 is provided to horizontally rearrange the signal charges on the same line during frame shift transfer from the image pickup unit 32 to the storage unit 34,
Line shift transfer can be performed by one-stage transfer, and line shift transfer becomes easy.

12 and 13 show a FIT type solid-state image pickup device 51 according to the fourth embodiment of the present invention.

In this example, as shown in FIG. 12, a plurality of light receiving portions 1 are arranged in a matrix, and a plurality of (n + 1) vertical transfer registers 2 having a CCD structure are arranged so as to sandwich each light receiving portion (n columns).
[2A, 2B] are arranged, and a plurality of vertical transfer registers of CCD structure, that is, one vertical transfer register corresponds to each two vertical transfer registers 2 in the imaging unit 32, that is, A storage unit 34 having a vertical transfer register 52 [52A ₁ , 52B ₁ , 52A ₂ ] for storage and transfer, a horizontal transfer register 3 having a CCD structure, and an output unit 4 connected to the final stage of the horizontal transfer register 3. Comprising. In this example, the vertical transfer registers 2 in each of the two columns of the imaging unit and the vertical transfer register 52 in each of the storage units are connected.

The image pickup section 32 can be constructed in the same manner as in the second embodiment. Vertical transfer clock pulses φIM ₁ and φIM ₂ are applied to the first transfer electrode and the second transfer electrode of the image pickup section 32, respectively, and odd columns and even columns are applied. Vertical transfer clock pulses φIM _3O and φIM _3E are applied to the third transfer electrodes of the column, respectively.

The vertical transfer register 52 of the storage section 34 has first, second and third transfer electrodes made of, for example, first layer, second layer and third layer polycrystalline silicon. A three-phase vertical transfer clock pulse φST [φST ₁ , φST ₂ and φST ₃ ] is applied to the first, second and third transfer electrodes of.

Two-phase horizontal transfer clock pulses φH ₁ and φH ₂ are applied to the horizontal transfer register.

FIG. 13 shows vertical transfer pulses φIM ₁ and φI of the FIT type solid-state image pickup device 51 according to the fourth embodiment.
M ₂ , φIM _3E , φIM _3O , φST (φST ₁ , φST
₂ , φST ₃ ) and a vertical blanking pulse V-BLK timing chart.

In the fourth embodiment, in the vertical blanking period
Interval T₁ΦIM ₁, ΦIM₂Reading
All the pixels are read out simultaneously by the output pulse 12, that is,
The signal charge of the light receiving unit 1 on the odd line is transferred to the vertical transfer line on the even column.
Dista 2B₁, 2B₂The signal voltage of the light-receiving
Vertical transfer register 2A with odd number of loads₁, 2A₂, 2A ₃
Are read respectively.

Next, the read vertical transfer register 2
Vertical blanking period T of signal charge ₁Inside frame shift
Transfer period T₃, Each vertical transfer pulse φIM₁, ΦIM
₂, ΦIM_3O, ΦIM_3E, ΦST (φST₁, ΦS
T₂, ΦST₃) Frame shift transfer pulse 3
6, the signal charge is transferred vertically from the image pickup unit 32 to the storage unit 34.
It is transferred at high speed to the transfer register 52.

At this time, the frame shift transfer period T₃of
Vertical transfer pulse φIM in the first half_3EIs the highest of the three values
Fixed to level 37 and vertical transfer register 2B for even columns
₁, 2B₂Only the signal charges of the even lines existing in
Vertical transfer register 52B₁, 52A₂Fast transfer to.
As a result, each vertical transfer register 52 of the storage unit 34 is
B ₁, 52A₂The signal charge of the odd line is the same in the lower half
The signal charges of the two pixels in the line should be arranged vertically
Accumulated.

In the subsequent second half of the frame shift transfer period T ₃ , the vertical transfer pulse φIM _3O is fixed to the highest level 37 of the three values, and the vertical transfer levels 2A ₁ , 2 of the odd columns are set.
Only the signal charges of the even lines existing in A ₂ and 2A ₃ are transferred at high speed to the corresponding vertical transfer registers 52A ₁ , 52B ₁ and 52A ₂ . As a result, the signal charges of even lines are accumulated in the upper half of each vertical transfer register 52A ₁ , 52B ₁ , 52A ₂ of the accumulation unit 34 so that the signal charges of two pixels of the same line are arranged vertically.

Next, in the line shift transfer period T ₄ of the first field, the vertical transfer pulses φST _{1 to} φ φ of the storage section 34 are transferred.
By the line shift transfer pulse 38 of ST ₃ , the signal charges of the odd lines are transferred to the horizontal transfer register 3. At this time, the transfer of two stages is performed within the horizontal blanking period, and the signal charges are arranged in the horizontal transfer register 3 in the arrangement order corresponding to the same line. In this way, the data in the horizontal transfer register 3 is transferred line by line, and the CCD signal of the first field is output from the output unit 4.

Subsequently, in the line shift transfer period T ₅ of the second field, the signal charges of the even lines are similarly transferred to the horizontal transfer register 3, and the CCD signal of the second field is output from the output section 4. After that, in the surplus charge sweep-out transfer period T ₆ within the vertical blanking period, the surplus charge in the vertical transfer register 2 of the image pickup unit 32 is swept out to the accumulation unit by the surplus charge sweep-out transfer pulse 39.

In the fourth embodiment, all pixels can be read and interlaced scanning (reading) can be performed as in the above example, and a full frame electronic shutter can be realized.
Then, as in the case of FIG. 10, the smear component is reduced, and the period in which the signal charges are stopped in the vertical transfer register 2 is an extremely short period only during the frame shift transfer period (during high-speed transfer). Does not happen. Furthermore, the vertical transfer registers 2 in the two columns of the image pickup unit 32 are replaced by one vertical transfer register 52 in the storage unit 34, whereby the transfer efficiency of the vertical transfer registers 52 in the storage unit 34 can be improved.
The structure can be relatively simplified.

During the line shift transfer period, φI
Although M ₁ , φIM ₂ , φIM _3O , and φIM _3E are fixed to predetermined potentials as shown in the figure, it is also possible to drive the line shift transfer pulse 38.

Further, vertical transfer pulses φST ₁ and φST
₂ is substituted for vertical transfer pulses φIM ₁ and φIM ₂ (φIM
₁ = φST ₁ , φIM ₂ = φST ₂ ).

In the FIT type solid-state image pickup device 31, 41, 51, the electronic shutter may be a system for sweeping out charges to the substrate side or a system for sweeping out charges through the vertical transfer register 2.

As described above, in this embodiment, all pixels can be simultaneously read out and a full frame electronic shutter can be performed with a simple structure, and interlaced reading can be performed. Further, when the FIT type solid-state image pickup device is used, there are practical benefits such as reduction of the difference between the odd and even fields of smear and dark current.

[0107]

According to the driving method of the solid-state image pickup device of the present invention, it is possible to perform the interlaced readout while performing the simultaneous readout of all pixels. Further, the full-frame electronic shutter is enabled, and the image shift does not occur even in the high-speed shutter. Further, according to the solid-state image pickup device of the present invention, it is possible to realize simultaneous read-out of all pixels and interlaced read-out with a relatively simple configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an IT type solid-state imaging device (first embodiment) according to the present invention.

FIG. 2 is an operation explanatory diagram (1) of the first embodiment.

FIG. 3 is an operation explanatory diagram (2) of the first embodiment.

FIG. 4 is an enlarged view of a main part of FIG.

FIG. 5 is a timing chart of drive pulses according to the first embodiment.

6 is an enlarged timing chart of FIG.

FIG. 7 is a configuration diagram and operation explanatory diagram (No. 1) of a FIT type solid-state imaging device (second embodiment) according to the present invention.

FIG. 8 is an operation explanatory diagram (2) of the second embodiment.

FIG. 9 is a timing chart of drive pulses according to the second embodiment.

FIG. 10 is a configuration diagram and operation explanatory diagram of a FIT type solid-state imaging device (third embodiment) according to the present invention.

FIG. 11 is a timing chart of drive pulses according to the third embodiment.

FIG. 12 is a configuration diagram and operation explanatory diagram of a FIT type solid-state imaging device (fourth embodiment) according to the present invention.

FIG. 13 is a timing chart of drive pulses according to the fourth embodiment.

[Explanation of symbols]

1 light receiving part 2 [2A ₁ , 2B ₁ , 2A ₂ , 2B ₂ , 2A ₃ ] vertical transfer register 3 horizontal transfer register 4 output part 5 channel stop area 6, 7, 8 transfer electrode 9 buried channel area 11, 31, 41 , 51 solid-state imaging device 32 imaging unit 33 [33A ₁ , 33B ₁ , 33A ₂ , 33B ₂ , 33
A ₃ ] Vertical transfer register 34 Storage unit 42 [42A ₁ , 42B ₁ , 42A ₂ , 42B ₂ ] Vertical transfer register 43 Control gate unit 52 [52A ₁ , 52B ₁ , 52A ₂ ] Vertical transfer register

Claims (11)

[Claims] 1. A plurality of light-receiving units arranged in a matrix, a first vertical transfer unit arranged between every other column of the light-receiving units, and a space between every other column of the light-receiving units. In a method for driving a solid-state image pickup device, which has a second vertical transfer section arranged in a row and a horizontal transfer section for horizontally transferring the charges from the first and second vertical transfer sections, every other row. The signal charges of the first light receiving unit group are read out to the first vertical transfer unit, and the signal charges of the second light receiving unit group located on the other row are read out to the second vertical transfer unit. A method of driving a characteristic solid-state imaging device. 2. The solid-state imaging device is of FIT type.
7. A method for driving the solid-state image pickup device according to. 3. The method for driving a solid-state imaging device according to claim 1, wherein the signal charges of the first light receiving unit group and the signal charges of the second light receiving unit group are read simultaneously. 4. The signal charge transfer of the second vertical transfer unit is stopped during the signal charge transfer period of the first vertical transfer unit, and the first charge transfer period of the first vertical transfer unit is stopped during the signal charge transfer period of the second vertical transfer unit. The method for driving a solid-state imaging device according to claim 1, 2, or 3, wherein the signal charge transfer of the vertical transfer unit is stopped. 5. The first or second during the horizontal blanking period.
2. The method for driving a solid-state image pickup device according to claim 1, 2, 3 or 4, wherein two vertical bits of the vertical transfer unit are transferred to the horizontal transfer unit. 6. A plurality of light-receiving units arranged in a matrix, a first vertical transfer unit arranged between every other column of the light-receiving units, and a space between every other column of the light-receiving units. In the solid-state imaging device, the solid-state imaging device includes a second vertical transfer unit arranged in a vertical direction, and a horizontal transfer unit that horizontally transfers charges from the first and second vertical transfer units. The read gate section to be read out to the transfer section is provided on the first vertical transfer section side in the light receiving sections located in the odd rows, and on the second vertical transfer section side in the light receiving sections located in the even rows. A characteristic solid-state imaging device. 7. The solid-state imaging device according to claim 6, further comprising a storage unit between the first and second vertical transfer units and the horizontal transfer unit. 8. The storage unit is one of the first and second vertical transfer units.
There is one storage / transfer unit for each column, and the charges of the first and second vertical transfer units are adjacent to each other for each vertical unit bit between the storage unit and the first and second vertical transfer units. The solid-state imaging device according to claim 7, further comprising a control gate that is alternately allocated to the matching storage and transfer unit. 9. The storage unit comprises two of the first and second vertical transfer units.
The solid-state imaging device according to claim 7, wherein each column has one accumulation / transfer unit. 10. The method according to claim 6, wherein the first and second vertical transfer units form one bit by the first, second and third electrodes. Solid-state imaging device. 11. The first and second electrodes are arranged in a horizontal direction, the third electrode is arranged in a vertical direction, and the third electrode is composed of a first vertical transfer section and a second vertical transfer section. The solid-state imaging device according to claim 10, wherein the solid-state imaging device is electrically independent of each other.