JPH0760865B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a non-volatile semiconductor memory device for achieving high integration of memory cells.

[Prior Art] FIG. 4A is a partial plan view showing a conventional N-channel floating gate nonvolatile semiconductor memory device, and FIG. 4B is a plan view of FIG.
FIG. 4 is a sectional view taken along the line IV B-IV B in the figure.

In the figure, above the P-type silicon substrate 10, a control gate made of a conductor layer of polycrystalline silicon or the like is provided with a predetermined gap therebetween so as to extend in a direction indicated by an arrow X with an insulator layer 7 interposed therebetween. 2 is formed. Below the control gate 2, a floating gate 1 also formed of a conductor layer is formed via an insulator layer 7. An N-type impurity diffusion region 3 on the drain side and an N-type impurity diffusion region 4 on the source side are formed in the P-type silicon substrate 10 below the floating gate 1 at intervals. The N-type impurity diffusion region 3 has a biting portion 3a below the floating gate 1, and the N-type impurity diffusion region 4 also has a biting portion 4a. The N-type impurity diffusion region 3 on the drain side is connected to the metal wiring layer 5 made of aluminum or the like via the contact hole 6. The metal wiring layer 5 is orthogonal to the control gate 2 and is formed at predetermined intervals so as to extend in the direction indicated by the arrow Y.

Next, the operation of this floating gate type nonvolatile semiconductor memory device will be described. Here, charging the floating gate 1 with electrons is referred to as “writing”, and discharging the electrons from the floating gate 1 is referred to as “erasing”. First, in "writing", a high voltage is applied to one drain side N-type impurity diffusion region 3 and one control gate 2, and the other N-type impurity diffusion regions 3 and control gates 2 are at "Low" level. It is done by leaving it. Thereby, electrons having high energy generated in the channel region of one memory transistor selected in a matrix form reach the floating gate 1 over the conduction band energy gap of the insulating layer 7 below the floating gate 1. . In this way, "writing" is performed by charging the floating gate 1 with negative charges. on the other hand,
The "erasing" is performed by emitting electrons in the floating gate 1 by irradiation with ultraviolet rays or light having a wavelength close to that of ultraviolet rays. Therefore, the threshold voltage of the memory transistor varies depending on the presence / absence of charges in the floating gate 1. Therefore, "reading" utilizes the fact that the amount of current flowing between the drain and the source changes depending on the difference in threshold voltage, and this amount of current is sense amplifier (not shown) connected to the metal wiring layer 5
It is performed by amplifying and detecting by, and distinguishing the states of "write" and "erase".

By the way, the conventional nonvolatile semiconductor memory device is formed so that two memory transistors are formed for one N-type impurity region 3 on the drain side, as shown in FIG. 4A. This is because the N-type impurity diffusion region 4 on the source side, which is normally set to the substrate potential (ground potential), is shared and the interval between the memory transistors in the direction indicated by the arrow Y is reduced. Further, the distance between the metal wiring layers 5 in the direction indicated by the arrow X is wider than the distance in the Y direction, and there are many regions where only the insulator layer 7 is formed. This is because it is difficult to pattern the metal wiring layer 5 stacked on the uppermost layer. For example, in a non-volatile semiconductor memory device having a capacity of 1 megabit, the minimum technically possible intervals are 1.0 μm between impurity diffusion regions, 1.5 μm between gates, and 2.0 μm between metal wiring layers. is there. As is clear from this, it is necessary to pattern with a wider space as the layers are stacked on the semiconductor substrate. This is because the level difference of the stacked layers increases as the layers are stacked on top. For example, the metal wiring layer 5 has a film thickness of about 2000 to 3000 Å, which is smaller than that of the gate.
Since it is formed as thick as 10000Å, the sagging of the pattern is large, and it is necessary to design the pattern with a particularly large interval.

[Problems to be Solved by the Invention] Since the conventional nonvolatile semiconductor memory device, in particular, the floating gate type nonvolatile semiconductor memory device is configured as described above, the interval between the metal wiring layers formed in the uppermost layer is It was necessary to make it wider. Therefore, no pattern serving as an active region is formed in the region between the metal wiring layers, which is a blank portion, which has been an obstacle to high integration of the nonvolatile semiconductor memory device.

In addition, in the conventional nonvolatile semiconductor memory device, there is a problem that the size of the chip increases with the increase of the memory capacity, resulting in a decrease in yield, and the manufacturing cost increases.

Therefore, the present invention has been made to solve the above-mentioned problems, and it is possible to effectively utilize a blank area between metal wiring layers and easily achieve high integration. It is an object of the present invention to provide a semiconductor memory device capable of achieving the above.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a semiconductor substrate having a main surface and having a predetermined impurity concentration of a certain conductivity type, a first conductor layer, and a second conductor layer. Of the conductor layer, the first floating conductor layer, the second floating conductor layer, and one and the other semiconductor region having a conductivity type opposite to that of the semiconductor substrate. The first conductor layer is formed above the main surface of the semiconductor substrate so as to extend along the first direction and is insulated. The second conductor layer is formed above the main surface of the semiconductor substrate so as to extend along a second direction intersecting the first direction and is insulated. Further, the first floating conductor layer is formed between the semiconductor substrate and the first conductor layer and insulated. The second floating conductor layer is formed between the semiconductor substrate and the second conductor layer and insulated. Further, one and the other semiconductor regions having a conductivity type opposite to that of the semiconductor substrate are formed on the main surface of the semiconductor substrate at intervals below the first floating conductor layer and the second floating conductor layer. Has been done.

[Operation] A semiconductor memory device according to the present invention includes a first conductor layer and a first floating conductor layer extending along a first direction,
It has a 2nd conductor layer and a 2nd floating conductor layer which extend along the 2nd direction which intersects with the 1st direction. Further, under the first floating conductor layer and the second floating conductor layer, a semiconductor region having a conductivity type opposite to that of the semiconductor substrate, which is to be an active region, is formed with a space.
Therefore, the memory element can be formed along two directions in which the first direction and the second direction intersect,
The range of utilizing an area on the semiconductor substrate as an active area is increased. Therefore, a region where a memory element is newly formed is provided, and the semiconductor memory device can be highly integrated.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1A
FIG. 1 is a partial plan view showing an N-channel floating gate type nonvolatile semiconductor memory device according to the present invention, FIG. 1B is a sectional view taken along line IB-IB of FIG. 1A, and FIG. 1C is an IC- of FIG. 1A. It is sectional drawing in IC line.

In the figure, above the P-type silicon substrate 10, control gates 2 made of a conductor layer of polycrystalline silicon or the like are formed at predetermined intervals so as to extend in the direction indicated by the arrow X. There is. Further, the control gates 12 are arranged at predetermined intervals above the control gates 2 via the insulator 7 so as to extend in the direction orthogonal to the direction in which the control gates 2 extend, that is, the direction indicated by the arrow Y. It is formed separately. Below the control gate 2, a floating gate 1 made of a conductive layer such as polycrystalline silicon is formed along the direction indicated by the arrow X with an insulator layer 7 interposed therebetween.
The floating gate 11 is also formed below the control gate 12 with the insulating layer 7 interposed therebetween in the direction indicated by the arrow Y. Further, the P-type silicon substrate 10 below the floating gate 1 is spaced from the N-type impurity diffusion region 3 on the drain side and the N-type impurity diffusion region 3 on the source side.
A type impurity diffusion region 4 is formed. Similarly, below the floating gate 11, N-type impurity diffusion regions 3 and 4 are formed.
Are formed on the P-type silicon substrate 10 at intervals. In this case, the N-type impurity diffusion region 3 on the drain side
Is the biting part 3a under the floating gate 1,
It has a biting part 3b under the floating gate 11. Further, the N-type impurity diffusion region on the source side has a biting part 4 a below the floating gate 1 and a biting part 4 b below the floating gate 11. Further, metal wiring layers 5 made of aluminum or the like are formed at predetermined intervals so as to extend in the direction indicated by the arrow Y so as to be connected to the N-type impurity diffusion region 3 on the drain side via the contact holes 6. Has been done.

Next, the operation of the nonvolatile semiconductor memory device according to the present invention will be described. First, as in the conventional case, the writing and reading of the memory transistor arranged in the direction shown by the arrow X are performed by "Lo" in all parts of the control gate 12.
As described above, since the bite 3b of the N-type impurity diffusion region on the drain side and the bite 4b of the N-type impurity diffusion region on the source side are completely disconnected by applying the voltage of w "level. Thus, it can be performed in the same manner as the conventional method.

The writing and reading of the memory transistors arranged along the direction indicated by the arrow Y are performed by the control gate 2
By applying a "Low" level voltage to all parts of the memory cell, the same operation as in the conventional memory transistor arranged along the direction indicated by arrow X can be performed. That is, a high voltage is applied to one drain-side N-type impurity diffusion region 3 and one control gate 12, and the other drain-side N-type impurity diffusion region 3 and control gate 12 are applied.
By applying a "Low" level voltage to the memory cell, "writing" is performed on one memory transistor selected in a matrix. Similarly to the above, "reading" is performed by selectively applying a low voltage to the drain side N-type impurity diffusion region 3 and the control gate 12. Furthermore, the "erasure" can be performed without any change from the conventional method.

Although the floating gates 1 and 11 are rectangular in plan view in the above embodiment, the contact holes 6 for connecting the N-type impurity diffusion region 3 on the drain side and the metal wiring layer 5 are formed. If the area can be reduced, it may be formed as shown in FIG. That is, referring to FIG. 2, the corners, which are the regions where the floating gates 1 and 11 are adjacent to each other and have the smallest interval,
Alternatively, a floating gate having a shape cut off at an angle of 45 ° with the direction indicated by Y may be formed. Even if the floating gate is formed in this manner, the same effect as that of the above-described embodiment can be obtained, and higher integration can be achieved.

FIG. 3A is a partial plan view showing another embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 3B is a sectional view taken along line IIIB-IIIB in FIG. 3A. With reference to these figures, a part of the insulator layer 7 formed between the floating gates 1 and 11 and the N-type impurity diffusion region 3 on the drain side is thin so that the film thickness is several tens of liters. Has been formed. in this way,
By reducing the thickness of the insulator layer formed between the bite part 3a (or 3b) of the drain side N-type impurity diffusion region and the floating gate 1 (or 11) formed thereabove. , And the injection of electrons may be performed by causing a tunnel effect by an electric operation performed during that time. As described above, the semiconductor memory device according to the present invention has the EPROM (Erasa) of the above-described embodiment.
ble Programmable Read Only Memory)
As shown in FIGS. 3A and 3B, the EEPROM (Electric
ally Erasable and Programable Read Only Memo
ry).

Further, in the above embodiment, the control gate
Although 12 is shown formed above control gate 2, it goes without saying that it may be formed below control gate 2. Further, although the P-type silicon substrate is used in the above-described embodiment, an N-type silicon substrate may be used to configure a semiconductor memory device of the opposite conductivity type.

As described above, according to the present invention, the first conductor layer and the first floating conductor layer extending along the first direction above the semiconductor substrate intersect with the first direction. Since the semiconductor memory device is configured to have the second conductor layer and the second floating conductor layer extending along the second direction, the semiconductor memory element is formed along the two intersecting directions. Can be done.
Therefore, the area of the region to be the active region on the semiconductor substrate can be increased, and higher integration (about 10 to 50%) can be achieved as compared with the conventional case. Therefore, it is possible to configure a semiconductor memory device having a larger memory capacity with the same chip size, and it is possible to reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1A is a partial plan view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along line IB-IB of FIG. 1A, and FIG. 1C is an IC-IC line of FIG. 1A. FIG. FIG. 2 is a partial plan view showing a nonvolatile semiconductor memory device according to another embodiment of the present invention. FIG. 3A is a partial plan view showing an EEPROM which is a nonvolatile semiconductor memory device according to yet another embodiment of the present invention, and FIG.
FIG. 3B is a sectional view taken along line IIIB-IIIB in FIG. 3A. FIG. 4A is a partial plan view showing a conventional nonvolatile semiconductor memory device, and FIG.
The drawing is a cross-sectional view taken along the line IV B-IV B in FIG. 4A. In the figure, 1 and 11 are floating gates, 2 and 12 are control gates, 3 and 4 are N-type impurity diffusion regions, and 10 is a P-type silicon substrate. In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor substrate having a main surface and having a predetermined impurity concentration of a certain conductivity type; and a semiconductor substrate formed above the main surface of the semiconductor substrate so as to extend along a first direction and insulated. A first conductor layer, and a second conductor layer which is formed above the main surface of the semiconductor substrate so as to extend along a second direction intersecting the first direction and is insulated. A first floating conductor layer is formed between the semiconductor substrate and the first conductor layer and is insulated, and a first floating conductor layer is formed between the semiconductor substrate and the second conductor layer, and is insulated. A second floating conductor layer, and the semiconductor substrate formed on the main surface of the semiconductor substrate at a distance below the first floating conductor layer and the second floating conductor layer. Storage device having one and the other semiconductor regions having conductivity types opposite to those of