JPH0766411A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] The channel formation layer 11 is formed in the SOI film 103.
4, a p @ + diffusion region 110 is formed, and a substrate contact 111 is connected to this region 110. Board 10
P + diffusion region 112 at the boundary with the first insulating film 102.
This region 112 is provided immediately below a region where the tip of the gate electrode 106 and the p + diffusion region 110 for absorbing holes overlap. Then, when a negative voltage is applied from the contact 113, the potential for holes in the overlap portion OL decreases, and the energy barrier E
B (broken line in FIG. 1C) is erased, and the channel formation layer 1
The holes generated by impact ionization in 14 can be guided to the region 110. [Effect] The drain breakdown voltage rises and the power supply level of the thin film FET rises.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention improves the performance of a semiconductor device using an SOI structure as a substrate, and more specifically, a single crystal silicon thin film on an insulating film (hereinafter referred to as SOI (Silicon-On-Insulator)).
The present invention relates to a technology for improving the performance of the MOS transistor formed in the above.

[0002]

2. Description of the Related Art It is well known that forming a MOSFET on an SOI film is effective in reducing stray capacitance and radiation resistance. Recently, in particular, when the film thickness (typically about 1000 angstroms) at which the SOI film is entirely depleted (hereinafter, this structure is referred to as a thin film SOI device),
1) Reduction of short channel effect, 2) increase of carrier mobility, 3) improvement of subthreshold characteristics, 4) reduction of instability during switching, and many other advantages of realizing high-speed and fine devices. Has been reported (M.Yos
himi et al., IEEE, vol.ED-36, no.3, p.493,1989, etc.).

However, in the conventional thin film SOI device, it is known that the drain current rapidly increases with the increase of the drain voltage, that is, so-called drain breakdown easily occurs, which is a great obstacle to practical use. (M.Yos
himi et al., IEEE, vol.ED-37, no.9, p.2015,1990, etc.).

FIG. 13 shows an n-type MOSF of this type of semiconductor device.
The structure of ET is shown. In this figure, B01
Is a silicon substrate, and SiO ₂ is formed on the substrate B01.
The SOI film B03 is formed through the insulating film B02 made of. A gate oxide film B is formed on the SOI film B03.
04 through the gate electrode B05, the SOI film B
The region immediately below the gate electrode B05 in 03 becomes the channel formation region B06. An n + type source diffusion layer region B07 and an n + type drain diffusion layer region B08 are formed on each side of the channel forming region B06.

The cause of the decrease in drain breakdown voltage is that the channel formation region B06 of the SOI film B03 is in an electrically floating state. Channel forming region B06
Are in an electrically floating state, as the drain voltage increases, the electrons that gain energy in the channel cause impact ionization in the vicinity of the drain diffusion layer region B08, and the resulting holes are generated in the channel formation region B06. After the accumulation, the potential of the channel is raised, excess electrons are injected from the source, and excess drain current flows as shown in FIG. B09 is holes accumulated on the source side.

FIG. 15 shows the structure of a conventional MOSFET having the most typical countermeasures. In this figure, C01 is an n-type silicon substrate, C02 is an insulating film, and C0.
3 is an SOI film, C04 is an element isolation oxide film, C05 is a gate oxide film, C06 is a gate electrode, C07 is a gate interlayer contact, C08 is a source diffusion layer region, C09 is a drain diffusion layer region, and C12 is a channel formation region. is there.

A channel forming region C1 is formed in the SOI film C03.
2 and a p + diffusion layer region C10 is formed adjacent to
An interlayer contact C11 called a substrate contact is connected to the + diffusion layer region C10.

With this structure, holes generated in the drain diffusion layer region C09 are absorbed from the contact C11 to stabilize the potential in the channel forming region C12.

This method was certainly effective for an early SOI device or an SOS (Silicon-On-Sapphire) structure whose SOI is typically thicker than 5000 angstroms. That is, the holes generated near the drain are efficiently collected at the substrate contact through the central region formed in the deep region of the thick SOI film, and as a result,
The potential of the film immediately below the channel formed in the channel formation region C12 was stable, and the drain breakdown voltage was improved.

The layout of the p + diffusion layer region for absorbing holes is not limited to the above example, and the structure shown in FIG. 16 is also conceivable. In this figure, D01 is a gate electrode, D02 is a gate contact, D03 is an n + source diffusion layer region, D
Reference numeral 04 denotes an n + drain diffusion layer region, where a p + diffusion layer region D05 for absorbing holes is formed on the source side with the gate electrode D01 as a boundary.

[0011]

However, as a result of experiments or simulations conducted by the present inventors, such a conventional improvement method is not effective for a thin film SOI structure as described below, and the drain breakdown voltage is , It was found that providing a substrate contact does not improve in the practical area.

In the experiment, S having a film thickness of 500 angstrom
Thin film SOI with a channel length of 0.5 μm formed on the OI film
The current-voltage characteristics of the device were measured. FIG. 17 shows the result, and the solid line in the figure shows the current-voltage characteristic in the normal structure without using the substrate contact, and the broken line shows the current-voltage characteristic in the structure using the substrate contact.

As shown in this figure, when the substrate contact is provided, the drain breakdown voltage is improved when the gate voltage is equal to or higher than the threshold voltage (gate voltage = 1 V and 2 V in the figure). You can see that not. Considering the actual circuit operation, it is obvious that the latter is important, and it was found that the conventional measures do not bring about effective improvement.

Therefore, although the thin film SOI device structure has an advantage of fine and high-speed operation, it has a disadvantage of low drain breakdown voltage, so that the range of usable power supply voltage is remarkably limited. It was not always possible to withdraw.

The present invention has been made in view of the above-mentioned problems of the prior art, and the object thereof is a thin film SO.
By improving the drain breakdown voltage of the I element, the usable power supply voltage range of the element is expanded, and the thin film SOI
It is to maximize the performance of the device.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device in which a semiconductor film is formed on a semiconductor supporting substrate via an underlying insulating film, and the dielectric constant of the semiconductor film is ε _Si , When the difference between the Fermi energy of this semiconductor film and the intrinsic Fermi energy is φ _F , the electron charge is q, and the impurity concentration of the semiconductor film is N _SUB , the thickness of this semiconductor film is 2 [ε _Si · φ _F / q · N _SUB ] ^1/2 or less, a semiconductor substrate having an SOI structure, a source region formed of a high-concentration impurity diffusion region of the first conductivity type formed in the semiconductor film, and the semiconductor film A drain region formed of the high-concentration impurity diffusion region of the first conductivity type formed at a predetermined distance from the source region;
A gate electrode formed through a gate insulating film on a second conductivity type channel forming region sandwiched between the source region and the drain region of the semiconductor film and adjacent to the channel forming region of the semiconductor film. And a channel extraction region which is formed so as to partially overlap with the gate electrode and which is a high-concentration impurity diffusion region of the second conductivity type, which attracts unnecessary carriers of the second conductivity type, and the semiconductor support substrate. Of the second-conductivity-type high-concentration impurity diffusion region formed immediately below the region where the gate electrode and the channel extraction region overlap each other, and controls the potential of the overlap region in the semiconductor film. By doing so, unnecessary carriers for guiding unnecessary carriers of the second conductivity type generated in the channel formation region to the channel extraction region are formed. Characterized in that it comprises a rear guiding area.

According to a second aspect of the present invention, in a semiconductor device, a semiconductor film is formed on a semiconductor supporting substrate through an underlying insulating film, and the dielectric constant of the semiconductor film is ε _Si , and the Fermi energy and the intrinsic property of the semiconductor film. The difference from the Fermi energy is φ _F , the electronic charge is q, and the impurity concentration of the semiconductor film is N.
_{When SUB} is formed, the semiconductor film having an SOI structure is formed so that the thickness of the semiconductor film is 2 [ε _Si · φ _F / q · N _SUB ] ^1/2 or less, and the semiconductor film is formed on the semiconductor film. A source region formed of a first-conductivity-type high-concentration impurity diffusion region; and a drain region formed of the first-conductivity-type high-concentration impurity diffusion region formed in the semiconductor film at a predetermined distance from the source region,
A gate electrode formed through a gate insulating film on a second conductivity type channel forming region sandwiched between the source region and the drain region of the semiconductor film and adjacent to the channel forming region of the semiconductor film. And a channel lead-out region for absorbing the second-conductivity-type carriers, which is formed of the second-conductivity-type high-concentration impurity diffusion region formed so as to partially overlap with the gate electrode, and in the semiconductor film. The second conductivity type high-concentration impurity diffusion region is formed so as to overlap a part of the channel formation region, and provides a passage to the channel extraction region for the second conductivity type carriers. As a result, an unnecessary carrier guiding region for guiding the unnecessary carriers of the second conductivity type generated in the channel forming region to the channel extraction region is provided. It is characterized by a door.

[0018]

First, the inventor of the present invention three-dimensionally explains the reason why the drain breakdown voltage is not improved in the conventional countermeasures shown in FIGS. Detailed analysis was performed by simulation. As a result, under the condition of low gate voltage, the holes generated in the drain can be effectively absorbed, but when the gate voltage is high, the potential of the extraction portion from the channel is pulled up by the gate electrode and rises to a positive value. It has been clarified that this is because the energy barrier to the holes is formed. FIG. 15C shows the potential of the channel formation region C12 for holes when the gate voltage (V _g ) is lower and higher than the threshold value (V _TH ). When the gate voltage is high, a barrier EB that prevents the diffusion of holes is formed in the SOI film in the p @ + diffusion layer region C10 overlapping the gate electrode C06.

The essence of the present invention is to eliminate or reduce the energy barrier that prevents the diffusion of holes.

Therefore, in the semiconductor device according to the first aspect, a bias for lowering the potential is applied to the holes from the semiconductor supporting substrate through the base insulating film. This bias is limited to the overlap region OL between the gate electrode and the channel lead portion. If this bias is applied to the channel formation region, the threshold value of the transistor will change, hindering the normal operation of the circuit.

FIG. 6 shows a channel length of 0.5 μ according to this structure.
The current-voltage characteristic of the element of m is shown. The drain breakdown voltage is
Even in the region where the gate voltage is high, the voltage rises by 1.5 V or more.

In the SOI structure, applying a bias to a part of the substrate to change the potential of the SOI film is already known as a method of changing the threshold value of the transistor. However, the present invention is novel in that the bias is applied only to the overlapping region of the substrate contact and the gate electrode, the bias applying configuration is completely different from the conventional method, and the bias is applied from the channel forming region. The fact that a hole barrier is formed in the overlap region between the extraction region and the gate electrode is a finding first found by the inventor of the present invention, and cannot be easily predicted from the conventional method.

In a semiconductor device according to a second aspect of the present invention, a high concentration impurity region is formed in a channel forming region which is in contact with a source region to provide a region which is not subject to modulation by a gate bias. By connecting the channel extraction region with the channel extraction region, holes are efficiently extracted to the substrate electrode, and the drain breakdown voltage is improved.

Further, by using the present invention, it becomes possible to prevent a decrease in current driving force. That is, in the structure in which the impurity concentration is simply increased over the entire channel,
The current driving force is significantly reduced due to the influence of impurity scattering, and the merit of the thin film SOI device disappears. According to the present invention, since only the channel portion near the source has a high concentration, it is possible to prevent the current driving force from decreasing.

FIG. 12 shows a channel length of 0.5 according to this structure.
The current-voltage characteristic of a μm element is shown. The drain breakdown voltage is
Even in the region where the gate voltage is high, the voltage rises by 1.5 V or more, and the improvement effect of the present invention can be confirmed.

[0026]

FIG. 1 is a MOSFET according to an embodiment of the present invention.
FIG. 2 (a) is a plan view and FIG.
Is a cross-sectional view taken along the line S1-S1 ', and FIG. 7C is a potential distribution diagram for holes in the SOI film 103.

In this figure, 101 is a silicon supporting substrate, and an SOI film 103 is formed on this substrate 101 via a base insulating film 102 made of SiO ₂ . The SOI film 103 has a dielectric constant of ε _Si , a difference between the Fermi energy of the semiconductor film and an intrinsic Fermi energy of φ _F , an electronic charge of q, and an impurity concentration of the semiconductor film of N.
_When it is set to _SUB , it is formed to be thinner than 2 [ε _Si · φ _F / q · N _SUB ] ^1/2 . An element isolation oxide film 104 is formed on the SOI film 103 to a depth where it is connected to the insulating film 102. A gate oxide film 105 is formed on a region of the SOI film 103 surrounded by an element isolation oxide film 104, and a gate electrode 106 is formed on the gate oxide film 105. Gate electrode 1 in SOI film 103
The region immediately below 06 serves as a channel forming layer 114, 107 is a gate contact, and 108 and 109 are M type source / drain regions 10.

A channel forming layer 114 is formed on the SOI film 103.
A p + diffusion region 110 is formed adjacent to, and a contact 111 called a substrate contact is connected to this p + diffusion region 110. Insulating film 1 on substrate 101
A p @ + diffusion region 112 is formed at the boundary with 02. The p + diffusion region 112 extends from a region immediately below the end of the channel region between the source and drain to a region immediately below the electric field between the p + diffusion region 110 for absorbing holes and the channel forming layer 114. Here, the p + diffusion region 11
2 may extend to the lower part of the p + diffusion region 110 so as to overlap therewith. Further, it is preferable that the p + diffusion region 112 is formed at least over the entire width direction (source / drain direction) of the p + diffusion region 110 and the channel forming layer 114. Reference numeral 113 is a contact connected to the extension end of the p + diffusion region 112.

In the above structure, the potential for holes is lowered by applying a negative voltage to the electrode 113, the energy barrier EB is erased as shown by the solid line in FIG. 1C, and the channel forming layer is formed. P + diffusion region 110 of holes generated by impact ionization in 114
Will be able to lead to. As described above, as shown in FIG. 6, the drain breakdown voltage increases by 1.5 V or more even in the region where the gate voltage is high.

In the above structure, the p + diffusion region 11
2 may be formed over the entire interface between the substrate 101 and the base insulating film 102. A negative voltage may be applied to this. In this case, n + diffusion cool air may be used. Further, in the case of p-channel, the relationship of the above-mentioned conductivity types is reversed.

2 to 5 show a process for obtaining the structure shown in FIG.

First, oxygen ions are ^{added to} an N-type (100) silicon substrate 200 having an impurity concentration of 4 × 10 ¹⁵ cm ^-3 to 20 times.
Implantation is performed at a accelerating voltage of 0 kV and a dose amount of 4 × 10 ¹⁷ cm ^-2 , and then annealed at 1350 ° C. for 6 hours to a depth of 0.35 μm from the surface of the silicon substrate 200, and a buried oxide having a thickness of 800 Å. Membrane 201
Then, the SOI film 202 is formed. Then, as shown in FIG. 2, the SOI film 202 is oxidized by thermal oxidation and ammonium fluoride, respectively, and etched to form a 1000 angstrom SOI on the surface of the substrate 200.
The film 103 is formed. Then, a well-known selective oxidation method was used to form an isolation oxide film 104 in a region other than the element region.
Next, a resist film 203 is applied on the entire surface, and SOI is partially applied.
A hole 204 is formed to expose the surface of the film 103, and boron (B) ions are accelerated at a voltage of 100 kV and a dose of 3 ×.
The SOI film 103 is formed through the hole 204 at 10 ¹⁵ cm ^-2.
Then, the p-type region 112 is formed in a part of the supporting substrate 101 by penetrating the underlying insulating film 102 and injecting it into the supporting substrate 101. : FIG. 3 Next, after removing the resist film 203, the SOI film 10
3 is thermally oxidized to form a gate oxide film 105 having a thickness of 100 angstrom on the surface. Next, a 3000 angstrom thick polysilicon film is deposited by a CVD method, phosphorus-doped, and a gate electrode 106 is formed by a well-known patterning method. Then, arsenic is added to the accelerating voltage 40
kV, ion implantation at a dose of 2 × 10 ¹⁵ cm ^-2 , 9
The source region 205 and the drain region 206 are formed by annealing at 00 ° C. for 30 minutes. At this time, the p-type region 1
Also in the transistor on the 10 side, n is perpendicular to the paper surface.
The source and drain of the mold are formed. Here, the substrate contact portion is covered with a resist mask during ion implantation. Further, the resist mask was removed, the source / drain was covered with another resist mask, and boron was implanted into the substrate contact portion at 40 kV and 2 × 10 ¹⁵ cm ⁻² to form the p-type region 110. : FIG. 4 Next, a CVDSiO ₂ film (not shown) is deposited, contact holes are opened, and aluminum wirings 106a, 108, 1 are formed.
After forming 09 and 111 and depositing a passivation film, this device was completed. At this time, the contact hole is
It is possible to use holes having two kinds of depths, a hole reaching the source / drain and a hole reaching the p-type diffusion layer of the silicon substrate. 5: FIG. 7 shows the structure of a MOSFET according to a second embodiment of the present invention.

In this figure, 701 is a gate electrode, and 7
Reference numeral 02 denotes a gate contact, which is a channel forming region 707 immediately below the gate electrode 701 in the SOI film.
N is formed on each side of the channel formation region 707 in the SOI film.
A source region 703 and a drain region 704 of the mold are formed.

In the SOI film, a p + type diffusion region 708 is formed adjacent to the channel forming region 707 and partially overlapping with the gate electrode 701 for the purpose of contacting the substrate for further extracting holes. Has been formed. 705
Is the substrate contact (p + type).

In the SOI film, the gate electrode 701
A p @ + diffusion region 706 is formed in a region where the channel extraction region 708 and the channel extraction region 708 overlap each other. The conductivity type of the diffusion region 706 may be the same as the conductivity type of the channel region, and when the channel region is n-type, it is n + type. It is preferable that the concentration be between the impurity concentration of the channel and the impurity concentration of the source / drain.

With such a structure, the diffusion region 706 provides a path for holes to the diffusion region 708 without being modulated by the gate bias, so that the positive region generated in the channel formation region 707 is generated. Hole diffusion area 7
08, so that the channel formation layer 7 functions.
P + of holes generated by impact ionization in 07
The guidance to the diffusion region 708 can be achieved. In particular, it is effective that the diffusion region 7016 partially overlaps the channel region. As described above, as shown in FIG. 12, the drain breakdown voltage rises by 1.5 V or more even in the region where the gate voltage is high.

Here, in the diffusion region 708,
In order to secure the passage of holes, the diffusion region 706 is partially present in the width direction of the diffusion region 708 (the direction connecting the source region 703 and the drain region 704).
In particular, it is preferable that the source be knitted and provided.

8 to 10 show a manufacturing process of the MOSFET shown in FIG.

First, the impurity brain and 1 × 10 ¹⁵ cm ^-3 p-type 1
For example, oxygen ions are implanted into a single crystal silicon substrate 800 of 00 at an acceleration voltage of 150 keV and a dose amount of 4 × 10 ¹⁷ cm ^-2 , and an insulating film 802 made of SiO ₂ having a thickness of 500 Å is formed by annealing at 1300 ° C. for 6 hours. An SOI film 803 having a thickness of 2000 Å is formed. Next, an oxide film (not shown) is formed on the surface of the SOI film 803 with a thickness of 2000 angstrom by the hydrogen combustion oxidation method, and then the oxide film is removed with an ammonium fluoride aqueous solution. At this stage, the film thickness on the surface of the SOI film 803 is 1
Thinned to 000 angstroms. Next, as shown in FIG. 8, an SOI film 804 which serves as an element active region is formed by a reactive ion etching method using a resist (not shown) as a mask. After that, the resist is removed. After that, using a resist (not shown) as a mask, B is partially formed in a part of a predetermined region of the SOI film 804 as a channel formation region.
F ₂ ions are accelerated at an acceleration voltage of 30 keV and a dose amount of 3 × 10 ¹³
The p + diffusion region 706 is formed by implanting at cm ⁻² . Then, this resist is removed. Next, a gate oxide film (not shown) is formed with a film thickness of 100 angstroms, and a phosphorus diffusion type polycrystalline silicon film to be a gate electrode is subsequently formed with a thickness of 2000 angstroms. FIG. 10: Then, after patterning the polycrystalline silicon film using the resist as a mask, an ion implantation method is used to form a source region 703 and a drain region 704 of N-type impurities (arsenic).
And the resist is subsequently removed. Thereafter, similarly, using the resist as a mask, the substrate electrode region 705 of p-type impurities (boron) is formed by using the ion implantation method. After that, a contact hole and aluminum wiring are formed by using a normal MOS transistor manufacturing method, and M
The OS transistor will be completed. 7A and 7B show the main manufacturing process of the semiconductor device according to the third embodiment of the present invention. FIG. 7A is a plan view and FIG. 11B is a cross section taken along line S3-S3 '. Figure, (c) of the figure is S
FIG. 4 is a sectional view taken along line 4-S4 ′. In this embodiment, the step of forming the p + diffusion region A13 after forming the gate electrode is in the reverse order of the second embodiment.

Here, the p + diffusion region A13 is formed as follows. Gate electrode A05 and source region A0
9. After forming the drain region A08, the resist film A1
1 is used as a mask and the BF ₂ ion is accelerated at an angle of 45 ° with respect to the vertical direction of the gate electrode A05 at an acceleration voltage of 60 ke
Implant with V and dose of 1 × 10 ¹⁴ cm ⁻² . As a result, the p + diffusion region A13 is formed.

The present invention is not limited to the above-described embodiments, but various modifications can be made without departing from the scope of the invention. For example, the MOS transistor formed in the SOI film is not limited to the n channel and may be the p channel. Channel drawer 1 for p-channel
In this case, the region is n-type, and in this case, unnecessary carriers (electrons) accumulated in the channel can be extracted.

Further, the manufacturing process can be appropriately changed according to the specifications.

Further, the high-concentration impurity diffusion region which is in contact with the source region may be present over the entire direction perpendicular to the gate electrode. Further, the peak of the concentration distribution in the depth direction of the high concentration region is preferably closer to the back surface than the front surface of the SOI film.

[0044]

As described above, according to the present invention, in the thin film SOI device structure, a high drain breakdown voltage can be maintained even in an actual operating region, and as a result, the usable operating voltage range can be greatly increased. Can be improved to thin film SOI
It is possible to bring out the high performance of the device.

[Brief description of drawings]

FIG. 1 is a plan view ((a)) showing a configuration of a MOS transistor formed on an SOI structure substrate according to a first embodiment of the present invention, a sectional view taken along the line S1-S1 ′, and an inside of an SOI film. Potential distribution map for holes.

2 is an element cross-sectional view in a first step of the manufacturing process of the MOS transistor shown in FIG.

FIG. 3 is an element sectional view in a second step of the manufacturing process of the MOS transistor shown in FIG.

4 is an element sectional view in a third step of the manufacturing process of the MOS transistor shown in FIG.

5 is an element cross-sectional view in a fourth step of the manufacturing process of the MOS transistor shown in FIG.

6 is a data curve diagram showing the drain breakdown voltage characteristics of the MOS transistor shown in FIG. 1 in comparison with those of a conventional element.

FIG. 7 is a plan view showing the structure of a MOS transistor formed on an SOI structure substrate according to a second embodiment of the present invention.

8 is an element cross-sectional view in a first step of the manufacturing process of the MOS transistor shown in FIG.

9 is a plan view ((a)) and S2-S2 in a second step of the manufacturing process of the MOS transistor shown in FIG.
′ Line sectional view ((b)).

FIG. 10 is a plan view of a third step of the manufacturing process of the MOS transistor shown in FIG.

FIG. 11 is a plan view ((a)) showing the configuration of a MOS transistor formed on an SOI structure substrate according to the third embodiment of the present invention and the main steps of the manufacturing process (S3—S3 ′);
A line sectional view and the same S4-S4 'line sectional view.

FIG. 12 is a data curve diagram showing the drain breakdown voltage characteristics of the MOS transistors shown in FIGS. 7 and 11 in comparison with those of a conventional element.

FIG. 13 is a cross-sectional view showing a configuration of a MOS transistor formed on a conventional SOI structure substrate having no substrate contact.

14 is a data curve diagram showing drain breakdown voltage characteristics of the MOS transistor shown in FIG.

FIG. 15 is a plan view ((a)) showing a structure of a MOS transistor formed on an SOI structure substrate having a conventional substrate contact, a sectional view taken along the line S5-S5 ′ of FIG. 15, and showing holes for holes in the SOI film. Potential distribution map.

FIG. 16 is a plan view showing the configuration of another example of a MOS transistor formed on an SOI structure substrate having a conventional substrate contact.

FIG. 17 is a data curve diagram showing drain breakdown voltage characteristics of the MOS transistor shown in FIG.

[Explanation of symbols]

 101 Silicon Support Substrate 102 Base Insulating Film 103 SOI Film 104 Element Isolation Oxide Film 105 Gate Oxide Film 106 Gate Electrode 107 Gate Contact 108 Source Contact 109 Drain Contact 110 Hole Extraction p + Diffusion Region 111 Hole Extraction Substrate Contact 112 Potential Control p + diffusion region 113 Potential control substrate contact 114 Channel formation region EB Energy barrier OL Overlap region 701 Gate electrode 702 Gate contact 703 n + Source diffusion region 704 n + Drain diffusion region 705 Substrate contact p + diffusion region 706 P + diffusion region for hole induction 707 channel stopper formation region 708 p + diffusion region for hole extraction A01 silicon supporting substrate A02 base insulating film A03 SOI film A Fourth gate oxide film A05 gate electrode A06 gate contact A07 channel formation region A08 n + drain diffusion region A09 n + source diffusion region A10 hole extraction for p + diffusion region

Claims (2)

[Claims] 1. A semiconductor film is formed on a semiconductor supporting substrate via a base insulating film, the dielectric constant of the semiconductor film is ε _Si , and the difference between the Fermi energy of the semiconductor film and the intrinsic Fermi energy is φ _F , An SOI formed such that the thickness of the semiconductor film is 2 [ε _Si · φ _F / q · N _SUB ] ^1/2 or less, where q is the electronic charge and N _SUB is the impurity concentration of the semiconductor film. A semiconductor substrate having a structure, a source region formed of a high-concentration impurity diffusion region of a first conductivity type formed in the semiconductor film, and a first conductivity type formed in the semiconductor film at a predetermined distance from the source region. A drain region formed of a high-concentration impurity diffusion region, a gate electrode formed on a channel forming region of the semiconductor film sandwiched between the source region and the drain region via a gate insulating film, and Channel shape A channel lead-out region that is adjacent to the region and is formed of the second-conductivity-type high-concentration impurity diffusion region formed so as to partially overlap the gate electrode, and that attracts the second-conductivity-type unnecessary carriers; The second conductive type high-concentration impurity diffusion region is formed in the semiconductor supporting substrate immediately below a region where the gate electrode and the channel extraction region overlap, and the overlap region in the semiconductor film is formed. And a unnecessary carrier induction region for guiding the unnecessary carriers of the second conductivity type generated in the channel formation region to the channel extraction region by controlling the potential of the semiconductor device. 2. A semiconductor film is formed on a semiconductor supporting substrate via an underlying insulating film, the dielectric constant of the semiconductor film is ε _Si , the difference between the Fermi energy of the semiconductor film and the intrinsic Fermi energy is φ _F , An SOI formed such that the thickness of the semiconductor film is 2 [ε _Si · φ _F / q · N _SUB ] ^1/2 or less, where q is the electronic charge and N _SUB is the impurity concentration of the semiconductor film. A semiconductor substrate having a structure, a source region formed of a high-concentration impurity diffusion region of a first conductivity type formed in the semiconductor film, and a first conductivity type formed in the semiconductor film at a predetermined distance from the source region. A drain region formed of a high-concentration impurity diffusion region, a gate electrode formed on a channel forming region of the semiconductor film sandwiched between the source region and the drain region via a gate insulating film, and Channel shape A channel lead-out region that is adjacent to the region and that is formed so as to partially overlap the gate electrode and that is of the second-conductivity-type high-concentration impurity diffusion region, and that attracts the second-conductivity-type carrier; The second conductive type high-concentration impurity diffusion region is formed in the semiconductor film so as to overlap a part of the channel forming region, and the second conductive type carrier is extended to the channel extraction region. A semiconductor device comprising: an unnecessary carrier guiding region that guides the second conductive type unnecessary carriers generated in the channel forming region to the channel drawing region by providing a passage.