JPH0775066A - Picture signal converter - Google Patents

Abstract

PURPOSE:To realize the up-convert of an SD signal to an HD signal with high resolution. CONSTITUTION:The SD signal inputted from an input terminal 31 is supplied to a blocking circuit 32, and the data in block units are extracted from the SD picture, and supplied to an ADRC circuit 33 and a prediction arithmetic circuit 35. The ADRC circuit 33 requantizes the data in block units, and supplies a signal to a class code generating circuit 34. Then, a class code is generated from the supplied signal, the prediction coefficient of the class is read from a prediction coefficient memory 5, an arithmetic operation according to a prediction expression is performed from the data in block units supplied from the blocking circuit 32 and the prediction coefficient by the prediction arithmetic circuit 35, and estimated HD data are outputted from an output terminal 36.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an input standard resolution (hereinafter referred to as SD) when converting an image signal.
The present invention relates to a signal conversion device that up-converts a signal into a high resolution (hereinafter, referred to as HD) signal.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing an example of a conventional signal conversion device for up-converting. Input terminal 5
The SD signal input from 0 doubles the number of pixels in the horizontal direction by the horizontal interpolation filter 51, doubles the number of lines in the vertical direction by the vertical interpolation filter 52, and is output as an HD signal from the output terminal 53. It That is, the image is up-converted using the filter.

FIG. 9 shows a configuration example of the interpolation filter.
By the multiplier on the signal supplied from the input terminal 54, the filter coefficients α _n, α _n-1, multiplied by ‥‥ alpha _0, the unit delay amount T
The register is sequentially delayed and added, and the interpolated output is output from the output terminal 55. Horizontal interpolation filter 5
In 1, the unit delay amount T is selected as the sampling period, and in the vertical interpolation filter 52, this is selected as the line period.

[0004]

In the above-mentioned conventional image signal converting apparatus, when the SD signal is up-converted into the HD signal by using the filter, the output signal is merely an interpolated signal and the resolution is It is no different from the input SD signal.

Therefore, an object of the present invention is to obtain and identify a prediction coefficient of a prediction equation by learning from a known HD signal rather than simply interpolating, and use this prediction coefficient to convert an SD signal to an HD signal. An object of the present invention is to provide an image signal conversion device capable of up-conversion.

[0006]

According to the present invention, in order to solve the above-mentioned problems, learning using an SD signal generated from a known HD signal is performed, and a block S is formed.
The prediction coefficient of the prediction formula from the SD signal to the HD signal is stored in advance in the memory for each class divided by the pattern of the level distribution of the D signal.

When an SD signal is up-converted to an HD signal, a class is specified from an SD signal level distribution pattern in a block for an arbitrary SD signal, and a prediction coefficient is read from a memory for prediction of the class. It is characterized in that it comprises means for performing an operation based on an equation and outputting an optimum estimated value.

[0008]

Since the HD signal corresponding to the SD signal is determined by learning, up-conversion can be performed based on the nature of the actual image. Moreover, since the class is adaptively selected according to the level distribution of the SD signal, it is possible to perform up-conversion that follows the local property of the image. Therefore, as compared with the interpolation by the filter, an HD signal having a higher resolution image quality can be obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration at the time of learning according to an embodiment of the present invention. Reference numeral 1 is an input terminal for inputting a large number of standard still images of HD signals, and a vertical thinning filter 2
And to the learning unit 4. The vertical thinning filter 2 supplied with the HD image from the input terminal 1 vertically thins the HD image into 1/2. The horizontal decimation filter 3 is connected to the vertical decimation filter 2 to horizontally decimate to 1/2, and a still image of pixels equivalent to the SD signal is supplied to the learning unit 4. The prediction coefficient memory 5 stores the class code created by the learning unit 4 and the coefficients w1 to wn.

In this embodiment, as learning data, a 1/4 average image is created as an SD image corresponding to a known HD image as shown in FIG. Also in this case,
A method of using the weighted average of HD images as SD images in a slightly wider range is also conceivable.

As shown in FIG. 2, when SD pixel (3 × 3) blocks are used, SD pixels a to i and HD pixel A,
B, C, and D are a set of learning data. There are a plurality of sets of learning data for one frame, and a very large number of sets of learning data can be used by increasing the number of frames.

FIG. 3 is a flow chart showing the operation of the learning unit 4 when it has a software processing configuration. The control of the learning unit is started from step 11, and in the corresponding data block formation of step 12, the HD signal and the SD signal are supplied, and the processing of extracting the HD pixel and the SD pixel having the arrangement relationship as shown in FIG. 2 is performed. Step 1
At the end of the data of 3, if the processing of all the input data, for example, the data of one frame is completed, the control is moved to the prediction coefficient determination of step 16, and if not, the control is moved to the class determination of step 14.

In the class determination in step 14, the class is determined from the signal pattern of the SD signal. In this control, adaptive dynamic range coding (hereinafter referred to as ADRC), which will be described later, can be used to reduce the number of bits. In the normal equation addition in step 15, equations 7, 8 and 9 described later are created.

After the processing of all the data is completed from the end of the data in step 13, control is transferred to step 16, and step 1
In the prediction coefficient determination of No. 6, the prediction coefficient is determined by solving the equation 9 described later using the matrix solution method. The prediction coefficient store in step 17 stores the prediction coefficient in the memory, and step 18
Then, the control of the learning unit ends.

The simplest method for class division is to use the bit sequence of the learning data in the block as the class number as it is. However, this method requires a huge amount of memory.

In this example, ADRC is used for class division according to the signal pattern of the SD signal. Originally ADRC
Is an adaptive requantization method developed for high-efficiency coding for VTRs, which can efficiently express a local pattern of signal levels with a short word length. When an SD pixel (3 × 3) block is used, if A in FIG.
The levels of the D pixels a to i are x1 to x9, respectively. Further, the requantized data obtained by performing the p-bit ADRC on the data of x1 to x9 is q1 to q9, respectively, and its dynamic range is DR, the maximum value is MAX, and the minimum value is MIN. At this time, the class of this block is
It is defined by Equation 1.

[0017]

[Equation 1]

Here, taking 1-bit ADRC as an example, A
The DRC will be described. An example of the ADRC encoding circuit 33 is shown in FIG. In FIG. 4, the detection circuit 22 detects the maximum value MAX and the minimum value MIN for each block with respect to the data converted into the order of blocks from the input terminal 21. MAX and MIN are supplied to the subtraction circuit 23, and the dynamic range DR is generated at the output thereof. The input data and MIN are supplied to the subtraction circuit 24, and the subtraction circuit 2
By removing the minimum value from 4, normalized pixel data is generated.

The dynamic range DR is supplied to the division circuit 25, the normalized pixel data is divided by the dynamic range DR, and the output data of the division circuit 25 is supplied to the comparison circuit 26. The comparison circuit 26 determines whether the division calculation power of the eight pixels other than the central pixel is larger or smaller than 0.5 with reference to 0.5. Depending on this result,
Data DT of "0" or "1" is generated. This comparison output DT is taken out to the output terminal 27. This 1-bit AD
If the class is divided using RC, the class of the (3 × 3) SD block is represented by a 9-bit class code.

Next, Table 1 shows the correspondence between the HD pixel of interest and the SD pixel. In Table 1, A, B, C, and D respectively represent HD pixels, and x1 to x9 are data when predicting each HD pixel, that is, data for class creation.
Regarding a plurality of attention HD pixels A, B, C, and D that are close to each other,
By defining the SD pixels used as x1 to x9 as shown in Table 1, the coefficients relating to these HD pixels can be integrated. Therefore, it is not necessary to prepare a separate prediction coefficient memory for each HD pixel, the memory can be shared, and the hardware can be simplified.

[0021]

[Table 1]

The process for obtaining the coefficient for identifying the relationship between the HD pixel and the SD pixel in FIG. 2 will be described in more detail. Generally, when the SD pixel level is set to x1 to xn and the HD pixel level is set to y, n by the coefficients w1 to wn for each class
Linear estimation formula of tap y ′ = w1x1 + w2x2 + ... + wnxn (2) is set. Before learning, wi is an undetermined coefficient.

As described above, learning is performed by using a plurality of Hs for each class.
Perform on D data and SD data. When the number of data is m, y _j ′ = w1x _j 1 + w2x _j 2 + ... + wnx _j n (3) (where j = 1, 2, ...

When m> n, w1 to wn are not uniquely determined, and therefore the elements of the error vector e are e _j = y _j − (w1x _j 1 + w2x _j 2 + ... + wnx _j n) (4) (however, j = 1, 2, ..., M), and a coefficient that minimizes the following Expression 5 is obtained.

[0025]

[Equation 2]

This is a so-called least squares method. Here, the partial differential coefficient by wi of Formula 4 is calculated.

[0027]

[Equation 3]

Since each wi may be determined so that equation 6 is set to 0,

[0029]

[Equation 4]

Assuming that the matrix is used,

[0031]

[Equation 5]

Thus, the prediction coefficient wi can be obtained by solving for wi using a general matrix solution method such as the sweep-out method.
The prediction coefficient wi is stored in the memory using the class code as an address.

As described above, the learning unit is the actual data HD
The signal can be used to obtain the prediction coefficient wi, which is stored in memory. Next, when an SD signal is converted into an HD signal, that is, when up-converted, an arbitrary input S
An output HD image can be generated for the D image.
The configuration for this is shown in the block diagram of FIG.

The blocking circuit 32 converts the SD signal input from the input terminal 31 into the data of the raster scanning order as shown in FIG. 2 in the order of (3 × 3) blocks. The output data of the blocking circuit 32 is supplied to the ADRC circuit 33 and the prediction calculation circuit 35.

In the ADRC circuit 33, the supplied data in block units is subjected to, for example, 1-bit ADRC encoding, and the class is determined according to Expression 1. At this time, the law of Table 1 also applies.

The class code generation circuit 34 generates a class code corresponding to the determined class, and the class code is supplied to the prediction coefficient memory 5 as an address. The prediction coefficient of the class is read from the memory 5, and the prediction calculation circuit 35 determines the prediction coefficient w determined as the block unit data supplied from the blocking circuit 32.
1 to wn, a prediction formula y ′ = w1x1 + w2x2 + ... + wnxn (10) The estimated HD data y ′ is output by the calculation according to (10)
Output from. In the example of FIG. 2 described above, (n = 9). Corresponding to the position of the HD data y ′ to be predicted, the predetermined SD data are x1 to x1 in the relationship shown in Table 1 above.
Used as x9.

Here, FIG. 6 is a flowchart of the above-described up-conversion processing. The up-conversion control is started from step 41, and in the data block formation of step 42, the SD signal is supplied, and as shown in FIG. 2, processing of extracting SD pixels in processing block units is performed.
At the end of the data in step 43, if the processing of all the input data has been completed, the control proceeds to the end of step 47, and if not completed, the control proceeds to the class determination in step 44.

In the class determination of step 44, the class is determined from the signal pattern of the SD signal. With this control,
It is preferable to use 1-bit ADRC in order to reduce the number of bits as in learning. In the prediction coefficient restoration of step 45, the prediction coefficient corresponding to the class code is restored from the memory. In the prediction calculation of step 46, the prediction formula calculation of Formula 10 is performed to output the prediction data of HD pixels. This series of control is repeated for all the data, and when all the data are completed, the control moves from the data end of step 43 to the end of step 47, and the up-conversion processing is completed.

In the blocking circuit 32, as shown in FIG.
Although a D pixel (3 × 3) block, that is, a two-dimensional block is used, this is merely an example, and instead, for example, as shown in FIG. 7, SD pixels 3 to 4 pixels, that is, a one-dimensional block is used. , HD pixels can also be interpolated.

In the one-dimensional interpolation of FIG. 7, in the case of learning,
The prediction coefficient of the HD pixel A is obtained from the SD pixels a, b and c,
The prediction coefficient of the HD pixel B is obtained from the SD pixels a, b, c and d. In the case of interpolation, the HD pixel A is interpolated from the SD pixel a, b, c and the prediction coefficient acquired by learning, and SD
The HD pixel B is interpolated from the prediction formula corresponding to the pixels a, b, c, and d.

Although the ADRC circuit 33 is provided as the information compression means, instead of the ADRC circuit 33, for example, DCT (Discrete Cosine Transform), V
What is provided can be appropriately selected as long as it is a means that can perform data compression, such as a Q (vector quantization) or DPCM (predictive coding) circuit.

[0042]

According to the present invention, the correspondence relationship between the SD signal and the HD signal is learned based on the property of the actual image, and the HD signal corresponding to the SD signal is determined from the learning, so that the interpolation close to the actual image is performed. Can be done. Also, SD
Since the class is adaptively selected according to the level distribution of the signal, up-conversion that follows the local property of the image becomes possible. Further, the present invention is different from the one using the interpolation filter and can obtain the HD signal of which the resolution is compensated.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a configuration for acquiring a prediction coefficient in an image signal conversion device according to the present invention.

FIG. 2 is an example of a schematic diagram used to describe HD pixels and SD pixels in an embodiment of the present invention.

FIG. 3 is a flowchart of an example of a configuration for acquiring a prediction coefficient in the image signal conversion device according to the present invention.

FIG. 4 is a block diagram used to describe an ADRC circuit.

FIG. 5 is a block diagram of an embodiment of an image signal conversion device according to the present invention.

FIG. 6 is a flowchart of an embodiment of the present invention.

FIG. 7 is an HD pixel and SD in another embodiment of the present invention.
It is an approximate line figure used for explanation of a pixel.

[Fig. 8] Fig. 8 is a block diagram used for description of up-conversion from a conventional SD signal to an HD signal.

FIG. 9 is a block diagram of an example of an interpolation filter used in a conventional signal conversion device.

[Explanation of symbols]

 5 Prediction Coefficient Memory 31 Input Terminal 32 Blocking Circuit 33 ADRC Circuit 34 Class Code Generation Circuit 35 Prediction Arithmetic Circuit 36 Output Terminal

Claims (3)

[Claims] 1. An image signal conversion device for converting a standard resolution image signal into a high resolution image signal, means for performing class division according to the shape of the level distribution of the standard resolution input image signal, and the class division. A storage unit that stores prediction coefficient values acquired by learning in advance for each of the selected classes, and is connected to the storage unit, and outputs an optimum estimated value from an operation based on a prediction formula that includes the prediction coefficient value. An image signal conversion apparatus comprising means for outputting an image signal having a higher resolution than the input image signal by including the estimated value. 2. The image signal conversion device according to claim 1, wherein adaptive dynamic range coding is used as the class division in order to save memory capacity. 3. The image signal conversion apparatus according to claim 1, wherein the prediction coefficients for a plurality of adjacent pixels of the high resolution signal are integrated to save memory.