JPH0778788A - Semiconductor device wiring structure, forming method thereof, and mos transistor - Google Patents

Abstract

PURPOSE:To provide a method of forming a semiconductor device wiring structure which is capable of lessening a lower conductor region in sheet resistance, restrained from increasing in contact resistance and junction leakage, and set excellent in barrier properties. CONSTITUTION:The wiring structure of a semiconductor device is composed of a lower conductor region 18 formed on a semiconductor substrate 10, an upper wiring layer 32 formed on an insulating layer 22b which covers the lower conductor region 18, and a connection hole 28 which electrically connects the lower conductor region 18 and the upper wiring layer 32 together. A single crystal CoSi2 layer 20 and a single crystal TiN layer 26 are formed on the base of the connection hole 28 facing the semiconductor substrate 10 in this sequence. The wiring forming method, includes a step wherein a single crystal CoSi2 layer is epitaxially grown on the base of a connection hole and a step wherein a single crystal TiN layer is epitaxially grown on the single crystal CoSi2 layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a wiring forming method in a semiconductor device, and a MOS type transistor.

[0002]

2. Description of the Related Art As semiconductor devices become highly integrated, the junction depth is becoming shallower. When the dimensional rule of the semiconductor device reaches the level of 0.1 μm, the sheet resistance of the junction area becomes 1
Since it becomes more than kΩ / □, there arises a problem that the response speed of the semiconductor element becomes slow. One method of solving this problem is to form salicide of CoSi ₂ , TiSi ₂ or the like on the surface of the source / drain regions formed on the semiconductor substrate.

In order to electrically connect the source / drain region and the upper wiring layer, it is necessary to form a connection hole.
The connection hole forms an insulating layer covering the source / drain region, forms an opening in the insulating layer above the source / drain region, and forms a barrier layer on the insulating layer including the opening. It is formed by depositing a metal wiring material on the barrier layer to fill the opening with the barrier layer and the metal wiring material. The barrier layer is formed to suppress the reaction between the source / drain regions and the metal wiring material in the opening.

As the dimensional rules of semiconductor devices become finer, the diameter of the connection holes also tends to become finer. As a result, there is a problem that the coverage of the barrier layer in the opening is reduced and the barrier property of the barrier layer is reduced.

Here, an outline of a conventional semiconductor device manufacturing process will be briefly described below with reference to FIG.

[Step-10] The element isolation region 12 and the gate electrode 14 are formed on the semiconductor substrate 10 by a conventional method.

[Process-20] LDD (Lightly-Doped Dr
Ion implantation is performed to form the ain) structure, then the gate sidewall 16 is formed, and then ion implantation is performed to form the lower-layer conductor region 18 including the source / drain regions (see FIG. 6A).

[Step-30] In order to reduce the sheet resistance of the lower conductor region 18 composed of the source / drain regions,
The CoSi ₂ salicide layer 10 is formed on the surface of the lower conductor region 18.
0 is formed (see FIG. 6B). Therefore, after forming a Co layer on the entire surface, heat treatment is performed to form the lower conductor region 1
8 in the Co layer to react with Co in the Co layer to form CoSi ₂
Form layer 100. The unreacted Co layer is selectively removed with hydrogen peroxide.

[Step-40] After that, the insulating layer 22 is formed on the entire surface.
And further, an opening 24 is formed above the lower layer conductor region 18 (see FIG. 6C).

[Step-50] Next, a barrier layer (consisting of a Ti layer / TiN layer from below) 102 is formed on the insulating layer 22 including the openings 24 by, for example, a sputtering method, and a tungsten layer 104 is further formed by a CVD method. After depositing on the whole surface at
The tungsten layer 104 and the barrier layer 10 on the insulating layer 22
2 is selectively removed to form a connection hole 28 made of a tungsten plug in the opening 24 (see FIG. 7A). Then, from the bottom, Ti layer / TiON layer / Al-S
After the i layer is deposited on the entire surface by the sputtering method, the wiring 106 is formed by patterning these layers (see FIG. 7B). In addition, 106A is Ti layer / Ti
An ON layer is shown.

In the above process, since the barrier layer 102 formed in the opening 24 is formed by the sputtering method, the coverage of the barrier layer 102 in the opening 24 becomes extremely high as the aspect ratio of the opening 24 increases. Get worse. As a result, the thickness of the barrier layer 102 at the bottom of the opening 24 is reduced. Therefore, the tungsten layer 1 is formed by the CVD method.
When 04 is deposited, the barrier layer 102 is eroded by the fluorine contained in the CVD source gas (WF ₆ ),
Further, the source / drain regions 18 are corroded by fluorine. As a result, there arises a problem that junction leakage increases.

As a method for solving the problem of the coverage of the barrier layer 102 in the opening 24, T by CVD method is used.
The formation of a barrier layer composed of i layer / TiN layer can be mentioned. The CVD method can solve the coverage problem of the barrier layer 102 at the bottom of the opening 24. However, since the TiN layer formed by the CVD method is polycrystalline, when the semiconductor substrate is subjected to a high temperature heat treatment such as a subsequent diffusion step or an annealing step, the TiN grain boundary portion is corroded by fluorine, There is a problem that the metal wiring material in the connection hole 28 diffuses in the TiN grain boundary portion and corrodes the semiconductor substrate. That is, it cannot be said that the polycrystalline TiN layer has sufficient barrier properties.

In order to solve the problem caused by the polycrystallinity of the TiN layer, the present applicant has proposed to directly epitaxially grow a single crystal TiN layer on a silicon semiconductor substrate (see Japanese Patent Application No. 5-69197). ).

[0014]

However, even if a single crystal TiN layer is simply formed on a silicon semiconductor substrate, it is difficult to obtain a good electrical ohmic contact. This is because there is a natural oxide film on the semiconductor substrate,
This is because, even if the iN layer is formed on this natural oxide film, the TiN layer cannot reduce the natural oxide film, so that electrical conduction is difficult to obtain. Furthermore, if the natural oxide film remains,
There is also a problem that the TiN layer is difficult to grow epitaxially on the semiconductor substrate.

The following method can be given as a method for solving these problems. That is, the natural oxide film is reduced by hydrogen plasma before forming the TiN layer. This removes the natural oxide film and exposes the clean surface of the silicon semiconductor substrate. Then, a raw material gas for CVD is introduced to form a TiN layer by the CVD method.

However, as a problem in this method,
As a pretreatment before the formation of the TiN layer, the surface of the silicon semiconductor substrate is exposed to hydrogen plasma treatment. As a result, there is a problem that hydrogen atoms enter the silicon crystal, crystal defects occur in the silicon crystal, and junction leak increases.

When the TiN layer is formed on the silicon semiconductor substrate by the CVD method, the surface of the silicon semiconductor substrate is exposed to nitrogen plasma, so that a thin SiN film is formed on the surface of the silicon semiconductor substrate and the contact resistance increases. There is also the problem of doing.

Further, in this method, the silicon surface is exposed on the surface of the source / drain regions. Therefore, the salicide layer cannot be formed on the surface of the source / drain regions in order to reduce the sheet resistance of the source / drain regions as described above. That is,
There is also a problem that a single crystal TiN layer cannot be formed on the salicide layer.

Therefore, it is an object of the present invention to reduce the sheet resistance of the lower conductor region, to suppress the increase of contact resistance and junction leakage, and to provide a wiring structure in a semiconductor device having an excellent barrier property. It is to provide a forming method thereof and a MOS transistor.

[0020]

The above object is to provide a lower conductor region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the lower conductor region, a lower conductor layer and an upper wiring layer. A wiring structure in a semiconductor device, which comprises a connection hole for electrically connecting and,
From the semiconductor substrate side, single crystal CoSi ₂ layer and single crystal Ti
This can be achieved by the wiring structure of the present invention characterized in that the N layer is formed.

In the wiring structure of the present invention, the semiconductor substrate is preferably a silicon semiconductor substrate. Also,
The orientation of the silicon semiconductor substrate is preferably (100).

Alternatively, the above-mentioned object is to electrically connect the lower conductor region formed on the semiconductor substrate, the upper wiring layer formed on the insulating layer covering the lower conductor region, the lower conductor layer and the upper wiring layer. A wiring forming method for forming a wiring structure in a semiconductor device, the method including:
A wiring forming method according to the present invention, which comprises a step of epitaxially growing a single crystal CoSi ₂ layer at least on the bottom of a contact hole, and a step of epitaxially growing a single crystal TiN layer on the single crystal CoSi ₂ layer. You can

In the wiring forming method of the present invention, the vacuum degree of the atmosphere before the epitaxial growth of the single crystal TiN layer is preferably 1.3 × 10 ^-5 Pa or less. Furthermore, before epitaxially growing the single crystal TiN layer,
It is preferable to include a step of removing the natural oxide film formed on the surface of the single crystal CoSi ₂ layer by hydrogen plasma treatment.

Further, the above object is to provide source / drain regions formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the source / drain regions, a source / drain region and an upper wiring layer. A single-crystal CoSi ₂ layer and a single-crystal TiN layer are formed at the bottom of the connection hole from the side of the semiconductor substrate. This can be achieved by the MOS type transistor of the present invention characterized by the above.

[0025]

In the present invention, the single crystal CoSi ₂ layer is formed at least at the bottom of the connection hole, and the lower sheet resistance of the lower conductor region can be achieved. In addition, single crystal Co
A single crystal TiN layer having an excellent barrier property is formed on the Si ₂ layer. When the native oxide film is removed by hydrogen plasma treatment before forming the TiN layer, CoSi ₂
Since the layer is formed, entry of hydrogen atoms into the silicon crystal can be suppressed. Furthermore, TiN
When the layer is formed, the surface of the silicon semiconductor substrate is not exposed to nitrogen plasma, and the formation of the SiN film can be prevented.

Conventionally, CoSi ₂ is known to grow epitaxially on a (111) silicon semiconductor substrate. However, the (100) silicon semiconductor substrate is often used in the production of ordinary MOS transistors. Co on a (100) silicon semiconductor substrate
In order to epitaxially grow Si ₂ , two layers of Co layer / Ti layer are previously formed on a semiconductor substrate. afterwards,
When heat treatment is applied to these two layers, a single crystal CoSi ₂ layer / Si structure can be obtained. At this time, single crystal CoS
A TiO _x layer is formed on the surface of the i ₂ layer.

A single crystal Ti is formed on the single crystal CoSi ₂ layer.
In order to epitaxially grow the N layer, hydrogen plasma treatment is performed in the apparatus for forming the TiN layer, and the single crystal C
It is necessary to reduce and remove TiO _x on the surface of the oSi ₂ layer. Then, by continuously forming a single crystal TiN layer by a CVD method, a single crystal TiN layer / single crystal CoSi ₂ layer / Si structure can be obtained.

Here, the degree of vacuum before film formation is also an important factor for epitaxially growing the single crystal TiN layer. According to gas kinetics, temperature T ° K, pressure P (toor)
The number N of the molecules having the molecular weight M colliding with the unit area (1 cm ² ) per second in the atmosphere of N is 2.89 × 10 ²² P (MT) ^−1/2 cm ⁻² s ⁻¹ (Equation (1 ) Can be represented.

The degree of vacuum before introducing the CVD source gas is 0.133 P in the chamber of the single crystal TiN layer forming apparatus.
In the case of a (1 × 10 ⁻³ toor), from equation (1), for example,
At room temperature (25 ° C.), oxygen molecules collide with 1 cm ^{2 of} the silicon semiconductor substrate at 3.0 × 10 ¹⁷ molecules / sec.

The intermolecular distance is 0.24 nm (interatomic distance +
Atomic diameter). Therefore, unit area (1 cm ² )
1 layer per ^{inner, (0.01 / 0.24 × 10- 9} )
² = 1.74 × 10 ¹⁵ oxygen molecules / cm ² exist.
All of the oxygen molecules that collide with the semiconductor substrate are single crystal CoSi
Assuming adsorption on the surface of _two layers, 1.74 × 10 ¹⁵
/3.0×10 ¹⁷ = A layer of oxygen molecules is formed in about 0.0058 seconds.

If 10 layers of TiN are grown for 1 minute, the surface of the semiconductor substrate must be kept clean during this period. To this end, it is necessary to keep the chamber of the film forming apparatus at a vacuum level at which no oxygen molecular layer is formed on the surface of the semiconductor substrate for one minute or more.
In other words, it is necessary to set the time required for forming one oxygen molecular layer to be 1 minute or more. From the formula (1), the degree of vacuum is required so that 2.9 × 10 ¹³ / second or less oxygen molecules collide with the single crystal CoSi ₂ layer per second. That is, a single crystal TiN layer can be formed on a clean semiconductor substrate surface by maintaining a vacuum degree of 1.3 × 10 ⁻⁵ Pa or less.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings. In Example 1, the single crystal TiN layer is formed on the bottom of the contact hole by the epitaxial growth method. In the second and third embodiments, single crystal Ti is epitaxially grown on the source / drain regions.
The N layer is formed.

(Example 1) Example 1 is an example in which the wiring structure and the wiring forming method of the present invention are applied to the manufacture of a MOS transistor.

As shown in the schematic partial cross-sectional view of FIG. 1, the wiring structure of the first embodiment has a lower conductor region 18 formed on the semiconductor substrate 10 and an insulating layer 22A for covering the lower conductor region 18. The upper wiring layer 32 is formed on the upper layer 22B, and the connection hole 28 electrically connects the lower conductor layer 18 and the upper wiring layer 32. Then, at the bottom of the connection hole 28, from the semiconductor substrate side, the single crystal CoSi ₂ layer 20 and the single crystal T are formed.
The iN layer 26 is formed. The lower layer conductor region 18 is specifically a source / drain region. The semiconductor substrate 10 is made of a silicon semiconductor substrate and its orientation is (100). In FIG. 1, 12 is an element isolation region, 14 is a gate electrode, and 30 is a barrier layer.

A method of forming the wiring structure of Example 1 shown in FIG. 1 will be described below with reference to FIGS.

[Step-100] First, the element isolation region 12 and the gate electrode 14 are formed on the silicon semiconductor substrate 10 having the orientation (100) by a conventional method.
Then, ion implantation is performed to form an LDD structure. Then, in order to form the gate sidewall 16, a SiO ₂ film is formed on the entire surface by the CVD method. SiO ₂
The film forming conditions can be set as follows, for example. Gas used: SiH ₄ / O ₂ / N ₂ = 250/250 /
100 sccm Temperature: 420 ° C Pressure: 13.3 Pa Film thickness: 0.25 μm

After that, the SiO ₂ film is etched back under the following conditions, for example, to form the gate sidewall 16 on the sidewall of the gate electrode 14. Gas used: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa

Next, impurity ion implantation for forming the source / drain regions is performed, for example, under the following conditions to form the lower layer conductor region 18 composed of the source / drain regions (see FIG. 2A). [In case of N channel formation] Ion species: As 20 KeV 5 × 10 ¹⁵ / cm ² [In case of P channel formation] Ion species: BF _{2 20} KeV 3 × 10 ¹⁵ / cm ²

[Step-110] Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.
_Two layers 20 are formed. Therefore, first, a Ti layer having a thickness of 5 nm is formed on the entire surface by the sputtering method under the following conditions, for example. Process gas: Ar = 100 sccm Power: 1 kW Film forming temperature: 150 ° C Pressure: 0.47 Pa

Further, a Co layer is continuously sputtered,
For example, it is formed under the following conditions. Process gas: Ar = 100 sccm Power: 3 kW Film formation temperature: 150 ° C Pressure: 0.47 Pa

Then, heat treatment is performed to form the single crystal CoSi ₂ layer 20 from the Co layer by the silicidation reaction. The heat treatment condition is, for example, 600 ° C. × 60 seconds in a nitrogen gas (1 atm) atmosphere. by this,
Co reacts with Si in the semiconductor substrate to form CoSi _x . Then, the unreacted Ti and Co are selectively removed by immersing the entire semiconductor substrate in a mixed solution of hydrochloric acid, hydrogen peroxide and pure water for 10 minutes. Then, for example, nitrogen gas (1 atm) atmosphere, a heat treatment of 850 ° C × 60 seconds, a stable CoS the CoSi _X
i ₂ . Thus, the CoSi ₂ layer 20 is formed on the surface of the lower conductor region 18 including the source / drain regions (see FIG. 2B). When the CoSi ₂ layer 20 is formed, a natural oxide film (not shown) made of TiO _x is formed on the surface of the CoSi ₂ layer 20. The natural oxide film is removed by a hydrogen plasma treatment process which will be described later.

[Step-120] After that, SiO _{2 is formed on the} entire surface.
The insulating layer 22A made of, for example, CV using TEOS
It is formed by the D method. The conditions for forming the insulating layer 22A can be, for example, used gas: TEOS = 50 sccm pressure: 40 Pa temperature: 720 ° C. film thickness: 400 nm. Furthermore, B is further formed on the insulating layer 22A.
The insulating layer 22B made of PSG is formed under the following conditions, for example. Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ / O ₂ / N ₂ = 8
0/7/7/1000 / 32000sccm Temperature: 400 ° C Pressure: 1.0 × 10 ⁵ Pa Film thickness: 500 nm

Next, after heat treatment is applied to flatten the surface of the insulating layer, resist patterning is performed on the insulating layers 22A and 22B, and then the insulating layer 22 is dry-etched.
The openings 24 are formed in A and 22B (see FIG. 2C). The conditions of dry etching can be set as follows, for example. Gas used: C ₄ F ₈ = 50 sccm RF power: 1200 W Pressure: 2 Pa

After that, a junction region is formed by performing ion implantation. The conditions of ion implantation are illustrated below. [In case of forming N channel] Ion species: As 20 KeV 5 × 10 ¹⁵ / cm ² [In case of forming P channel] Ion species: BF _{2 20} KeV 3 × 10 ¹⁵ / cm ^{2 and} then at 1050 ° C. × 5 seconds Perform activation annealing.

[Step-130] Next, a single crystal TiN layer 26 is formed on the bottom of the opening 24. For that purpose, first,
ECRC is performed on the substrate that has been processed up to [Step-110].
Bring in the VD device. Here, the ECRCVD apparatus is used such that the degree of vacuum of the atmosphere before epitaxially growing the single crystal TiN layer is 1.3 × 10 ⁻⁵ Pa or less. After the substrate is loaded into the ECRCVD apparatus, the natural oxide film and the like existing on the surface of the CoSi ₂ layer 20 exposed at the bottom of the opening 24 is reduced and removed by hydrogen plasma treatment under the following conditions, for example. Gas used: H ₂ / Ar = 26/60 sccm Microwave power: 2.8 kW

Next, the single crystal TiN layer 26 is formed by the ECRCVD method. The conditions for forming the single crystal TiN layer 26 can be set as follows, for example. Incidentally, a TiN nucleus is formed on the surface of the single crystal CoSi ₂ layer 20 in the first film forming step, and the single crystal T is formed from this nucleus in the second film forming step.
Grow iN. In the first film forming stage, single crystal T
It is desirable to grow iN epitaxially at a growth rate of 10 monolayers / minute or less. By providing the first film formation step, the single crystal T in the second film formation step
The growth rate of the iN layer can be increased. [Conditions for the First Film Forming Stage] Working gas: TiCl ₄ / H ₂ / N ₂ = 2/2.
6 / 0.8 sccm Temperature: 750 ° C Film thickness: 0.5 nm Pressure: 6.6 × 10 ⁻⁴ Pa Microwave power: 2.8 kW [Conditions for the second film forming stage] Working gas: TiCl ₄ / H ₂ / N ₂ = 20/2
6/8 sccm Temperature: 750 ° C Film thickness: 70 nm Pressure: 0.12 Pa Microwave power: 2.8 kW As a result, the epitaxially grown single crystal TiN layer 26 is formed on the entire surface of the insulating layer 22B including the bottom of the opening 24. (See FIG. 3A). In Example 1, it is desirable that the temperature during film formation be 700 to 1250 ° C. Incidentally, depending on the formation conditions of the single crystal TiN layer,
The single crystal TiN layer 26 may not be completely epitaxially grown on the insulating layer 22B, but this is sufficient because the object of the present invention can be sufficiently achieved.

[Step-140] After that, a metal wiring material is embedded in the opening 24 to form the connection hole 28. In Example 1, tungsten (W) was used as the metal wiring material. That is, for example, tungsten is deposited on the single crystal TiN layer 26 by the CVD method under the following conditions. The thickness of the tungsten layer on the insulating layer 22B is set to 400
nm. Gas used: WF ₆ / H ₂ = 95/550 sccm Temperature: 450 ° C Pressure: 1.1 × 10 ⁴ Pa

Then, etch back is performed to form the insulating layer 22.
The tungsten layer and the single crystal TiN layer 26 on B are removed, and the tungsten layer and the single crystal Ti are formed only in the opening 24.
The N layer 26 is left. In this way, the connection hole 28 is completed (FIG. 3).
(B)). The conditions of etch back are illustrated below. Gas used: SF ₆ = 50 sccm Microwave power: 850W RF power: 150W Pressure: 1.33Pa

[Step-150] After that, the barrier layer 30 and the upper wiring layer 32 are formed by the sputtering method. Example 1
In the above, the barrier layer 30 is a Ti layer (thickness 30
nm) / TiON layer (thickness 70 nm). The upper wiring layer 32 is made of Al-1% Si (thickness: 50%).
0 nm). The sputtering conditions for each layer are illustrated below. [Ti film forming condition] Process gas: Ar = 100 sccm Power: 4 kW Film forming temperature: 150 ° C Pressure: 0.47 Pa [TiON film forming condition] Process gas: Ar / N ₂ -6% O ₂ = 40/70 sc
cm Power: 5 kW Pressure: 0.47 Pa [Al-1% Si film forming condition] Process gas: Ar = 40 sccm Power: 22.5 kW Film forming temperature: 150 ° C Pressure: 0.47 Pa

Thereafter, resist patterning and dry etching are performed to form the upper wiring layer 32 and the barrier layer 30 into desired wiring pattern shapes. The conditions of dry etching are illustrated below. Gas used: BCl ₃ / Cl ₂ = 60/90 sccm Microwave power: 1000W RF power: 50W Pressure: 0.016Pa

Thus, the wiring structure shown in FIG. 1 can be formed. The single crystal CoSi ₂ layer 20 is formed on the surface of the lower conductor region 18 formed of the source / drain regions, and the lower sheet resistance of the lower conductor region 18 can be achieved. Further, a single crystal TiN layer 26 having an excellent barrier property is formed on the single crystal CoSi ₂ layer 20.
When the natural oxide film or the like is removed by hydrogen plasma treatment before forming the single crystal TiN layer 26, the CoSi ₂ layer 2 is already formed.
Since 0 is formed, entry of hydrogen atoms into the silicon crystal can be suppressed. Further, when the single crystal TiN layer 26 is formed, the surface of the silicon semiconductor substrate is not exposed to the nitrogen plasma, and the formation of the SiN film can be prevented.

Example 2 In Example 1, the single crystal TiN layer 26 has a single crystal CoS layer at the bottom of the opening 24.
It is in contact with the i ₂ layer 20. On the other hand, in Example 2, the single crystal TiN layer is formed on the entire surface of the single crystal CoSi ₂ layer. In addition, in Example 1, the opening 2
4 was filled with tungsten to form the connection hole 28. On the other hand, in the second embodiment, when the upper wiring layer is formed by sputtering the aluminum-based wiring material, the buried connection hole 28 is also formed in the opening 24 with the aluminum-based wiring material.

[Step-200] First, the element isolation region 12 and the gate electrode 14 are formed on the silicon semiconductor substrate 10 having the orientation (100) by the conventional method, and then the LDD structure is formed and the gate side is formed. Formation of wall 16 and lower layer conductor region 18 including source / drain regions
Formation. These forming conditions can be the same as those in [Process-100] of the first embodiment.

[Step-210] Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.
_Two layers 20 are formed. This step also corresponds to [Step-
110].

[Step-220] Then, single crystal CoSi
_A single crystal TiN layer 40 is formed on the _two layers 20. Therefore, first, the hydrogen plasma treatment described in [Step-130] of Example 1 is performed to remove the natural oxide film and the like formed on the surface of the single crystal CoSi ₂ layer 20. Then ECR
The single crystal TiN layer 40 is formed into a single crystal CoSi by the CVD method.
_It is selectively formed only on the _two layers 20. By setting the temperature at the time of film formation to be lower than that in [Step-130] of Example 1, the single crystal TiN layer 40 is selectively formed only on the single crystal CoSi ₂ layer 20. It is desirable to further promote TiN single crystallization by applying a substrate bias during film formation. The conditions for forming the single crystal TiN layer 40 can be set as follows, for example. Note that TiN nuclei are formed on the surface of the CoSi ₂ layer 20 in the first film forming step, and single crystal TiN is grown from the nuclei in the second film forming step. [Conditions for the First Film Forming Stage] Working gas: TiCl ₄ / H ₂ / N ₂ = 2/2.
6 / 0.8 sccm Temperature: 300 ° C Film thickness: 0.5 nm Pressure: 6.6 × 10 ⁻⁴ Pa Microwave power: 2.8 kW [Conditions for the second film formation stage] Working gas: TiCl ₄ / H ₂ / N ₂ = 20/2
6/8 sccm temperature: 300 ° C. film thickness: 70 nm pressure: 0.12 Pa microwave power: 2.8 kW As a result, the epitaxially grown single crystal TiN layer 40 is formed on the single crystal CoSi ₂ layer 20 (FIG. 4).
(A)). A polycrystalline TiN layer 40A is formed on the gate electrode 14. Further, under the above film forming conditions, the TiN layer is not formed on the element isolation region 12.

[Step-230] Next, in the same manner as in [Step-120] of Example 1, after forming the insulating layers 22A and 22B on the entire surface, the openings 24 are formed in the insulating layers 22A and 22B (see FIG. 4 (B)), ion implantation is performed to form a junction region, and activation annealing is performed at 1050 ° C. × 5 seconds.

[Step-240] Next, an underlayer 42 made of Ti and having a thickness of 30 nm is formed on the insulating layer 22B including the opening 24 by the sputtering method, and then the underlayer 42 is formed by the high temperature aluminum sputtering method. An upper wiring layer 44 made of Al-1% Si and having a thickness of 500 nm is formed thereon. The formation conditions of the base layer 42 and the upper wiring layer 44 can be set as follows, for example. [Formation conditions of base layer] Process gas: Ar = 100 sccm Power: 4 kW Film formation temperature: 150 ° C Pressure: 0.47 Pa [Formation conditions of upper wiring layer] Process gas: Ar = 40 sccm Power: 22.5 kW Film formation temperature : 500 ° C Pressure: 0.47Pa

Thereafter, similar to [Step-150] of the first embodiment, resist patterning and dry etching are performed to form the upper wiring layer 44 and the underlying layer 42 into desired wiring pattern shapes.

(Embodiment 3) Embodiment 3 is a modification of Embodiment 2. In Example 2, the single crystal TiN layer 40 was selectively formed on the single crystal CoSi ₂ layer 20. In Example 3, the entire surface of the semiconductor substrate including a single crystal CoSi ₂ layer to form a TiN layer, then, the single-crystal CoSi ₂ layer on the single crystal TiN layer, and single crystal Ti used as a wiring portion
The N layer is left and the other part of the TiN layer is removed.

[Step-300] First, the element isolation region 12 and the gate electrode 14 are formed on the silicon semiconductor substrate 10 having the orientation (100) by the conventional method, and then the LDD structure is formed and the gate side is formed. Formation of wall 16 and lower layer conductor region 18 including source / drain regions
Formation. These forming conditions can be the same as those in [Process-100] of the first embodiment.

[Step-310] Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.
_Two layers 20 are formed. This step also corresponds to [Step-
110].

[Step-320] After that, single crystal CoSi
_A single crystal TiN layer 40 is formed on the _two layers 20. Also,
The single crystal TiN layer 40 is formed in the region other than the single crystal CoSi ₂ layer.
Form A. For that purpose, first, [Step-
130], the natural plasma film formed on the surface of the single crystal CoSi ₂ layer 20 is removed. Next, single crystal CoSi ₂ was formed by the ECRCVD method.
The single crystal TiN layer 40 is formed on the layer 20, and the single crystal TiN layer 40A is also formed in other regions. The single crystal TiN layer 40A may be formed depending on the formation conditions of the single crystal TiN layer.
May not completely epitaxially grow on another region (for example, the element isolation region 12), but the object of the present invention can be sufficiently achieved, and therefore, there is no problem.

The temperature at the time of film formation was set to [Step-22 in Example 2].
0], the single crystal TiN layer 40
Is formed on the single crystal CoSi ₂ layer 20, and the single crystal TiN layer 40A is also formed in other regions. It is desirable to further promote TiN single crystallization by applying a substrate bias during film formation. TiN layers 40, 40
The conditions for forming A can be set as follows, for example. Incidentally, a TiN nucleus is formed on the surface of the CoSi ₂ layer 20 or the like in the first film forming step, and a single crystal TiN layer is grown from this nucleus in the second film forming step. [Conditions for the First Film Forming Stage] Working gas: TiCl ₄ / H ₂ / N ₂ = 2/2.
6 / 0.8 sccm Temperature: 750 ° C Film thickness: 0.5 nm Pressure: 6.6 × 10 ⁻⁴ Pa Microwave power: 2.8 kW Substrate RF bias: −50 W [Conditions for the second film formation stage] Working gas : TiCl ₄ / H ₂ / N ₂ = 20/2
6/8 sccm Temperature: 750 ° C Film thickness: 70 nm Pressure: 0.12 Pa Microwave power: 2.8 kW Substrate RF bias: -50 W As a result, the epitaxially grown single crystal TiN layer 40 is formed on the single crystal CoSi ₂ layer 20. The single crystal TiN layer 40A is also formed in the other regions.

[Step-330] After that, the unnecessary single crystal TiN layer 40A is removed by dry etching after resist patterning, and the single crystal TiN layer 40A necessary as a wiring portion is left. Dry etching conditions
For example, it can be as follows. Gas used: BCl ₃ / Cl ₂ = 60/90 sccm Power: 50W Pressure: 2Pa

[Step-340] Next, in the same manner as in [Step-120] of Example 1, after forming the insulating layers 22A and 22B on the entire surface, the openings 24 are formed in the insulating layers 22A and 22B, and the ions are formed. Implantation is performed to form a junction region, and activation annealing is performed at 1050 ° C. for 5 seconds.

[Step-350] Next, as in the case of [Step-240] of the second embodiment, the underlayer 42 of Ti having a thickness of 30 nm is formed by the sputtering method on the insulating layer 22 including the opening 24.
B is formed on the underlayer 42 by a high temperature aluminum sputtering method to a thickness of 500 n consisting of Al-1% Si.
The upper wiring layer 44 of m is formed. After that, resist patterning and dry etching are performed in the same manner as in [Step-150] of Example 1 to perform upper wiring layer 44 and base layer 4.
2 is a desired wiring pattern shape. Thus, the wiring structure whose schematic partial cross-sectional view is shown in FIG. 5 can be formed.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various conditions and numerical values described in the embodiments are examples and can be changed as appropriate.

The insulating layers 22A and 22B are made of SiO ₂ and BP.
Besides SG combination, PSG, BSG, AsS
It can be made of a known insulating material such as G, PbSG, SbSG, or SiN, or a combination of these insulating materials. As the aluminum-based wiring material, in addition to Al-1% Si, pure Al or Al-
Examples thereof include Al alloys such as Si-Cu, Al-Cu, and Al-Ge.

The method of forming the connection hole in the first embodiment can be replaced with the method of forming the connection hole described in the second embodiment. That is, in Example 1, after the single crystal TiN layer 26 was formed, the single crystal T was formed by the high temperature aluminum sputtering method.
A thickness of 500 nm made of Al-1% Si on the iN layer 26
By forming the upper wiring layer 32, the upper wiring layer and the connection hole can be formed.

The formation of various layers by the sputtering method can be carried out by various sputtering devices such as a magnetron sputtering device, a DC sputtering device, an RF sputtering device, an ECR sputtering device, and a bias sputtering device for applying a substrate bias. As a CVD device, in addition to the ECRCVD device,
Thermal CVD equipment, plasma CVD equipment, helicon wave, IP
A CVD apparatus equipped with a plasma generation source such as C (Inductively Coupled Plasma) can be used. In addition to the hydrogen plasma treatment for removing the natural oxide film, IP
An Ar sputter etching method with a reduced ion bias such as C soft etching can be adopted.

It is also possible to combine the wiring structure and the method of forming the wiring structure described in the first and second embodiments. That is, the single crystal TiN layer 4 is formed on the surface of the single crystal CoSi ₂ layer 20.
0 is formed, and in addition, single crystal TiN is also formed on the bottom of the opening.
The layer 26 may be formed.

The wiring structure of the present invention can be applied to devices other than MOS type transistors, such as bipolar transistors and CCDs.

[0073]

According to the present invention, since the single crystal CoSi ₂ layer is formed at the bottom of the opening, it is possible to reduce the sheet resistance of the lower conductor region and the wiring material in the lower conductor region and the connection hole. The reaction between and can be prevented by the single crystal TiN layer. Moreover, since the single crystal TiN layer is formed at the bottom of the connection hole, the barrier property is remarkably improved.

Moreover, since the natural oxide film and the like are removed and then the single crystal TiN layer is formed, the single crystal CoSi is formed.
The interface between the _two layers and the single crystal TiN layer is kept clean at the atomic level. Therefore, an ideal ohmic contact is obtained, and the contact resistance can be reduced.

Further, the surface of the semiconductor substrate is made of single crystal CoSi ₂
Since it is covered with a layer and the silicon surface is not exposed, it is possible to suppress the occurrence of crystal defects in the semiconductor substrate even if hydrogen plasma treatment is performed as a pretreatment before the formation of the single crystal TiN layer. It is also possible to prevent the formation of the SiN film due to the nitrogen plasma.

Further, conventionally, a wiring portion was formed by patterning a polycrystalline TiN layer, but in the wiring structure of the third embodiment, since the single crystal TiN layer 40A is used as the wiring portion, the wiring resistance is low. Can be realized.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device showing a wiring structure of a first embodiment.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of the wiring forming method according to the first embodiment.

FIG. 3 is a schematic partial cross-sectional view of the semiconductor element for explaining each step of the wiring forming method according to the first embodiment, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of the wiring forming method according to the second embodiment.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor device showing the wiring structure of the first embodiment.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a conventional wiring forming method.

FIG. 7 is a schematic partial cross-sectional view of the semiconductor element for explaining each step of the conventional wiring forming method, following FIG. 6;

[Explanation of symbols]

10 Semiconductor Substrate 12 Element Isolation Region 14 Gate Electrode 16 Gate Sidewall 18 Lower Conductor Region 20 Single Crystal CoSi ₂ Layer 22A, 22B Insulation Layer 24 Opening 26, 40 Single Crystal TiN Layer 28 Connection Hole 30 Barrier Layer 32, 44 Upper Layer Wiring Layer 40A Wiring part consisting of single crystal TiN layer 42 Underlayer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/768 H01L 21/90 B

Claims (7)

[Claims] 1. A lower-layer conductor region formed on a semiconductor substrate,
A wiring structure in a semiconductor device, comprising: an upper wiring layer formed on an insulating layer that covers the lower conductor region; and a connection hole that electrically connects the lower conductor layer and the upper wiring layer. At the bottom of the hole, from the semiconductor substrate side, single crystal CoSi
A wiring structure in a semiconductor device, wherein _two layers and a single crystal TiN layer are formed. 2. The wiring structure in a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon semiconductor substrate. 3. The wiring structure in a semiconductor device according to claim 2, wherein the orientation of the silicon semiconductor substrate is (100). 4. A lower conductor region formed on a semiconductor substrate,
Wiring formation for forming a wiring structure in a semiconductor device, which includes an upper wiring layer formed on an insulating layer covering the lower conductor region and a connection hole electrically connecting the lower conductor layer and the upper wiring layer a method, in the bottom of at least the connection hole, epitaxially growing a single crystal CoSi ₂ layer, and a wiring forming method characterized by the single-crystal CoSi ₂ layer on comprising the step of epitaxially growing a single crystal TiN layer. 5. The wiring forming method according to claim 4, wherein the vacuum degree of the atmosphere before the epitaxial growth of the single crystal TiN layer is 1.3 × 10 ⁻⁵ Pa or less. 6. The method according to claim 4, further comprising a step of removing a natural oxide film formed on the surface of the single crystal CoSi ₂ layer by hydrogen plasma treatment before epitaxially growing the single crystal TiN layer. Item 5. The wiring forming method according to Item 5. 7. A source / drain region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the source / drain region, and the source / drain region and the upper wiring layer are electrically connected to each other. A MOS transistor having a wiring structure consisting of a connection hole connected to a single crystal CoSi.
A MOS transistor characterized in that _two layers and a single crystal TiN layer are formed.