JPH0778968A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Objective] In a power composite semiconductor device in which, for example, a GTO and a regenerative diode are separately formed on a single semiconductor substrate through a wide and deep recess, a separation layer (P base layer) immediately below the recess is formed. ) Is improved and the strict trade-off relationship between forward off breakdown voltage is improved, and product yield is improved. [Structure] In the recess etched by the conventional technique, the bottom end is etched deeper than the center bottom, and the breakdown voltage is destroyed when the depletion layer extending in the P base layer reaches the etching end. On the other hand, the high impurity diffusion layer forms a strained layer and has a higher etching rate than a non-strained layer in which impurities are not diffused. The present invention, after forming a strained layer not in contact with the side wall of the recess forming region of the substrate selectively in the region before forming the recess,
By etching, a recess is formed in which the depth of the bottom end of the recess does not reach the maximum depth of the bottom surface, thereby alleviating the trade-off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a flat bottom surface and a wide concave portion and a method for manufacturing the same, and is particularly used for a separation layer of reverse conducting GTO or reverse conducting G-Tr and its formation. It is what is done.

[0002]

2. Description of the Related Art A reverse conduction type power element is a GTO (Gate
A device such as a turn-off thyrister) or G-Tr (giant transistor, high-power control transistor) and a regenerative diode are monolithically formed on one pellet.

FIG. 7 is a partial sectional view showing an example of the structure of a reverse conducting GTO. The substrate of the reverse conducting GTO is roughly divided into a GTO region in which the GTO 1 is provided, a region in which the regenerative diode 2 is provided in parallel with the GTO region, and an isolation region which serves as a buffer band for preventing mutual interference between the two elements. .

The GTO 1 has a four-layer structure of a P emitter layer 3, an N ⁻ base layer 4, a P base layer 5 and an N ⁺ emitter layer 6. The N ⁺ layer 4a protruding from a part of the N ⁻ base layer 4 and the P emitter layer 3 are short-circuited by the anode electrode 7,
A so-called emitter short-circuit structure is formed. The N ⁺ emitter layer 6 is formed on the other main surface layer of the substrate with a narrow width in a plurality of divisions, is surrounded by the P base layer 5, and has a structure in which the GTO can be turned on / off by the control voltage of the gate electrode 9. Has become.

The PN junction of the regenerative diode 2 is formed by the P base layer 5 and the P layer 5a, which is the same body as the P base layer 5, and the N ⁻ base layer 4. The P layer 5a of the diode 2 is connected to the cathode electrode 8 of the GTO via the electrode 8a. The cathode region N ⁻ layer 4 of the diode 2 is connected to the anode electrode 7 of the GTO 1 via the N ⁺ layer 4a.

In the normally-off state, the reverse conducting GTO is used by applying a negative bias between the gate terminal G and the cathode terminal K in order to prevent malfunction. Therefore, K → diode electrode 8a → P layer 5a → P layer 5b → P base layer 5
→ Current flows into the gate circuit through the gate electrode 9 → G. If this current becomes large, the gate control function of the GTO is impaired. Therefore, the high-concentration layer in the vicinity of the surface of the separation region is removed by etching or the like, the recess 10 is dug, and the lateral resistance of the P base layer 5b (hereinafter referred to as the separation layer 5b, which is the P base layer 5 immediately below the recess) in the separation region. Is being made as high as possible.

However, in the prior art, the trade-off between the resistance value of the isolation layer 5b and the withstand voltage (forward off-breakdown voltage) is:
As will be described later, it is a problem in a very severe condition.

[0008]

As described in the previous section, the reverse conducting GTO requires the separation layer and its resistance value must be increased. In case of reverse conduction GTO,
The resistance of the separation layer must be 70Ω to 100Ω or more. Figure 8
[Fig. 4] is a partially cutaway perspective view of a GTO for roughly estimating a resistance value of a separation layer 5b. In the case of a large capacity GTO, the P base layer 5 has a surface concentration of about 1 × 10 ¹⁸ cm ^-3 and a diffusion depth X _jp = about.
It is formed with an impurity profile of about 70 μm.

The resistance value of the separation layer is expressed as follows.

R = (ρ _s / 2π) ln (X ₂ / X ₁ ) ρ _s = sheet resistance of the separation layer X ₁ = inner circumference of the separation layer X ₂ = outer circumference of the separation layer The recess 10 is formed by etching, The resistance value R of the separation layer is 70
The width of the recess 10 (X ₂ −
When X ₁ ) is 4 to 6 mm, it is necessary to deeply etch it to 40 to 45 μm.

On the other hand, it is confirmed by trial results that the breakdown voltage (the forward breakdown voltage) is broken down when the depletion layer formed at the PN junction between the P base layer 5 and the N ⁻ base layer 4 reaches the bottom surface of the recess. Was done. Therefore, if the etching depth of the recess 10 is increased in order to increase the resistance of the isolation layer, the depletion layer easily reaches the bottom surface of the recess, and the breakdown voltage decreases.

FIG. 9 shows this state. The vertical axis on the left side of FIG. 9 is the resistance value R of the separation layer, the vertical axis on the right side is the breakdown voltage V,
The horizontal axis represents the etching depth d from the substrate surface to the bottom of the recess. From the figure, the resistance R of the separation layer increases as the depth d increases, but the breakdown voltage V decreases when the depth d exceeds a certain value, and the resistance R and the breakdown voltage V are in a trade-off state. Recognize.

In the prior art, the trade-off between the resistance value and the withstand voltage of the separation layer is very severe, and the yield of products satisfying both the resistance value and the withstand voltage characteristics is extremely poor, which is a serious problem.

In order to solve this problem in terms of pattern design, it is necessary to further widen the width of the isolation region, the number of invalid portions increases, and there is no point in monolithically incorporating.

As a method of forming the isolation region, a method of completely digging and separating the mesa in the isolation layer or a method of forming an N ⁺ diffusion layer in the surface layer to avoid deep etching has been proposed.

FIG. 10 is a sectional view of the separation region showing the former method for separating mesas. As is clear from the figure, in this method, the number of surfaces relating to the breakdown voltage of the device increases from one surface to three surfaces, which causes a problem in reliability and yield.

FIG. 11 is a sectional view of the separation region showing the latter method of forming the N ⁺ diffusion layer on the surface layer. In this method, the diffusion depth of the N ⁺ diffusion layer 11 is adjusted to increase or decrease the cross-sectional area of the conduction path of the separation layer 5b to obtain a desired separation layer resistance, but it is formed in the GTO region. There is a problem in control accuracy in consideration of the control of the N ⁺ emitter layer 6
It was an inappropriate method for mass production.

The present invention has been made in view of the above problems, and in a composite semiconductor device having a wide and deep concave portion such as a reverse conducting GTO and a reverse conducting G-Tr, the distribution of the etching depth of the concave portion can be easily performed. An object of the present invention is to provide a composite semiconductor device that can be controlled and can improve the yield by improving the trade-off relationship between the resistance of the isolation layer immediately below the recess and the breakdown voltage of the device, and a method of manufacturing the same.

[0019]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first semiconductor element and a second semiconductor element are formed on a single semiconductor substrate from the main surface of the substrate. In the method for manufacturing a composite semiconductor device formed separately from each other through the recessed portion, before forming the recessed portion, a strained layer not in contact with the sidewall of the recessed portion forming region of the substrate is selectively formed in the region, and It is characterized by including a step of forming a recess by etching from the main surface of the substrate.

According to a second aspect of the semiconductor device of the present invention, the first semiconductor element and the second semiconductor element are formed on one semiconductor substrate so as to be separated from each other through a recess dug in the main surface of the substrate, and the substrate. Of the depth from the main surface to the bottom of the recess, the depth of the bottom of the recess is not the maximum depth,
It is a semiconductor device characterized by being provided.

[0021]

As described above, the breakdown voltage of the reverse conducting GTO is, for example,
Since the breakdown occurs when the depletion layer reaches the bottom of the recess, it is determined by the off-voltage value at this time. In addition, in the conventional etching method, when a wide and deep recess (for example, a recess having a width of several mm and a depth of several tens of μm) is formed, the end of the bottom of the recess (for example, about 10 % Width) tends to be deeply etched. Therefore, the resistance value of the P base layer (separation layer) immediately below the recess is determined by the central portion occupying most of the area, and the breakdown voltage is determined by the end portion that is deepest etched. In order to improve the trade-off, it is necessary to etch so that the bottom surface of the recess is flat or the bottom end portion does not reach the maximum depth.

The present invention has been completed by utilizing the knowledge obtained from the above trial results and the fact that the strained layer has a faster etching rate than other normal portions in the semiconductor substrate.

In the manufacturing method according to the first aspect, a high-concentration diffusion layer by phosphorus diffusion or the strained layer is selected by honing, a particle accelerator, or the like so as not to come into contact with the side wall of the central portion of the recess formation region. When the recess forming region is etched after the provision of the film, the etching rate of the strained layer portion is faster than that of the non-strained layer near the sidewall of the recessed portion, so that the end portion is prevented from being deeply etched and the entire bottom surface of the recessed portion is prevented. , It is possible to form recesses having almost the same depth or a desired depth distribution.

In the case of the recesses having substantially the same depth, for example, if the thickness (depth) of the separation layer is set to be the same as the thickness of the central portion of the related art, the thickness of the end portion of the separation layer becomes larger than that of the conventional one, and The resistance of is almost equal to the conventional one, and the withstand voltage can be improved.
For the same reason, if the breakdown voltage is the same as the conventional one, the thickness of the separation layer in the central portion can be reduced to the thickness of the end portion, and the resistance of the separation layer can be increased.

According to this manufacturing method, the trade-off relationship between the resistance value of the isolation layer and the withstand voltage can be relaxed, and a product satisfying both characteristics of the resistance value and the withstand voltage can be produced with high yield. .

In the semiconductor device according to the second aspect of the present invention, the depth from the main surface of the substrate to the bottom surface of the recess is such that the depth to the bottom edge does not reach the maximum depth. Is determined by the etching depth at the bottom edge, improving the trade-off relationship between the resistance value of the isolation layer and the breakdown voltage, and at the same time, the resistance value and breakdown voltage of the isolation layer are determined only by the etching depth at the central portion. It becomes possible to control.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the results of trials carried out in the course of completing the present invention will be described with reference to FIG. The figure shows the conventional reverse conduction G
It is an expanded sectional view of the isolation region of TO. The P base layer 5 is
It is formed with a surface concentration of about 1 × 10 ¹⁸ cm ^-3 and a diffusion depth of X _jp = about 70 μm. The recess 10 has a width w = about 5 mm and a depth d.
= 40-45 μm, the separation layer 5
The resistance R of b can be 70Ω to 100Ω or more.
However, the etching depth at the end of the bottom surface of the recess is as deep as Δd = 6 to 8 μm as compared with the central portion. Pressure resistance
In the case of the device of 2500 to 4000 V, the depletion layer 12 (hatched area) extends into the P base layer 5 by y = about 20 μm. When the depletion layer extends and reaches the etching edge, breakdown occurs. From this trial example, it is understood that the trade-off between the resistance value of the separation layer and the breakdown voltage is extremely severe. In order to improve this, it is necessary to flatten the bottom surface of the recess, or to perform etching so that the depth of the bottom end is not deeper than the depth of the central portion.

Next, an embodiment of the present invention will be described by taking the reverse conducting GTO as an example. FIG. 1 is a partial cross-sectional view of the device, which is the same as the conventional reverse conducting GTO shown in FIG. 7 except that the shape of the recess in the isolation region is different.

The reverse conducting GTO substrate has a large GTO region in which the GTO 1 is provided, a region in which the regenerative diode 2 is provided in parallel with the GTO region, and a separation region which serves as a buffer zone for preventing mutual interference between both elements. Be separated.

The GTO 1 has a four-layer structure of a P emitter layer 3, an N ⁻ base layer 4, a P base layer 5 and an N ⁺ emitter layer 6. The N ⁺ layer 4a protruding from a part of the N ⁻ base layer 4 and the P emitter layer 3 are short-circuited by the anode electrode 7,
A so-called emitter short-circuit structure is formed. The N ⁺ emitter layer 6 is formed on the other main surface layer of the substrate with a narrow width in a plurality of divisions, is surrounded by the P base layer 5, and has a structure in which the GTO can be turned on / off by the control voltage of the gate electrode 9. Has become.

The PN junction of the regenerative diode 2 is formed by the P layer 5a and the N ⁻ base layer 4 which are the same as the P base layer 5. The P layer 5a of the diode 2 is connected to the cathode electrode 8 of the GTO via the electrode 8a. The cathode region N ⁻ layer 4 of the diode 2 is connected to the anode electrode 7 of the GTO 1 via the N ⁺ layer 4a.

This reverse conducting GTO has a recess 20 formed in one semiconductor substrate by etching from the main surface of the substrate.
A first semiconductor element (GTO
1), the second semiconductor element (regeneration diode 2), and the bottom end 2 of the depth d from the main surface of the substrate to the bottom of the recess.
The recess 20 in which the depth d ₀ reaching 0a does not become the maximum depth
(That is, d ₀ <d or d ₀ = d).

Next, an embodiment of the method for manufacturing the reverse conducting GTO will be described. First, N having a predetermined specific resistance and thickness
^- Prepare Ha, this silicon wafer - - silicon wafer by diffusing impurities by known methods from one or both sides of the wafer,
P emitter layer 3 and N ⁺ anode short layer 4 shown in FIG.
a, a P base layer 5, an N ⁺ emitter layer 6, and an N ⁺ layer and a P ⁺ layer which are contact layers of the regenerative diode are formed.
In this embodiment, a high-concentration phosphorus diffusion layer is used as the strain layer selectively provided in the recess formation region. Therefore, at the same time when the N ⁺ emitter layer is formed, the N ⁺ layer to be a strained layer is formed.

Next, an etching mask made of SiO ₂ or the like having an opening for forming a recess is formed on the main surface of the wafer having the impurities diffused therein. FIG. 2 is a sectional view of the separation region showing this state. Reference numeral 21 is a mask SiO ₂ film formed on the impurity-diffused wafer, and has an opening 22 for forming a recess. The width w of the opening 22 is, eg, (4-6) mm. Reference numeral 23 is N ⁺ which is a strained layer
A layer is selectively formed in the central region of the periphery of the opening 22 excluding a portion (referred to as an end) having a width of x = about (0.4 to 0.6 mm). An impurity of phosphorus is diffused at a surface concentration of about 10 ²⁰ cm ^-3 to a depth of about 20 μm, which is about the same as the N ⁺ emitter layer 6, to form a strained layer.

Next, when wet etching is performed using a mixed solution of nitric acid, hydrofluoric acid, etc., a recess 20 is formed as shown in FIG. N ⁺ layer 2 with high concentration of phosphorus diffused
The etching rate of No. 3 is faster than the etching rate of the end portion 20a where phosphorus is not diffused. N ^{+ of} recess 20
When the etching depth d from the substrate surface in the central region including the layer 23 is 30 μm, the etching depth d ₀ of the end portion 20a is about 25 μm. That is, 5 μ between the portion where N ⁺ impurities are diffused and the portion where N ⁺ impurities are not diffused
There is a difference in etching depth of about m. Therefore, when the end portion is not strained and the center portion is strained, the end portion is not deeply etched as compared with other bottom surfaces as in the conventional example (for example, FIG. 7).

The reverse conducting GTO shown in FIG. 1 is obtained by a known conventional method such as forming a shallow mesa groove for a gate electrode by mesa etching.

As described above, in the conventional technique, when a recess having a width of several mm and an etching depth of several tens of μm is formed, the end portion is etched deeper than the central portion, and the separation layer (P directly below the recess portion is formed).
When the depletion layer extends into the base layer and reaches the etching end, the breakdown voltage is destroyed. On the other hand, in the embodiment of the present invention, the bottom surface of the recess is not deeply etched at the end portion as compared with the central portion, so that the depletion layer is less likely to reach the bottom surface of the recess as compared with the conventional example, and the breakdown voltage can be increased accordingly. The thickness of the separation layer in the central portion can be reduced and the resistance R of the separation layer can be increased while keeping the above condition. That is, the separation layer resistance R
The trade-off between pressure resistance and withstand voltage was eased, and the product yield was significantly improved.

4 and 5 are cross-sectional views showing another embodiment of the recess forming method. FIG. 4 shows a step corresponding to FIG. 2 and is divided into a plurality of recess forming etching openings 32. High concentration N ⁺ layer (strained layer) 33a, 33b,
33c, 33d and 33e are provided. FIG. 5 shows a cross section of the recess 30 after etching. The depth from the substrate surface to the bottom of the recess is deep in the region including the strained layer and shallow in the region without the strained layer, and the plane distribution of the strained layer provided in advance enables fine control of the resistance value of the separation layer. .

This method is not limited to the reverse conducting GTO,
It can be used when deeply etching a wide area of a recess.

In the above embodiment, the strained layer is formed by diffusing high concentration impurities such as phosphorus, but the present invention is not limited to this. For example, a strained layer may be formed by implanting fine particles with honing, a particle accelerator, or the like.

In the above embodiment, the N ⁺ layer (strained layer) 2
No. 3 was formed simultaneously with the formation of the N ⁺ emitter layer 6 of GTO, and the effect could be obtained without increasing the number of process steps, but separately from before or after the formation of the N ⁺ emitter layer 6. There is no problem even if an N ⁺ layer having a desired concentration is formed.

In the above embodiment, G is used as the first semiconductor element.
Although TO was used as a second semiconductor element and a regenerative diode as a constituent element, the present invention can be applied even if the first semiconductor element is a power control element such as G-Tr, and the second semiconductor element is a passive element. It may be an element.

[0043]

INDUSTRIAL APPLICABILITY The present invention is directed to reverse conduction GTO and reverse conduction GT.
In a composite semiconductor device with a wide and deep recess such as r,
The distribution of the etching depth of the recess can be easily controlled, and the depth of the bottom end of the recess is prevented from being deeper than that of the central portion. According to the present invention, it is possible to provide a composite semiconductor device capable of improving the trade-off relationship between the resistance of the isolation layer immediately below the recess and the breakdown voltage of the device and significantly improving the yield, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is an embodiment of a semiconductor device of the present invention (reverse conduction GTO).
FIG.

FIG. 2 is a cross-sectional view of the reverse conducting GTO shown in FIG. 1 showing a separation region forming step.

FIG. 3 is a sectional view of the region showing a step following FIG. 2;

FIG. 4 is a cross-sectional view of the separation region showing another embodiment of the process.

5 is a sectional view of the region showing a step following FIG. 4; FIG.

FIG. 6 is an enlarged cross-sectional view of an isolation region of a reverse conducting GT0 according to the related art.

FIG. 7 is a partial cross-sectional view of a conventional reverse conducting GTO.

FIG. 8 is a partially cutaway perspective view of a separation layer of a reverse conducting GTO.

FIG. 9 is a characteristic diagram showing a trade-off relationship between resistance and resistance of a separation layer.

FIG. 10 is a sectional view of another example of a conventional isolation region.

FIG. 11 is a cross-sectional view showing another example of a conventional isolation region.

[Explanation of symbols]

1 GTO 2 Regenerative Diode 3 P Emitter Layer 4 N ^- Base Layer 4a Anode Short Layer 5 P Base Layer 5a Diode P Layer 5b Separation Layer 6 N ⁺ Emitter Layer 7 Anode Electrode 8 Cathode Electrode 9 Gate Electrode 10, 20 Recess 20a End of recess 21 Oxide film for mask during etching 22 Opening for forming recess 23 N ⁺ layer (strained layer)

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Akira Yanagisawa 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Tamagawa factory

Claims (2)

[Claims] 1. A method of manufacturing a composite semiconductor device, wherein a first semiconductor element and a second semiconductor element are formed on a single semiconductor substrate so as to be separated from each other via recesses dug from the main surface of the substrate Before the formation, a strained layer which does not come into contact with the side wall of the recess forming region of the substrate is selectively formed in the region, and then the strained layer is etched from the main surface of the substrate to form the recess. Manufacturing method of semiconductor device. 2. A first semiconductor element and a second semiconductor element formed on one semiconductor substrate so as to be separated from each other through a recess dug from the main surface of the substrate, and a depth from the main surface of the substrate to the bottom surface of the recess. A semiconductor device comprising: a recess whose depth reaching the bottom end of the recess is not the maximum.