JPH0783369B2 - Ring transmission system - Google Patents

Description

The present invention relates to a transmission system for a ring-shaped local area network, and is particularly suitable for a multimedia integrated LAN providing various speed channels from high speed to low speed. Regarding transmission method.

[Background of the Invention]

Conventionally, the transmission method of a ring network that integrates multimedia is based on STDM (Synchronous Ti
me Division Multiplex) and the frame length is discussed in a document entitled "C & C-NET Loop 6830 Universal Link System" by Ito et al. in NEC Technical Report Vol.36 No.7 1983. Like to make it long enough to accommodate the slowest terminal (synchronous type),
Or set the basic transmission unit to a certain high level (for example, 64 Kb / s) as discussed in the article entitled "OKINET-2000 MODEL30" by Takahashi et al. In Oki Electric R & D No. 124 Vol.51 No.3 1983. It is said that the basic transmission unit is occupied and transmitted for a length less than that and for a length less than that. It is thought that this depends on what speed terminal is accommodated mainly, but in the former case it is more suitable for accommodating low speed terminals because it has better accommodation efficiency but increases transmission delay, while in the latter case it accommodates low speed terminals. Although it is inefficient, it is suitable for accommodating high-speed terminals because the transmission delay is short.
However, no consideration was given to a transmission method that was excellent in accommodation efficiency and transmission delay.

[Object of the Invention]

An object of the present invention is to provide a transmission method for a ring network that has a high accommodation efficiency for low-speed terminals and a short transmission delay.

[Outline of Invention]

The present invention focuses on the fact that information transmission between arbitrary stations is possible if there is a transmission channel that orbits the master station twice, and the low-speed channel has a multi-frame structure and is formed with the same slot extending over two frames. It was done like this.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. First
The figure shows an example of transmission time chart in a ring transmission system to which the present invention is applied, and the features of the present invention are shown. Here, the vertical axis represents the physical position of the transmission device, and the horizontal axis represents the passage of time. In this example, the transmission devices A and B are transmitting low-speed information, and transmission management devices are arranged at the most upstream and downstream positions in the figure. The information transmitted from the transmission management device is a repetition of a frame composed of a plurality of transmission units called time slots as shown in the figure. The length of the frame is kept constant, and the transmission device uses this time slot to transfer information. It is known that such a transmission method facilitates integrated transmission of various traffic characteristics. That is, when the transfer information is generated in a fixed amount and in a fixed cycle, it is possible to occupy the empty time slot by the transfer amount and transmit it. However, as the transmission speed increases, the transmission amount per unit increases, so it becomes difficult to provide a low-speed transmission unit while keeping the frame length suppressed. Therefore, a multi-frame configuration as shown in the figure is adopted, and the same time slot that spans two frames (in this example, the adjacent case is shown) is assigned to one low-speed transmission unit. In the case of the conventional method, it is sufficient to use only the frames having the same number. But for the amount of delay,
Compared to the conventional method that requires multiple frames, only one frame is required, and it can be seen that the characteristics can be greatly improved.

It should be noted that in high-speed information transfer, it is sufficient to identify only the time slot number without being aware of multi-frames and therefore frame numbers.

According to the conventional method, when performing transmission in high-speed transmission units, the amount of transmission per unit time increases, and it is necessary to increase the length per frame. In this case, if low-speed transmission is mixed, it is necessary for the transmission management device to hold low-speed information for many delays, but in the transmission system of the embodiment of the present invention, only one frame is required.

FIG. 2 is an example of the overall configuration of a ring transmission system to which the present invention is applied. As shown in the figure, various information processing devices 21 to 31 distributed and installed in various places in the factory, building, university campus, etc., join one transmission system via the transmission devices 11 to 16 to exchange information with each other. The devices are connected in a ring by a bit-serial transmission line 3. It should be noted that the figure shows an example in which there are four transmission devices and two or four information processing devices are connected to each transmission device, but the present invention does not limit the number thereof.

The information processing devices connected to the transmission device are roughly classified into the following two types according to the characteristics of the transmission traffic.

1) Type 1: Those requiring strict immediacy and data transmission with a long hold time.

2) Type 2: Immediateness is not required so much, and data transmission is performed with a relatively short holding time. Type 1 in the figure
ITV camera 26, monitor 28, telephone 25, 29, FA
X22, PBX (Private Branch Exchange) 23, type 2 remaining computers 24, PCs 27 via LAN (Local Area Network), filtering device 30, printer 31, printer 31,
Although the workstation 21 is mentioned, it is possible to handle the information transfer with different traffic characteristics in a mixed manner on the same line. Generally, it is well known that the former type of information is suitable for circuit switching (including dedicated allocation) and the latter is suitable for packet switching. A network in which both can be mixed is called a hybrid switching network. The present invention describes a transmission method for accommodating particularly low-speed circuit-switched terminal-to-terminal communication.

FIG. 3 shows an example of the format of information flowing through the ring transmission line. FIG. 3A shows the entire transmission format which adopts a multi-frame structure. The number of frames N is usually determined by the slowest transmission unit.

Each frame has a form in which a frame header is added to the head of a plurality of time slots as shown in FIG. Each time slot has the same length and is used for data transfer. The frame header section is used for synchronization and transmission control.

The frame header adopts the format shown in c) of the figure, and each area is used for the following purposes.

SYN: Indicates the beginning of the frame. Each transmission device detects this and adopts frame synchronization. It is realized by a fixed bit pattern or bio-modulation with modulation / demodulation.

NO: A number indicating the frame order on the multi-frame. It is necessary to recognize this in transmission between low speed terminals, but it is not necessary between high speed terminals.

AC: A bit that indicates whether the time slot in the frame can be used for transmission. This is also effective only in the low-speed transmission unit, and when the result is no, it indicates that the slot in the frame is the second round of the transmission path.

LNG: Indicates the distance (number of frames) between two time slots, which are low-speed transmission units. This is determined by the signal loop delay of the ring transmission line.

Each time slot is a format shown in Fig. 3 (d) and each area is used for the following purposes.

F / B: Indicates whether or not the time slot is empty. Prior to transmission, this bit must be made busy to occupy the time slot for transmission between certain terminals.

M: Indicates whether or not there is data information in the time slot. This bit is set when the data information is transmitted, and the time slot resets after one round of the transmission path. Refer to the corresponding receiver.

DATA: Put data information in this area.

FIG. 4 shows an example of the hardware configuration of the transmission device. Of the transmission devices, only one station operates as a transmission management device at the same time, but the hardware configurations and functions are all the same. Therefore, transmission management can be backed up by all transmission devices. The method of selecting one management device from a plurality of transmission devices is usually based on the unique priority given to each device, but the description is omitted here. Transmission device 11 is transmission line 3
Correspondingly, one line control module 110 and an interface module 111 corresponding to an information processing device (for example, 22) are configured. Since the two modules are connected via two sets of data transfer buses INBUS and OUTBUS, the transmission device structure has a wide spread of scale. Line control module 11
0 further consists of the following components.

1) Receiving circuit (1101) This is a circuit for receiving a signal from a transmission line and returning it to digital information, and has the following functions.

a) optical reception module b) bit synchronization circuit c) timing conversion circuit d) demodulation circuit e) serial / parallel conversion circuit 2) transmission circuit (1102) A circuit that converts digital transmission information into a signal suitable for a transmission line and transmits the signal. , And consists of the following functions.

a) optical transmission module b) modulation circuit c) parallel / serial conversion circuit 3) multiplexer (1103) output from frame delay circuit 1104 and frame generation circuit 11
Select and output 05 output. Switching is required when the transmission device 11 functions as a transmission management device, but when it functions as a normal transmission device, only the frame delay circuit 1104 is fixedly selected.

4) Frame delay circuit (1104) When the transmission device 11 functions as a transmission management device, the memory (RAM) therein adjusts the signal round-trip delay of the annular transmission line to be an integral multiple of the transmission frame. . In a normal transmission device, it acts as a mere register and no delay is inserted.

5) Frame generation circuit (1105) When the transmission device 11 operates as a transmission management device, it executes generation of a frame header and an empty time slot. Since it is a part directly related to the present invention, its details will be described later.

6) Bus control circuit (1106) An amount equivalent to the operation delay time of the time slot access circuit 1111 is inserted in the relay path from INBUS to OUTBUS to enable the interface module to send and receive information on the bus. In addition to this, it manages bus contention management and bus control such as timing supply.

The interface module 111 is composed of the following functional parts.

1) Time slot access circuit (1111) This circuit performs functions such as identifying a frame, occupying / releasing a time slot, and passing information by the occupied time slot, and is directly related to the present invention. Details will be described later.

2) Transmission control circuit (1112) Here, transmission / reception buffer management of transfer information, various transmission error checks, disassembly / assembly of transfer data into time slots, and other transmission / reception control are executed.

3) Device interface circuit (1113) Controls various interfaces between the interface module 111 and the information processing device 22.

Next, the flow of information in the ring-shaped transmission device composed of these components will be described.

When the transmission device 11 operates as a transmission management device, the frame information from the frame generation circuit 1105 is sent to the multiplexer 11
03, it is sent to the transmission line 3 via the transmission circuit 1102. The information that has passed through the transmission path is output to INBUS via the receiving circuit 1101, passes through the bus control circuit 1106, and is output.
It will enter the BUS and then the frame delay circuit 1104.

In the receiving operation, the information output to INBUS via the receiving circuit 1101 is the time slot access circuit 1111, the transmission control circuit.
1112, and is passed to the information processing device 22 via the device interface circuit 1113.

Similarly, the transmission operation follows the reverse path and is output from the time slot access circuit 1111 to OUTBUS. At this time, output from the bus control circuit 1106 to OUTBUS is prohibited. And a frame delay circuit 1104, a multiplexer 1103, a transmission circuit
It is output to the line through 1102.

FIG. 5 shows a more detailed hardware configuration of the frame generation circuit 1105. This circuit is functionally roughly divided into a frame header generation circuit 11050 and a time slot generation circuit 11051.

The frame header generation circuit 11050 further includes the following components.

1) SYN register (110501) This register stores the frame synchronization pattern.

2) NO register (110502) A register for temporarily storing the contents of the frame counter 110507.

3) AC pattern ROM (110503) RO that stores access permission bits issued for each frame
M. Frame counter 11050 for addressing this memory
Subtractor 11050 showing the output of 7 and the signal delay of one round of the circular transmission line
Use the output of 8.

4) LNG register (110504) This is a register that stores inter-frame distance information and is a subtractor 11
Store the output of 0508.

5) Dummy register (110505) A register for transmitting the remaining dummy information of the frame header.

6) Time slot counter (110506) A counter for counting the number of time slots to be transmitted. Outputs once when counting for one frame.

7) Frame counter (110507) A counter that indicates the transmission frame number. The current count value
NO register 110502, AC pattern ROM 110503, subtractor 110508
Supply to.

8) Subtractor (110508) Outputs the difference between the transmission frame number and the reception frame number as an absolute value. This value indicates the amount of delay for one round of the circular transmission line, and is used for presentation of the inter-frame distance in low-speed transmission units.

9) NO storage register (110509) This register stores the number of the frame being received and outputs the value to the subtractor 110508.

On the other hand, the time slot generation circuit 11051 comprises the following components.

1) Time slot generation register (110511) This register stores an empty time slot pattern.
In case of time slot for low speed transmission unit, free / busy bit is supplied from F / B delay RAM 110512.

2) F / B delay RAM (110512) A memory for delaying the free / busy bit in the slot by multiple frames when the time slot for low-speed transmission unit is received.

3) F / B cutout circuit (110513) Free / free from within the received low-speed transmission unit time slot
Circuit for cutting out busy bits.

When the transmission device 11 operates as a transmission management device, this circuit
Having described that the 1105 functions, the operation flow in that case will be described below.

As shown in the transmission format example of FIG. 3, initially the contents of SYN register 110501 are selected by multiplexer 11052. Following that, NO register 110502, AC pattern
The ROM 110503, LNG register, and dummy register 110505 are sequentially selected and the frame header is output. After that, the contents of the time slot generation register 110511 are output for the time slot in the frame to complete one frame. After that, this is repeated.

FIG. 6 shows an AC pattern ROM 11050 in the frame generation circuit 1105.
3 is an example of an access permission bit pattern stored in FIG. This example shows a case where the number of frames in the multiframe is set to 24. In the vertical direction, the inter-frame distance of the low-speed transmission unit is taken, and accordingly, the signal round trip delay time of the annular transmission line is taken, and in the horizontal direction, the frame number in the multiframe is shown.

Although the inter-frame distance changes according to the system scale, the maximum value is suppressed to 3 here. In the system shown in the transmission time chart of FIG. 1, the distance between frames is O,
That is, since the same time slot in adjacent frames constitutes a low-speed transmission unit, the AC bit of the frame header output from the transmission management station is 1010. This indicates that the time slot of the odd-numbered frame may be used for transmission.

The operation of the system shown in the time chart of FIG. 1 will be further described below. In the time chart of FIG. 1, a case where the transmission device C exists between the transmission devices A and B will be described as an example. Transmission device A transmits first and this
When the transmission ends after one transfer and then the transmission device C transmits using the same area, the frame # 1 of the first multiframe generated by the transmission management device, TSi, is F (free).
It was. As described above, since the odd-numbered frames (frame # 1, frame # 3, ...) Are displayed as being transmittable, the transmission apparatus A sets F (free) of this TSi to B.
Change to (busy) and send data. As a result, the transmission device downstream of A cannot transmit data by this TSi. When this TSi arrives at the transmission management device, it is delayed for a certain period of time, and its contents are transmitted in the TSi of frame # 2, and the F / B (now B) of this TSi corresponds to multiple frames (that is, the next frame). It is transmitted after being kept waiting (up to TSi of frame # 1). TSi of frame # 2 of the previous multi-frame
The contents sent to the transmission device A are erased when they are returned to the transmission device A (B
Back to F). As a result, the data sent from the transmission device A is the TSi of frame # 1 in the transmission device downstream of A,
The transmission device upstream of A receives the packet with TSi of frame # 2. Although TSi of frame # 2 is F (free), it is not used for transmission even if a transmission request is made by a transmission device downstream of A. This is because the A / C bit in the frame header is disabled. On the other hand, the TSi of the frame # 1 of the next multi-frame
The TS of B (busy) sent from the transmission management device at 1 is returned to F (free) by the transmission device A, and the transmission device downstream of A can use it for transmission.

FIG. 7 shows the detailed hardware configuration of the time slot access circuit 1111 in the interface module 111.

Information received from INBUS is supplied to a reception register 111101, a slot header decoder 111102, an AC detection circuit 111103, an LNG register 111104, and a NO register 111105. The reception data to the transmission control circuit 1112 is sent via the reception register 111101.

The slot occupancy detection circuit 11 detects the header pattern of each time slot of the slot header decoder 111102 and outputs the result.
1125, transmission slot detection circuit 111124, loop slot detection circuit 111123, and reception slot detection circuit 111122.

The AC detection circuit 111103 detects an access permission bit in the frame header and transmits the result to the slot occupation detection circuit 111125.

The LNG register 111104 stores inter-frame distance information in the frame header. The output is sent to the adder 111109, and is used for indexing the frame that makes a pair with the occupied frame.

The NO register 111105 stores information on the currently received frame number. The output is the receive frame register 1111.
07, transmission frame register 111106, comparator 11110
Supplied to 8,111112.

The transmission frame register 111106 is a frame number including a time slot used for transmission, the pair frame register 111110 is a frame number to be paired with the transmission frame, and the reception frame register 111107 is a frame number including a time slot used for reception. It is used to store each. Whether or not the frame currently being received is the corresponding frame is determined by the comparators 111112 and 111108, respectively.
It is judged by. Since the numbers of the transmission frame and the pair frame are not the same, each comparison is checked by switching to the time division by the multiplexer 111111.

For time slot, slot counter 111118
At this time, the current time slot number is counted, and the numbers used for transmission and reception are stored in the transmission slot register 111114 and the reception slot register 111116, respectively. Each of the comparators 111115 and 111117 determines whether or not the time slot currently being received matches the stored value.

On the other hand, the received data from the transmission control circuit 1112 is output to OUTBUS via the multiplexer 111119 and the transmission register 111118. In addition to this, there is a slot header hex 111121 for sending the slot header information, and the slot header register.
The multiplexer 111119 becomes the other input via the 111120.

Between the time slot access circuit 1111 and the transmission control circuit 1112, there are the following signals in addition to the transmitted / received data.

From the transmission control circuit 1112 to the time slot access circuit 1111
Send request, end transmission, and detect command addressed to own station.

In the reverse direction, slot occupancy, transmission start, reception start, and reception end.

The slot occupancy detection circuit 111125 is for notifying after transmitting the transmission request after occupying the slot, and an occupancy output is output when a free time slot is received in the frame with an accessible bit. This signal is also transmitted to the slot header coder 111121, which changes the transmission time slot to busy. It also serves as a signal stored in the transmission frame register 111106 and the pair frame register 111110.

The transmission slot detection signal 111124 is in the middle of transmission, and notifies that the time slot to be used has been detected and starts transmission. In addition, the slot header coder 111121 is instructed to send data that is busy. The judgment of detection requires that the frame number and the time slot number match and that the time slot is busy. If the time slot is free, an error occurs and the transmission is stopped. When the transmission end signal is received, the slot header coder 111121 is instructed to cancel the occupation of the time slot.

During transmission, the one-round slot detection circuit 111123 detects that the time slot has reached one cycle after transmission, and instructs the slot header coder 111121 to send no data.

The reception slot detection circuit 111122 notifies that the time slot to be used is detected during reception, as reception start. If the time slot is in the free state, it is determined that the transmission is completed and the reception end signal is output.

〔The invention's effect〕

According to the present invention, even if a multi-frame structure is adopted, a transmission delay of one frame is sufficient, and there is an effect that a low-speed terminal can be accommodated efficiently.

[Brief description of drawings]

FIG. 1 is an example of a transmission time chart showing the features of the present invention, FIG. 2 is an example of the entire configuration of a ring transmission system, FIG. 3 is an example of a transmission format, FIG. 4 is an example of the hardware configuration of a transmission device, and FIG. Is an example of the hardware configuration of the frame generation circuit,
FIG. 6 is an example of an access permission bit pattern, and FIG. 7 is a hardware configuration diagram of the time slot access circuit. 3 ... Transmission line, 11-16 ... Transmission device, 21-31 ... Information processing device, 110 ... Line control module, 111 ... Interface module, 1101 ... Reception circuit, 1102 ... Transmission circuit, 1103 ...... Multiplexer, 1104 ...... Frame delay circuit, 1105 ...... Frame generation circuit, 1106 ...... Bus control circuit, 1111 ...... Time slot access, 1112 ...... Transmission control circuit, 1113 ...... Device interface circuit, 11050
...... Frame header generation circuit, 11051 ...... Time slot generation circuit, 110501 ...... SYN register, 110502 ...... NO register, 110503 ...... AC pattern ROM, 110504 ...... LNG register, 110505 ...... dummy register, 110506 ...... Time slot Counter, 110507 ... frame counter, 110508 ...
… Subtractor, 110509 …… NO storage register, 110511 …… Time slot generation register, 110512 …… F / B delay RAM, 1105
13 …… F / B cutout circuit, 11052 …… Multiplexer, 1111
01 …… Receive register, 111102 …… Slot header decoder, 111103 …… AC detection, 111104 …… LNG register, 11110
5 …… NO register, 111106 …… Send frame register, 1
11107 ... Reception frame register, 111108,111115,11111
7,111112 …… Comparator, 111109 …… Adder, 111110
…… Pair frame register, 111111, 111119 …… Multiplexer, 111113 …… Slot counter, 111114 …… Transmit slot register, 111116 …… Receive slot register, 111118 …… Transmit register, 111120 …… Slot header register, 111121 …… Slot Hezda Coda, 111122
...... Reception slot detection circuit, 111123 …… One-round slot detection circuit, 111124 …… Transmission slot detection circuit, 111125 ……
It is a slot occupation detection circuit.

Front page continued (72) Inventor Seiichi Yasumoto 52-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Omika Factory, Ltd. (72) Inventor Masakazu Okada 5-2 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Incorporated company Hitachi Ltd. Omika factory (56) Reference JP-A-57-168552 (JP, A)

Claims (2)

[Claims] 1. A plurality of information processing devices, a transmission device that accommodates the information processing devices and executes information transfer, and a transmission that generates a transmission frame of a fixed length composed of a plurality of time slots for transferring information between the transmission devices. In a ring-shaped transmission system comprising a management device and a ring-shaped transmission line connecting these in a ring, the transmission management device configures a transmission frame so as to have a multi-frame structure composed of a plurality of frames each having a series of numbers. Each frame having the multi-frame structure has control information indicating whether or not the frame can be transmitted, and the information transferred between the transmission devices is between one frame. A first transmission unit that can be transmitted once, and a second transmission unit that can be transmitted once during one multiframe at a speed lower than that of the first transmission unit.
The transmission management device comprises means for adjusting a predetermined inter-frame distance, which is a time required for a frame to make a round in a circular transmission path, to an integral multiple of the transmission frame length, and whether the frame can be transmitted. The control means has setting means for setting the control information indicating whether or not the frame is an odd number of rounds of transmission, and is an even number of frames of which transmission is not possible. The transmission device, which periodically transmits in a time slot at a predetermined fixed position in a frame, has a predetermined inter-frame distance in the multi-frame.
A circular transmission system, wherein the second transmission unit is transmitted by occupying a time slot at the same position in a pair of frames that spans one frame. 2. The frame according to claim 1, wherein the frame has identification information indicating whether or not there is data in a time slot used for transmission of the second transmission unit, and the transmission management device A unit for delaying time slot occupancy information indicating whether or not a time slot used for transmission of the second transmission unit is empty by the multiframe length, the second transmission unit being fixed to a predetermined value within a frame. When transmitting data using the time slot, the transmission device that periodically transmits the time slot at the position sets the identification information to “with data”, and the time slot at the same position of the pair of frames comes. In the ring transmission system, the time slot is set to have no data.