JPH0794739A - Field effect transistor having quantum box and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Object] To provide a field effect transistor (FET) having a quantum box and capable of achieving a high degree of integration by applying a Mott transition (metal-insulator transition), and a manufacturing method thereof. The FET is composed of (a) substrate 10, (b) a plurality of quantum boxes 18 formed thereon, barrier layer 16, and two-dimensional conductive layer 24 formed on the barrier layer. The channel region, (c) the gate electrode 32, (d) the source / drain regions 34, and the source / drain electrodes 40. The FET manufacturing method is as follows: (a) A plurality of semiconductor crystal grains 1 are formed by heat-treating the semiconductor raw material layer 12 formed on the substrate.
4 is formed, the surfaces thereof are oxidized to form a barrier layer 16 made of an oxide film to form a quantum box 18 made of semiconductor crystal grains, and (b) a semiconductor raw material formed above the quantum box. The layer 22 is subjected to a heat treatment to form a two-dimensional conductive layer 24, and a channel region forming step is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a quantum box and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in quantum wave electronics, attention has been paid to a hyperfine structure having a cross-sectional dimension similar to the de Broglie wavelength of electrons, that is, a so-called quantum box or a quantum box assembly element which is a collection of a plurality of quantum boxes. Therefore, there is great interest in the quantum effect exhibited by the zero-dimensional electrons confined in this quantum box. In the quantum box assembly element, for example, electrons can move between adjacent quantum boxes by tunneling, and the effect of Coulomb interaction between electrons becomes remarkable due to zero-dimensional quantum confinement.

It is predicted that when one electron is supplied to each quantum box, Mott transition (metal-insulator transition) occurs due to Coulomb interaction between electrons. That is, consider a quantum box assembly element in which quantum boxes having a size of about 10 nm are arranged with a distance of about 5 nm. The transfer energy between the quantum boxes in such a system has a certain value (for example, about 10 meV), and metallic conduction occurs in a region where the electron density is low. However,
When the electron density rises to a density of one electron per quantum box (half field), each electron is confined in each quantum box due to Coulomb interaction between electrons, and cannot conduct. This phenomenon is called Mott insulator. This state can be considered as a state in which electrons are packed in the low energy side of the subbands separated by the Hubbard gap. On the other hand, when the electron density exceeds the half field, the high energy side of the subband separated by the Hubbard gap is clogged with electrons, and the metallic conduction becomes possible again.

[0004]

A field effect transistor (FE) is one of the application fields of such a quantum box assembly element.
T) is considered. A source / drain current flowing in the channel region is formed by forming a quantum box assembly element in the channel region of a field effect transistor and controlling the conduction of the channel region by controlling the movement of electrons or holes in the quantum box assembly element. It is possible to control

At present, a quantum box assembly element, which is an assembly of a plurality of quantum boxes, is mainly made of a compound semiconductor material. This quantum box assembly device is a system that realizes electron confinement by a heterojunction of compound semiconductors. The reason why the compound semiconductor material is used is that not only the crystallinity and homogeneity of the formed compound semiconductor layer have been improved by the progress of the epitaxial growth technology of the compound semiconductor such as the molecular beam epitaxy technology or the MOCVD technology, but also the sharpness is improved. It relies heavily on the ability to form heterojunctions. These crystal growth techniques are premised on growing a crystal layer made of a compound semiconductor material on a single crystal substrate made of a compound semiconductor material.

At present, most field effect transistors use Group IV elements such as silicon as their constituent materials. Therefore, a field effect transistor having a quantum box using a group IV element such as silicon as a constituent material is desired in terms of stability of material characteristics. Further, there is a strong demand for a technique for manufacturing a high-performance field-effect transistor with a high degree of integration on a large-area substrate, such as a field-effect transistor for control of LCD or the like.

An isolated quantum box having a size of about 10 nm in which the quantum effect becomes remarkable is conventionally manufactured by using electron beam exposure. For example, MN Reeds, et al.,
See Phys. Rev. Lett. 60, 535 (1988). Regarding electron beam exposure, for example, AN Broers,
See et al., Appl. Phys. Lett. 29, 596 (1976). However, the limit of the resist pattern interval by the conventional electron beam exposure is 5 due to the proximity effect of the electron beam.
It is about 0 nm. Therefore, it is extremely difficult to manufacture an extremely highly integrated quantum box assembly element in which the quantum box spacing is close to about 5 nm by the existing technique.

Therefore, an object of the present invention is to have a quantum box,
An object of the present invention is to provide a field effect transistor that can achieve a high degree of integration by applying a Mott transition (metal-insulator transition) and a manufacturing method thereof. Further, an object of the present invention is to provide a field effect transistor having a quantum box which does not have a heterojunction and which can use a widely used group IV element-based material as a constituent material, and a manufacturing method thereof. is there. A further object of the present invention is to provide a method capable of producing a high-performance field effect transistor with a high degree of integration on a large-area substrate.

[0009]

A field-effect transistor according to a first aspect of the present invention for achieving the above object comprises: (a) a substrate; and (b) a plurality of quantum boxes formed on the substrate. A channel region composed of a barrier layer formed between the quantum boxes and on the quantum boxes, and a two-dimensional conductive layer formed on the barrier layer, and (c) a gate electrode provided in the channel region. And (d) a source / drain region formed at both ends of the channel region, and a source / drain electrode provided in the source / drain region. In the field effect transistor according to the first aspect, an interlayer insulating layer can be further formed between the barrier layer and the two-dimensional conductive layer.

A second aspect of the present invention for achieving the above object.
The field effect transistor according to the aspect of
(B) A two-dimensional conductive layer formed on a substrate, an interlayer insulating layer provided on the two-dimensional conductive layer, a plurality of quantum boxes provided on the interlayer insulating layer, between these quantum boxes, and A channel region composed of a barrier layer formed on the quantum box, and (c)
It is characterized by comprising a gate electrode provided in the channel region, (d) a source / drain region formed at both ends of the channel region, and a source / drain electrode provided in the source / drain region.

In the field effect transistors according to the first and second aspects of the present invention, it is desirable that the quantum box is made of crystal grains of group IV element. Silicon can be used as the group IV element. Further, the barrier layer preferably comprises silicon dioxide. The two-dimensional conductive layer can be composed of silicon crystal grains. The substrate preferably comprises a transparent material. Further, the quantum box or the two-dimensional conductive layer preferably has a doping concentration capable of confining one electron or hole per one quantum box.

A first aspect of the present invention for achieving the above object
The method for manufacturing the field effect transistor according to the aspect of
(A) After forming a semiconductor raw material layer on a substrate and then subjecting this semiconductor raw material layer to heat treatment to form a plurality of semiconductor crystal grains, the surface of each of these semiconductor crystal grains is oxidized to form an oxide film. A step of forming a quantum box made of semiconductor crystal grains separated from each other by a barrier layer made of an oxide film, and (b) forming a semiconductor raw material layer above the quantum box and then heat treating the semiconductor raw material layer. And a channel region forming step of forming a two-dimensional conductive layer made of semiconductor crystal grains. in this case,
After the step (a), a step of forming an interlayer insulating layer on the barrier layer can be included.

A second aspect of the present invention for achieving the above object.
The method for manufacturing the field effect transistor according to the aspect of
(B) a step of forming a semiconductor raw material layer on the substrate and then heat treating the semiconductor raw material layer to form a two-dimensional conductive layer made of semiconductor crystal grains; and (b) an interlayer insulating layer on the two-dimensional conductive layer. And (c) forming a semiconductor raw material layer on the interlayer insulating layer, and then subjecting the semiconductor raw material layer to heat treatment to form a plurality of semiconductor crystal grains, The surface is oxidized to form an oxide film,
And a channel region forming step of forming quantum boxes made of semiconductor crystal grains separated from each other by a barrier layer made of an oxide film.

In the method of manufacturing the field effect transistor according to the first and second aspects of the present invention, the semiconductor raw material layer can be composed of a group IV element. Polysilicon can be used as the semiconductor raw material layer. The substrate preferably comprises a substrate or insulating layer that can withstand heat treatment. The heat treatment can be laser annealing treatment. Further, the semiconductor raw material layer for forming the quantum box or the semiconductor raw material layer for forming the two-dimensional conductive layer is doped with a concentration that can confine one electron or hole per one quantum box. Is preferred.

[0015]

In the field effect transistor of the present invention, the movement of electrons or holes by tunneling between the plurality of quantum boxes and the two-dimensional conductive layer formed above or below the quantum boxes is controlled by the gate electrode. When electrons or holes are drawn to the two-dimensional conductive layer, the two-dimensional conductive layer exhibits a metallic behavior, and source / drain currents flow in the channel region. On the other hand, when electrons or holes are trapped in the quantum box, the two-dimensional conductive layer behaves as an insulator,
No source / drain current flows in the channel region. In the state where one electron or hole is trapped per quantum box, the decrease in electrical conductivity is the largest, and the source / drain current flow in the channel region can be controlled most effectively.

In the method of manufacturing the field effect transistor of the present invention, the semiconductor raw material layer is heat-treated to form a plurality of semiconductor crystal grains. Since the size of the semiconductor crystal grain depends on, for example, the thickness of the semiconductor raw material layer, if the thickness of the semiconductor raw material layer is reduced, extremely fine semiconductor crystal grains can be formed. Then, since each surface of the semiconductor crystal grains is oxidized to form an oxide film, quantum boxes made of semiconductor crystal grains are formed which are separated from each other by a barrier layer made of a thin oxide film. That is, it becomes possible to fabricate a field effect transistor composed of a plurality of fine quantum boxes in which the quantum boxes are very close to each other through a barrier layer made of a thin oxide film. With such a structure, a quantum box can be manufactured without forming a heterojunction.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The field effect transistor of the present invention and the method for manufacturing the same will be described below with reference to the drawings.

Example 1 Example 1 relates to a field effect transistor according to the first aspect of the present invention and a method for producing a field effect transistor according to the first aspect. The field-effect transistor of Example 1 has one layer composed of a plurality of quantum boxes (hereinafter also referred to as quantum box layer), and has a two-dimensional conductive layer thereon. The semiconductor raw material layer is composed of polysilicon. The substrate is made of glass, which is a material that can withstand heat treatment. Furthermore, the heat treatment is a laser annealing treatment.

FIG. 1A shows a schematic partial sectional view of the field effect transistor of the first embodiment. Specifically, this field effect transistor includes (a) a substrate 10 made of glass, (b) a quantum box 18 made of a plurality of silicon crystal grains formed on the substrate 10, and between the quantum boxes. Barrier layer 1 made of silicon dioxide formed on a quantum box
6 and a two-dimensional conductive layer 24 made of silicon crystal grains formed on the barrier layer,
(C) Gate electrode 32 provided above the channel region
And (d) a source / drain region 34 formed at both ends of the channel region, and a source / drain electrode 40 provided in the source / drain region 34. In the field effect transistor of Example 1, the barrier layers 16 and 2
An interlayer insulating layer 20 is further formed between the dimensional conductive layer 24.

A method of manufacturing the field effect transistor of Example 1 will be described below with reference to FIGS. 2 and 3.

[Step-100] First, the semiconductor raw material layer 12 is formed on the substrate 10. That is, the semiconductor raw material layer 12 made of polysilicon is formed on the substrate 10 made of glass by, for example, the CVD method (see FIG. 2A). Since the thickness of the semiconductor raw material layer 12 defines the size of the quantum box, the thickness of the semiconductor raw material layer 12 is, for example, 10 nm to
It is 100 nm. In Example 1, the semiconductor raw material layer 12 had a thickness of 10 nm. The size of the finally formed quantum box is preferably 2 nm to 50 nm.
Further, the semiconductor raw material layer 12 has 10 ¹⁸ / cm ³ to 10 ¹⁹
It is desirable to add a dopant at a concentration of about / cm ³ . As a result, one quantum box contains one electron or hole.

[Step-110] Next, the semiconductor raw material layer 12
Is subjected to heat treatment to form a plurality of semiconductor crystal grains 14.
Specifically, the semiconductor raw material layer 12 is irradiated with pulsed laser light. As the pulsed laser light, for example, one having the following specifications can be used. Laser used: XeCl excimer laser Pulse width: 30 nsec Irradiation energy: 180 mJ / cm ²

The region of the semiconductor raw material layer 12 irradiated with the pulsed laser light is instantaneously melted and cooled from the time when the irradiation of the pulsed laser light is completed, and a uniform fine semiconductor crystal (for example, about 10 nm) made of silicon is formed. Grains 14 are formed (see FIG. 2B). Since the semiconductor crystal grains formed in this way have a sufficiently large electric conductivity, it is considered that there is almost no electron scattering at the semiconductor crystal grain interface.
Therefore, it is considered that there are almost no voids between the semiconductor crystal grains.

[Step-120] Then, semiconductor crystal grains 1
Each surface of 4 is oxidized to form an oxide film, and a quantum box 18 made of semiconductor crystal grains 14 separated from each other by a barrier layer 16 made of an oxide film is formed ((C) in FIG. 2).
reference). The oxide film can be formed, for example, under the following conditions. Oxidizing atmosphere: Oxygen gas atmosphere diluted with nitrogen gas Temperature: 950 ° C Time: 30 minutes

Quantum boxes 18 having a structure in which the respective surfaces of the semiconductor crystal grains 14 are oxidized and the central part made of silicon is surrounded by an oxide film (barrier layer 16) made of silicon dioxide are formed in the regions where channel regions are to be formed. It The reason is that oxygen taken in from the outside is
Semiconductor crystal grains 1 made of silicon diffused on the interface 4
It is because it invades in 4. Thus, the quantum box 18 becomes
They are separated from each other by a barrier layer 16 made of an oxide film.
The controllability of the oxidation treatment on the surface of semiconductor crystal grains made of silicon is very excellent. Therefore, an oxide film having a thickness of several nm can be formed.

In this way, a plurality of quantum boxes 18 composed of semiconductor crystal grains 14 made of silicon of nanometer order can be manufactured. Further, these quantum boxes 18 are separated from each other by a barrier layer 16 (oxide film) made of nanometer-order silicon dioxide. As described above, when forming the quantum box 18, it is not necessary to form a heterojunction with the base body 10 as the base.

The size of such a quantum box can be observed by observing a cross section of the quantum box with a scanning tunneling microscope (STM) or by blue shift in photoluminescence.

[Step-130] Thereafter, if necessary,
An interlayer insulating layer 20 is formed on the entire surface (see FIG. 2D). As a result, the quantum box 18 is covered with the interlayer insulating layer 20. The interlayer insulating layer 20 is made of, for example, silicon dioxide and can be formed by a CVD method or the like. The total thickness of the interlayer insulating layer 20 and the barrier layer 16 formed of an oxide film formed on each surface of the semiconductor crystal grains 14 is set to a thickness at which electrons can tunnel. Specifically, the total thickness is, for example, about several nm to several tens of nm.

[Step-140] Next, the semiconductor raw material layer 22 is formed on the entire surface (see FIG. 3A). As a result, the semiconductor raw material layer 22 is formed on the barrier layer 16 (on the interlayer insulating layer 20 when the interlayer insulating layer 20 is formed). The semiconductor raw material layer 22 can be composed of, for example, polysilicon formed by a CVD method. The thickness of the semiconductor raw material layer 22 may be about 5 to 20 nm. When no dopant is added to the semiconductor raw material layer 12 in [Step-100], in [Step-140],
It is desirable to add a dopant having a concentration of about 10 ¹⁸ / cm ³ to 10 ¹⁹ / cm ³ to the semiconductor raw material layer 22. As a result, one quantum box contains one electron or hole.

[Step-150] After that, the semiconductor raw material layer 2
2 is heat-treated to form a two-dimensional conductive layer 24 made of semiconductor crystal grains (see FIG. 3B). Two-dimensional conductive layer 2
By configuring 4 as a semiconductor crystal grain, the electrical conductivity of the two-dimensional conductive layer 24 can be improved. This heat treatment step can be similar to, for example, [Step-110]. The region of the semiconductor raw material layer 22 irradiated with the pulsed laser light is instantaneously melted, cooled from the time when the irradiation of the pulsed laser light is completed, and is a two-dimensional conductive layer composed of homogeneous fine semiconductor crystal grains made of silicon. 24 is formed. Thus, the channel region of the field effect transistor is formed.

[Step-160] Next, the quantum box 18 and the barrier layer 16 outside the source / drain region formation planned region.
Then, the two-dimensional conductive layer 24, and optionally the interlayer insulating layer 20 are partially removed to separate each element of the field effect transistor (this state is not shown).

[Step-170] Next, the two-dimensional conductive layer 24.
The surface of the gate oxide film 30 is oxidized by an ordinary oxidation method.
To form. Next, a gate electrode 32 made of polysilicon or the like is formed on the gate oxide film 30 by a conventional method (see FIG. 3C).

[Step-180] Next, the source / drain regions 34 are to be formed by the conventional ion implantation method to form the source / drain regions 34. Thereafter, the insulating layer 36 made of, for example, silicon dioxide is CV
After the entire surface is formed by the D method or the like, an opening 38 is formed in the insulating layer 36 on the source / drain region 34 by using a lithography technique and an etching technique such as an RIE method, and the opening 38 is formed by a sputtering method or the like. A metal wiring material such as an aluminum alloy is deposited on the insulating layer 36 including
A drain electrode 40 is provided. Next, the metal wiring material deposited on the insulating layer 36 is subjected to desired patterning to form wiring.

Thus, the field effect transistor shown in FIG. 1A is completed. This field effect transistor includes a plurality of quantum boxes 18 formed on a substrate 10, barrier layers 16 formed between and on the quantum boxes, and a two-dimensional conductive layer 24 formed on the barrier layers. And a channel region consisting of

The outline of the operation of the field effect transistor of the first embodiment will be described below. This field effect transistor applies Mott transition. The quantum boxes are assumed to have a doping concentration capable of confining one electron per one quantum box.

With a proper bias applied between the source / drain electrodes 40, a positive potential of about 0.1 to 1 V is applied to the gate electrode 32. As a result, electrons are attracted to the two-dimensional conductive layer 24, the electric conductivity of the two-dimensional conductive layer 24 increases, and the two-dimensional conductive layer 24 exhibits a metallic behavior.
A current flows between the source / drain electrodes 40. On the other hand, when a negative potential of about −0.1 to −1 V is applied to the gate electrode 32, the electrons are drawn toward the quantum box 18,
Captured within. As a result, the electric conductivity of the two-dimensional conductive layer 24 becomes almost 0, the two-dimensional conductive layer 24 behaves as an insulator, and no current flows between the source / drain electrodes 40. Based on the above operation principle, the conductivity of the channel region of the field effect transistor, that is, the source / drain current can be controlled.

Example 2 Example 2 relates to a field effect transistor according to the second aspect of the present invention and a method for producing a field effect transistor according to the second aspect. The field-effect transistor of Example 2 has a two-dimensional conductive layer and a quantum box layer on it. The semiconductor raw material layer is composed of polysilicon. The substrate is made of glass, which is a material that can withstand heat treatment. Furthermore, the heat treatment is a laser annealing treatment.

FIG. 1B is a schematic partial sectional view of the field effect transistor of the second embodiment. Specifically, this field effect transistor includes (a) a substrate 10 made of glass, (b) a two-dimensional conductive layer 24 made of silicon crystal grains formed on the substrate 10, and a two-dimensional conductive layer 24 on the two-dimensional conductive layer 24. The interlayer insulating layer 50 made of silicon dioxide provided, the quantum boxes 18 made of a plurality of silicon crystal grains provided on the interlayer insulating layer 50, and silicon dioxide formed between these quantum boxes and on the quantum boxes. A channel region composed of a barrier layer 16 composed of (c), (c) a gate electrode 32 provided above the channel region, (d) a source / drain region 34 formed at both ends of the channel region, and a source / drain region. The source / drain electrodes 40 are provided in the drain region 34.

A method of manufacturing the field effect transistor of Example 2 will be described below with reference to FIG.

[Step-200] First, the semiconductor raw material layer 22 is formed on the substrate 10 (see FIG. 4A). The semiconductor raw material layer 22 can be composed of, for example, polysilicon formed by a CVD method. This semiconductor raw material layer 22
May have a thickness of about 5 to 20 nm. If necessary, as described in [Step-140] of Example 1,
A dopant can be added to the semiconductor raw material layer 22.

[Step-210] After that, the semiconductor raw material layer 2
2 is heat-treated to form a two-dimensional conductive layer 24 made of semiconductor crystal grains (see FIG. 4B). This heat treatment step can be performed, for example, in the same manner as in [Step-110] of the first embodiment. The region of the semiconductor raw material layer 22 irradiated with the pulsed laser light is instantaneously melted, cooled from the time when the irradiation of the pulsed laser light is completed, and is a two-dimensional conductive layer composed of homogeneous fine semiconductor crystal grains made of silicon. 24 is formed.

[Step-220] Next, the two-dimensional conductive layer 24.
An interlayer insulating layer 50 is formed thereover (see FIG. 4C).
The interlayer insulating layer 50 is made of, for example, silicon dioxide, and has a C content.
It can be formed by the VD method or the like. The thickness of the interlayer insulating layer 50 is set so that electrons can be tunneled. Specifically, the thickness of the interlayer insulating layer 50 is, for example, several nm to several tens n.
It is about m.

[Step-230] Then, the interlayer insulating layer 50 is formed.
A semiconductor raw material layer 12 is formed thereon (see FIG. 4D),
Next, the semiconductor raw material layer 12 is subjected to heat treatment including laser annealing treatment to form a plurality of semiconductor crystal grains. After that, each surface of the semiconductor crystal grains is oxidized to form an oxide film, and the quantum boxes 18 made of the semiconductor crystal grains are separated from each other by the barrier layer 16 made of the oxide film ((E) in FIG. 4). reference). The above steps can be the same as [Step-100] to [Step-120] of the first embodiment. In this way, when forming the quantum box 18, it is not necessary to form a heterojunction with the underlying interlayer insulating layer 50.

[Step-240] Next, element isolation is performed in the same manner as in [Step-160] of the first embodiment, and then the gate oxide film 30 made of, for example, silicon dioxide is formed above the plurality of quantum boxes 18. .

[Step-250] After that, the gate electrode 32 is formed on the gate oxide film 30 above the channel region.

[Step-260] Next, as in [Step-180] of Example 1, the source / drain regions 34 are formed by the ion implantation method, the insulating layer 36 and the openings 38 are formed, and the source / drain electrodes 40 are formed. Formation.

Thus, the field effect transistor shown in FIG. 1B is completed. This field effect transistor includes a two-dimensional conductive layer 24 formed on a substrate 10, an interlayer insulating layer 50 formed on the two-dimensional conductive layer 24, and a plurality of quantum boxes formed on the interlayer insulating layer 50. 18 and a barrier region 16 formed between the quantum boxes and on the quantum boxes.

The operating principle of the field-effect transistor of the second embodiment is substantially the same as that of the field-effect transistor of the first embodiment except that the sign of the potential applied to the gate electrode 32 is different, and therefore the detailed operation principle will be described. The description is omitted.

Although the field effect transistor and the method for manufacturing the same according to the present invention have been described based on the preferred embodiments, the present invention is not limited to these embodiments. The film forming method and various conditions in the examples are merely examples, and can be appropriately changed. The semiconductor raw material layer can be made of amorphous silicon, other than germanium, or the like, in addition to polysilicon. The interlayer insulating layer and the insulating layer are not limited to silicon dioxide, and can be made of a known insulating material such as SiN that can be deposited on the quantum box layer or the two-dimensional conductive layer by an appropriate method. As the substrate, besides glass, quartz, a silicon substrate, or a substrate that can withstand heat treatment can be used. Alternatively, the substrate may be an insulating layer that covers various elements and wirings. In this case, a multi-layer element structure can be formed.

In the field effect transistor, a quantum box layer or 2
A plurality of dimensional conductive layers may be provided. With such a structure, a large amount of source / drain current can be passed through the field effect transistor, and a large amount of current can be controlled.

The method for forming the two-dimensional conductive layer and the method for heat-treating the semiconductor raw material layer are not limited to the laser annealing process, but may be RTA.
(Rapid Thermal Annealing) processing can be adopted.

In the embodiments, the so-called top gate type field effect transistor has been described as an example, but the field effect transistor of the present invention may be a so-called bottom gate type. When the structure of the field effect transistor described in the first embodiment is applied to the bottom gate type field effect transistor, it has, for example, the following structure. (A) Substrate 10 made of glass (B) Gate electrode 32 formed on the substrate 10 (C) Gate oxide film 30 formed on the gate electrode 32 (D) A plurality of gate electrodes formed on the gate oxide film 30 Quantum boxes 18 made of silicon crystal grains, and a barrier layer 1 made of silicon dioxide formed between and on the quantum boxes 1.
6 and a two-dimensional conductive layer 24 made of silicon crystal grains formed on the barrier layer (E) source / drain regions 34 formed at both ends of the channel region, and source / drain regions Source / drain electrode 40 provided on

Such a bottom gate type field effect transistor can be manufactured by changing the order of the manufacturing steps in the first embodiment as follows. (X) [Step-170] (however, the order of forming the gate electrode and the gate oxide film is reversed) (Y) [Step-100] to [Step-160] (however, the quantum box is formed by the gate oxide film) Performed above) (Z) [Step-180]

When the structure of the field effect transistor described in the second embodiment is applied to the bottom gate type field effect transistor, it has the following specific structure. (A) Substrate 10 made of glass (b) Gate electrode 32 formed on the substrate 10 (c) Gate oxide film 30 formed on the gate electrode 32 (d) Silicon crystal formed on the gate oxide film 30 A two-dimensional conductive layer 24 made of grains, an interlayer insulating layer 50 made of silicon dioxide provided on the two-dimensional conductive layer 24, and a quantum box 18 made of a plurality of silicon crystal grains provided on the interlayer insulating layer 50. A channel region formed between these quantum boxes and a barrier layer 16 made of silicon dioxide formed on the quantum boxes (e) source / drain regions 34 formed at both ends of the channel region, and source / drain Source / drain electrodes 40 provided in the region 34

Such a bottom gate type field effect transistor can be manufactured by changing the order of the manufacturing steps in the second embodiment as follows. (X) [Step-250] (however, the order of forming the gate electrode and the gate oxide film is reversed) (Y) [Step-200] to [Step-240] (however, 2
The three-dimensional conductive layer is formed on the gate oxide film) (Z) [Step-260]

The field effect transistor of the present invention is preferably manufactured by the method of manufacturing a field effect transistor of the present invention, but is not limited to the method of manufacturing a field effect transistor of the present invention. It is also possible to form a quantum box by forming a layer made of semiconductor crystal grains (referred to as a semiconductor crystal grain layer) and then patterning the semiconductor crystal grain layer. During patterning, the resist material is formed on the semiconductor crystal grain layer by, for example, using an electron beam with a spot diameter sufficiently narrowed in a predetermined resist source gas atmosphere in a vacuumed sample chamber of an electron beam irradiation apparatus to form a semiconductor crystal. This can be performed by selectively irradiating the grain layer and depositing a decomposition product of the resist source gas on the portion of the semiconductor crystal grain layer irradiated with the electron beam. Further, the etching of the semiconductor crystal grain layer at the time of patterning can be performed by an anisotropic dry etching method such as the RIE method. The planar shape of the quantum box can be rectangular, for example. For example, CVD is provided between the quantum boxes thus formed and between the quantum boxes.
A barrier layer made of silicon dioxide may be deposited by a method or the like.

[0057]

According to the present invention, it is possible to provide a field effect transistor having a quantum box and applying Mott transition (metal-insulator transition) and having a high degree of integration. In this field effect transistor, the electron density in the channel region is constant, and the electrons and the like only move between the two-dimensional conductive layer and the quantum box by tunneling. Therefore, the field effect transistor can be operated at high speed. In addition, a high-performance field effect transistor can be manufactured with high integration degree over a large area substrate.
The field-effect transistor of the present invention has a quantum box that does not have a heterojunction, and can use a widely used group IV element-based material as a constituent material. According to the method of manufacturing a field effect transistor of the present invention, it is possible to manufacture a field effect transistor composed of a plurality of fine quantum boxes in which quantum boxes are very close to each other through a thin oxide film. The field effect transistor of the present invention can be applied to, for example, a thin film transistor for driving control of an LCD.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a field effect transistor of the present invention.

FIG. 2 is a schematic partial cross-sectional view in each step for explaining the manufacturing method of the field-effect transistor of Example 1.

FIG. 3 is a schematic partial cross-sectional view in each step for explaining the manufacturing method of the field-effect transistor of Example 1, following FIG.

FIG. 4 is a schematic partial cross-sectional view in each step for explaining the manufacturing method of the field-effect transistor of Example 2.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Base | substrate 12,22 Semiconductor raw material layer 14 Semiconductor crystal grain 16 Barrier layer 18 Quantum box 20,50 Interlayer insulating layer 24 Two-dimensional conductive layer 30 Gate oxide film 32 Gate electrode 34 Source / drain region 36 Insulating layer 38 Opening 40 Source Drain electrode

Claims (18)

[Claims] 1. A substrate, (b) a plurality of quantum boxes formed on the substrate, barrier layers formed between the quantum boxes and on the quantum boxes, and on the barrier layer. A channel region composed of the formed two-dimensional conductive layer, (c) a gate electrode provided in the channel region, (d) source / drain regions formed at both ends of the channel region, and the source / drain region A field effect transistor comprising: a source / drain electrode provided on the. 2. Between the barrier layer and the two-dimensional conductive layer, further comprising:
The interlayer insulating layer is formed, The claim 1 characterized by the above-mentioned.
A field effect transistor described in 1. 3. A base, (b) a two-dimensional conductive layer formed on the base, an interlayer insulating layer formed on the two-dimensional conductive layer, and an interlayer insulating layer formed on the interlayer insulating layer. A plurality of quantum boxes, and a channel region composed of a barrier layer formed between the quantum boxes and on the quantum boxes, (c) a gate electrode provided in the channel region, and (d) both ends of the channel region. And a source / drain electrode provided in the source / drain region. 4. The field effect transistor according to claim 1, wherein the quantum box is made of a crystal grain of a group IV element. 5. The field effect transistor according to claim 4, wherein the quantum box is made of silicon crystal grains. 6. The field effect transistor according to claim 1, wherein the barrier layer is made of silicon dioxide. 7. The field effect transistor according to claim 1, wherein the two-dimensional conductive layer is made of silicon crystal grains. 8. A quantum box having a doping concentration capable of confining one electron or hole per one quantum box.
A field effect transistor according to item. 9. The two-dimensional conductive layer has a doping concentration capable of confining one electron or hole in one quantum box, according to any one of claims 1 to 7. Field effect transistor. 10. A semiconductor raw material layer is formed on a substrate,
Next, the semiconductor raw material layer is subjected to heat treatment to form a plurality of semiconductor crystal grains, each surface of the semiconductor crystal grains is oxidized to form an oxide film, which is separated from each other by a barrier layer formed of the oxide film. Forming a quantum box made of semiconductor crystal grains, and (b) forming a semiconductor raw material layer above the quantum box and then heat treating the semiconductor raw material layer to form a two-dimensional conductive layer made of semiconductor crystal grains. A method of manufacturing a field effect transistor, comprising a step of forming a channel region. 11. The method for manufacturing a field effect transistor according to claim 10, wherein an interlayer insulating layer is formed on the barrier layer after the step (a). 12. (a) a step of forming a semiconductor raw material layer on a substrate and then subjecting the semiconductor raw material layer to a heat treatment to form a two-dimensional conductive layer made of semiconductor crystal grains; and (b) a two-dimensional conductive layer. A step of forming an interlayer insulating layer thereon, and (c) forming a semiconductor raw material layer on the interlayer insulating layer, and then subjecting the semiconductor raw material layer to heat treatment to form a plurality of semiconductor crystal grains, and thereafter, the semiconductor A step of forming an oxide film by oxidizing each surface of the crystal grains and forming quantum boxes made of semiconductor crystal grains separated from each other by a barrier layer made of the oxide film; A method for manufacturing a field effect transistor, comprising: 13. The method of manufacturing a field effect transistor according to claim 10, wherein the semiconductor raw material layer is made of a group IV element. 14. The method for manufacturing a field effect transistor according to claim 13, wherein the semiconductor raw material layer is made of polysilicon. 15. The substrate according to claim 10, wherein the substrate comprises a substrate or an insulating layer which can withstand heat treatment.
4. The method for manufacturing the field effect transistor according to any one of 4 above. 16. The method for manufacturing a field effect transistor according to claim 10, wherein the heat treatment is a laser annealing treatment. 17. The semiconductor raw material layer for forming the quantum boxes is doped with a concentration having a concentration capable of confining one electron or hole per one quantum box. Item 17. A method for manufacturing a field effect transistor according to any one of items 16. 18. The semiconductor raw material layer for forming the two-dimensional conductive layer is doped with a concentration enough to confine one electron or hole per one quantum box. 17. A method for manufacturing a field effect transistor according to claim 16.