JPH0799752B2 - Field effect transistor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to field effect transistors, and more particularly to compound semiconductor field effect transistors.

[Background of the Invention]

In GaAs MESFET, semi-insulating G
A type has been proposed in which a layer having p-type conductivity (p-type buried layer 3) is provided between the aAs substrate 1 and the n-type active layer 2 (Open Technical Report Vol. 81-4352).

The main role of the p-type buried layer 3 is to suppress the short channel effect (the short channel effect is a phenomenon in which the threshold voltage largely shifts in the negative direction as the gate length L is shortened). The short channel effect is that electrons injected from the source side n ⁺ layer 5 into the semi-insulating GaAs substrate 1 are drain side n ^+.
This is a phenomenon that appears when it flows into the layer 6, and it can be considered that there is a secondary current path that flows in the semi-insulating GaAs substrate 1 in addition to the current path that flows in the n-type active layer 2. . Therefore, the elevated barrier on the substrate side in the region of the p-type buried layer 3 suppresses the injection of electrons and eliminates the secondary current path.

It is customary to design the p-type buried layer 3 to have a low concentration in order to completely deplete it and not to provide a control voltage for controlling its potential. This is the n-type active layer 1
The parasitic capacitance between the n ⁺ layers 5 and 6 and the p-type buried layer 3 is reduced,
This is to increase the speed of the device.

However, the present inventors have found that the element thus designed is weak against α rays. That, SRAM which is constructed by using such a device (S tatic R andom A ccess M emor
In y), the stored information is destroyed every time an α-ray is incident (soft error). Such soft errors are caused by TC May and M.H.
It was first discovered by MH Woods in 1979 in Si devices. (TC May and MHC Woods, IEE
Transactions, Electron Devices, ED-26 Volume 2 1979 [TC May and MH Woods, IEEE Trans, Ele
ctron Device, ED-26, p2, 1979]) The mechanism of soft error in Si devices is usually considered as follows. The memory information is DRAM ( D yuamic
For R andom A ccess M emory), held in the form of the presence or absence of electric charge accumulated in the capacitor arranged in the memory cell, also in the case of SRAM, in the form of high and low potential of the node in the memory cell (node) To be done. When α rays enter there, 10 ⁶ electron-hole pairs are generated along the tracks in the Si substrate, and these carriers diffuse or drift in the substrate and flow into capacitors and nodes. Therefore, the amount of charge accumulated in the capacitor and the potential of the node largely change, and the stored information held is destroyed. GaAs M with the above-mentioned p-type buried layer
It is considered that a soft error will occur due to the same mechanism even in SRAM configured using ESFET.

It should be noted here that in Si devices, if the total amount of carriers generated along the α-ray track is 10 ⁶ pieces, the total amount of charges flowing into the capacitor or node is 160 fC (at most This is equivalent to the case where all carriers flow in.), Which means that it will not exceed 160 fC.

However, the present inventors have found that GaAs MES having a p-type buried layer
The following facts were found as a result of repeated measurement of the FET transistor operating state. In other words, the situation is different from that of Si devices, and it seems that a charge amount several times higher than 160 fC is generated by α-rays and flows to the electrodes. This indicates that the GaAs MESFET provided with the p-type buried layer has a smaller α-ray resistance than the Si device, and suggests that some carrier multiplication mechanism exists.

[Object of the Invention]

An object of the present invention is to provide a field effect transistor having high α-ray resistance.

[Outline of Invention]

In order to achieve the above object, the present invention provides a semiconductor layer forming a source / drain region and an active layer with a conductivity type opposite to that of the semiconductor layer and having conductivity (not completely depleted). A semiconductor layer is provided in contact with the semiconductor layer, and an electrode is provided on the conductive semiconductor layer.

That is, the present inventors have found the following mechanism as one of the above-mentioned carrier multiplication mechanisms. α
The total amount of positive charges (due to holes) and negative charges (due to electrons) generated in the substrate due to the incidence of rays is 160f.
Equivalent in C. Further, since the p-type buried layer is completely depleted, electric lines of force that start at the drain and end at the source run when voltage is applied to the drain.
This happened. Promotes carrier drift. further,
The mobility that determines the drift velocity in GaAs is more than 10 times greater for electrons than for holes. Therefore, a state in which holes remain in the substrate even after the electrons are completely absorbed on the drain side is realized. Therefore, the potential barrier on the substrate side is lowered, and the injection of electrons from the source side is promoted,
A mechanism similar to the mechanism found in the short channel effect, in which a new current flows into the drain side by forming a secondary current path, works. The charge flowing in this way is 160 fC
It is observed as a multiplication of the carrier.

In the device structure according to the present invention, in order to suppress the multiplication of carriers, for example, as shown in FIG. 2, a p-type buried layer which is not completely depleted below the n-type active layer 12 or the n ⁺ layers 15 and 16 is formed. A layer 13 is arranged, and a control electrode 17 for controlling the potential of the layer is provided.

According to such an element structure, it is possible to avoid the phenomenon that only the holes remain in the substrate and the potential barrier on the substrate side is lowered as described above. Because the holes are p
This is because it flows out to the control electrode 17 through the neutral region (region not depleted) of the mold burying layer 13.

Therefore, the injection of electrons from the source side into the substrate is suppressed, and the multiplication of carriers is suppressed.

There are only a limited number of elements in the integrated circuit that cause the problem of the carrier multiplication effect when α-rays are incident, and there is a problem in maintaining the high speed of the circuit without causing unnecessary parasitic capacitance in the circuit. It is preferable to adopt the element structure as shown in FIG. 2 only for the element. From this point of view, the element structure in which the p-type buried layer 13 is selectively formed as shown in FIG. 2 is more preferable than the element structure formed over the entire surface.

Further, in FIG. 1, since 2, 5, 6 are n-type and 3 is p-type, holes remain in the substrate and carrier multiplication occurs.
On the contrary, in Fig. 1, 2, 5, 6 are p-type and 3
When is an n-type, the carrier multiplication effect does not occur. This is because the holes remain in the substrate and thus suppress the injection of holes from the source side. However, the total amount of electric charge flowing into the electrode is about 140 fC at the maximum (almost equal to the total amount of electric charge generated by α rays), which is still large to avoid the soft error.

However, according to the device structure of the present invention shown in FIG.
When 5 and 16 are p-type, 13 is n-type and the control electrode 17 is provided, it is possible to reduce the total charge flowing into the electrodes. Because electrons flow out to the control electrode through the n-layer 13, and holes are p due to the electrostatic potential of the n-layer 13.
This is because it is prevented from flowing into the layers 12, 15 and 16.

In summary, according to the device structure of the present invention, when the active layer is the n-type and the buried layer is the p-type, the multiplication of the carrier is suppressed, and further, the total inflowing charge amount is α It can be suppressed more than the amount of charges generated by the line.
On the contrary, even when the active layer is p-type and the buried layer is n-type, the total amount of charges flowing in can be suppressed more than the amount of charges generated by α rays. That is, according to the element structure of the present invention, the α-ray resistance can be increased.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 3 shows a field effect transistor similar to that shown in FIG.
A p-type buried layer 33, an n-type active layer 32, and an n ⁺ layer 3 are formed on the semi-insulating GaAs substrate 31 by ion implantation and subsequent high temperature heat treatment.
Form 5,36. Ion implantation of the p-type buried layer 33 is B
Any of e, Mg, C, and Zn may be used, and the implantation energy depends on the formation conditions of the n-type active layer 32 and the n ⁺ layers 35 and 36, but is usually selected in the range of 70 KeV to 300 KeV. , The dose amount depends on the implantation energy in order to satisfy the condition of not being completely depleted, but is usually selected within the range of 10 ¹¹ cm ^-2 or more. The high temperature heat treatment is usually performed at a temperature of 700 ° C to 850 ° C. Source electrode 39, drain electrode 40, gate electrode 38
Is formed by a normal lift-off method. The control electrode 37 of the p-type buried layer 33 may be any metal that makes an ohmic contact with the p-type GaAs layer, and any one of Cr, AuZn and the like may be used.

According to this embodiment, it is possible to suppress the multiplication of carriers caused by α rays as described above.

A second embodiment is shown in FIG. This embodiment is an improvement of the embodiment shown in FIG. A p ⁺ layer 41 having a higher concentration than the p-type buried layer 33 is provided below the control electrode 37. The p ⁺ layer 41 is formed by high-dose ion implantation of any one of Mg, Be, C, and Zn and a high-temperature heat treatment step, or a selective diffusion step using a Zn insulating film as a mask. In the case of ion implantation, the implantation energy is
Normally select between 10 KeV and 300 KeV, and the dose amount is usually 10
Select from ¹³ cm ^-2 or more. Further, in the case of selective diffusion of Zn, it diffuses at a high temperature of 800 ° C. or higher so that the surface concentration becomes 10 ¹⁸ cm ⁻³ .

According to the present embodiment, the contact resistance between the control electrode 37 and the p-type buried layer 33 can be lowered to the utmost, and the multiplication effect of the carrier can be further reduced as compared with FIG. Further, in FIG. 3, the control electrode 37 has a metal used for the source electrode 39 and the drain electrode 40 (for example, a metal having an ohmic contact with the n-type layer such as AuGe) in order to make an ohmic contact with the p-type layer 33. It is necessary to use another kind of metal (for example, Cr or AuZn), but according to the present embodiment, since the p ⁺ layer 41 has a high concentration, it is the same kind of metal as the source electrode 39 or the drain electrode 40,
Ohmic contact can be realized even if the same metal as the metal of the gate electrode 38 is used, the process for forming the control electrode 37 can be omitted, and the process can be simplified.

FIG. 5 shows a third embodiment. This embodiment is an improvement of the embodiment shown in FIG. Adjacent to the source side n ⁺ layer 35
A p ⁺ layer 41 is provided, and the source electrode 39 is arranged on the n ⁺ layer 35 and the p ⁺ layer 41 at the same time.

According to the present embodiment, the multiplication of carriers can be suppressed as in the embodiments of FIGS. 3 and 4, and the element area can be further reduced as compared with those, and high integration can be achieved.

As described above, there are only a limited number of elements in the integrated circuit that cause the problem of the carrier multiplication effect when α rays are incident, and in order to maintain the high speed of the circuit without causing unnecessary parasitic capacitance in the circuit. It is preferable to adopt the element structure as shown in FIGS. 3 to 5 only for the element in question. From that point of view, FIGS.
An element structure in which the p-type buried layer 33 is selectively formed as in the illustrated embodiment is desirable.

FIG. 6 shows a fourth embodiment. This embodiment is an improvement of the embodiment shown in FIG. As described above, in order to maintain the high speed of the integrated circuit, it is desirable to eliminate the parasitic capacitance as much as possible. FIG. 6 shows the n ⁺ layer 36 on the drain side and the p-type buried layer 33.
In order to reduce the parasitic capacitance between and, the structure in which the p-type buried layer is not provided below the n ⁺ layer is shown. In order to suppress the carrier multiplication effect at the time of incidence of α rays, a p-type buried layer 33 is provided on the whole or part of the lower part of any one of the n ⁺ layer 35, the n ⁺ layer 36 and the n-type active layer 32. Is the minimum condition, and how the p-type buried layer 33 is arranged depends on how the speed of the integrated circuit is designed.

FIG. 7 shows a fifth embodiment. An n-type active layer 52, n ^{+ is formed} on the p-type GaAs substrate 53 by ion implantation and subsequent heat treatment.
Form layers 55, 56. The concentration of the p-type substrate 53 is selected from the range of 10 ¹³ cm ^-3 or more so that the substrate is not completely depleted. The source electrode 59, the drain electrode 60, and the gate electrode 58 are formed by a normal lift-off method. Control electrode 57 of p-type substrate 53
Is a metal that makes ohmic contact with p-type GaAs, and any of Cr, AuZn, etc. may be used.

According to the present embodiment, it is possible to suppress the multiplication of carriers caused by α rays similarly to FIG. Further, the step of forming the p-type buried layer 33 of FIG. 3 can be omitted, and the step can be simplified.

3 to 7, the buried layer and the substrate are described as p-type, and the active layer is described as n-type. However, when each has the opposite conductivity, when the α-ray is incident, The inflow of carriers can be suppressed more than the generated charge amount.

Also, although the explanation was limited to GaAs, InP, GaAlAs, In
It is needless to say that the compound structure of the present invention can suppress the multiplication effect of carriers even with other compound semiconductors such as GaAs and InGaAsP. This is because the electron mobility of a compound semiconductor is generally about one digit higher than the hole mobility, so that holes always remain in the substrate.

For Si and Ge substrates, the carrier multiplication effect itself is small, but it goes without saying that it can be suppressed similarly.

〔The invention's effect〕

As described above, according to the present invention, it is possible to suppress the multiplication effect of the carrier at the time of incidence of α-rays, and it is possible to increase the α-ray resistance as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a sectional structure view of a conventional field effect transistor, FIG. 2 is a sectional structure view of a field effect transistor according to the present invention, and FIGS. 3 to 7 are sectional structure views of an embodiment of the present invention. 11 ... Semi-insulating GaAs substrate, 12 ... n-type active layer, 13 ... p
Mold buried layer, 15,16 …… n ⁺ layer, 17 …… Control electrode, 18 ……
Gate electrode, 19 ... Source electrode, 20 ... Drain electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuichi Hashimoto 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-50-41477 (JP, A) JP-A-SHO 58-148449 (JP, A) JP-A-59-165466 (JP, A) JP-A-59-191385 (JP, A)

Claims (12)

[Claims] 1. A first conductivity type first having a compound semiconductor substrate, a source region, a drain region, and an active region formed between the compound semiconductor substrate and the two regions.
A semiconductor layer, a gate electrode formed on the active region, a source electrode formed on the source region, and a drain electrode formed on the drain region, the compound semiconductor substrate A second conductivity type having a conductivity type opposite to the first conductivity type and formed between the first semiconductor layer and the first semiconductor layer in contact with at least one of the source region, the drain region and the active region. Second semiconductor layer, the second semiconductor layer is not completely depleted, and has a control electrode electrically connected to the second semiconductor layer, and the second semiconductor layer and the second semiconductor layer. A third semiconductor layer having a second conductivity type and a lower resistance than the second semiconductor layer is provided between the source electrode, the drain electrode and the control electrode, and the source electrode, the drain electrode and the control electrode are made of the same metal. Or drain Field effect transistors one emission electrode, characterized in that electrically connected is formed continuously with the control electrode. 2. A first conductivity type first having a compound semiconductor substrate and a source region, a drain region, and an active region formed between the two regions and formed on the compound semiconductor substrate.
A semiconductor layer, a gate electrode formed on the active region, a source electrode formed on the source region, and a drain electrode formed on the drain region, the compound semiconductor substrate Formed between the first semiconductor layer and the first semiconductor layer continuously in contact with the source region, the drain region, and the active region, and in contact with a portion of the drain region, the conductivity being opposite to the first conductivity type. A second semiconductor layer having a second conductivity type of the second conductivity type, the second semiconductor layer not being fully depleted,
A field-effect transistor having a control electrode electrically connected to the second semiconductor layer. 3. A third semiconductor layer having a second conductivity type and a resistance lower than that of the second semiconductor layer between the second semiconductor layer and the control electrode. The field effect transistor described. 4. The field effect transistor according to claim 3, wherein the source electrode, the drain electrode and the control electrode are made of the same metal. 5. The field effect transistor according to claim 4, wherein the control electrode and one of the source electrode and the drain electrode are continuously formed. 6. The field effect transistor according to claim 1, wherein the field effect transistor is one of a plurality of field effect transistors integrated in an integrated circuit. 7. The second semiconductor layer of the field effect transistor is not connected to any of the second semiconductor layers of other field effect transistors of the plurality of field effect transistors. Field effect transistor. 8. A first conductivity type first having a compound semiconductor substrate and a source region, a drain region, and an active region formed between the compound semiconductor substrate and the two regions.
A semiconductor layer, a gate electrode formed on the active region, a source electrode formed on the source region, and a drain electrode formed on the drain region, the compound semiconductor substrate A second conductivity type having a conductivity type opposite to the first conductivity type and continuously formed between the first semiconductor layer and the first semiconductor layer in contact with the source region, the drain region, and the active region. The semiconductor layer is not completely depleted, and the field effect transistor has a control electrode electrically connected only to the second semiconductor layer, A third semiconductor layer having a second conductivity type and a resistance lower than that of the second semiconductor layer between the second semiconductor layer and the control electrode, and the field effect transistor is integrated in an integrated circuit. Multiple electric fields The second semiconductor layer of the field effect transistor is not connected to any of the second semiconductor layers of the other field effect transistors of the plurality of field effect transistors. Field effect transistor. 9. The field effect transistor according to claim 8, wherein the source electrode, the drain electrode and the control electrode are made of the same metal. 10. The field effect transistor according to claim 1, wherein the gate electrode and the control electrode are made of the same metal. 11. The second semiconductor layer comprises Be, Mg, C and Z.
The field effect transistor according to claim 1, wherein at least one selected from the group consisting of n is doped. 12. The field effect transistor according to claim 1, wherein the compound semiconductor substrate is made of semi-insulating GaAs.