JPH08106787A - Memory cell stabilizing circuit - Google Patents

Abstract

PURPOSE: To stabilize a memory by arranging a conductor to be capacitively coupled to a memory cell node and a level control means to change the conductor from the 'L' level to the 'H' level in the write operation. CONSTITUTION: A first bit wire BL1 and a second bit wire BL2 are arranged crossing word wires WL1 and WL2. A memory cell is of an HR type or of a TFT type and constituted of transistors Q1-Q4 and resistors R1 and R2. With such an arrangement, the stability of the operation of the memory cell can be improved by raising the 'H' level of a memory cell node immediately after the end of writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static RAM.
In particular, it relates to a memory cell stabilizing circuit for stabilizing the operation of an HR type (high resistance load type) or a TFT type (thin film transistor type) memory cell.

[0002]

2. Description of the Related Art Conventionally, in an HR type or TFT type static RAM, as a write operation to a memory cell, the potential from the "L" level write side of a bit line pair to one side of a memory cell node is "L". After the voltage is lowered to the level, the potential of the memory cell node on the other side is set to the “H” level by the source follower operation of the transfer gate to write the data.

However, the "H" level of the HR or TFT type memory cell node does not rise to the power supply voltage.
The level becomes lower by the threshold voltage of the transistor.
Therefore, the memory cell is in an unstable state immediately after writing (CMOS VLSI design, Takuo Sugano, Baifukan, P1
64-165).

On the other hand, as disclosed in Japanese Patent Application No. 2-3171, it is general to apply a high voltage to a word line at the time of writing. Although this document shows a method of applying the voltage before the internal voltage reduction to the word line, there is also a method of using a bootstrap word line for applying the boosted voltage to the word line. There is also a method of using a transistor with a small threshold voltage substrate bias effect for the transfer gate of the memory cell.

Further, the power supply voltage rises at the end of data retention (data holding operation), but since the "H" level of the memory cell node is connected to the power supply with a high resistance, the power supply voltage at the time of data retention is high. The memory cell is still in an unstable state.

However, if a high voltage is constantly applied to the word line or a transistor having a small substrate bias effect is used as described above, the memory cell current flowing from the bit line to the selected memory cell increases, resulting in power consumption. There was a problem of getting bigger.

Further, the above method has a problem that the stability of the memory cell immediately after writing is improved, but the stability of the memory cell at the end of data retention is not improved.

As a document showing the prior art, the invention of "word line potential stabilizing circuit" is disclosed in Japanese Patent Application No. 59-104787, and "Semiconductor Memory Device" in Japanese Patent Application No. 63-239862. Of the invention of Japanese Patent Application No. 4-
Although the invention of a "static type memory cell" is disclosed in Japanese Patent No. 82085, the configuration and the effect of the invention are different from those of the invention, and therefore the description thereof is omitted here.

[0009]

As described above, in the conventional static RAM memory cell stabilization method of the HR type or the TFT type, the increase in power consumption is small,
Furthermore, it has no effect on the stability at the end of data retention.

The present invention has been made to solve the above problems, and in a static RAM of HR type or TFT type, the power consumption is small and the operation of the memory cell is stable immediately after writing or at the end of data retention. It is an object of the present invention to provide a memory cell stabilizing circuit that can be realized and a method thereof.

[0011]

In order to achieve the above object, a memory cell stabilizing circuit according to the present invention sets a potential on one side of a memory cell node from an "L" level write side of a bit line pair to an "L" level. Then, the potential of the memory cell node on the other side is set to "H" level by the source follower operation of the transfer gate connected to the first word line to write static data RA.
A conductor used for M, formed on the formation layer of the memory cell node, and capacitively coupled to the memory cell node;
This conductor is provided with a level control means for changing the level from the "L" level to the "H" level during the write operation or after the end of the data retention.

Alternatively, a second word line used in the static RAM and formed in a conductor layer on the formation layer of the memory cell node and capacitively coupled to the first word line, and the second word line. The line control circuit is provided with level control means for changing the line from the "L" level to the "H" level in the write operation.

[0013]

In the memory cell stabilizing circuit having the above structure, the potential of the conductor capacitively coupled to the memory cell node is changed from the "L" level to the "H" level in the write operation or after the data retention is completed. so,
The "H" level of the memory cell node is raised to stabilize the operation of the memory cell.

In the memory cell stabilizing circuit having the later configuration, the potential of the second word line capacitively coupled to the first word line in the write operation is changed from the "L" level to the "H" level. By raising the "H" level of the first word line, that is, raising the gate voltage of the transfer gate, the write voltage of the "H" level of the memory cell node rises, thereby stabilizing the operation of the memory cell.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of a first embodiment of a memory cell stabilizing circuit according to the present invention. In FIG. 1, WL1 is a first word line and WL2 is a second word line, and a first bit line BL1 and a second bit line BL2 are wired so as to intersect these word lines WL1 and WL2.

The memory cell is of HR type or TFT type, and is composed of transistors Q1 to Q4 and resistors R1 and R2. Q1 and Q2 are driver gate transistors,
Q3 and Q4 are transfer gate transistors.

The transistors Q1 and Q2 have their gates and drains connected to each other. This connection portion serves as a memory cell driver gate = memory cell node. Also, each source is grounded.

The transistor Q3 has a gate connected to the first word line WL1, a drain connected to the first bit line BL1, a source connected to the drain of the transistor Q1, and a resistor R1 connected to the VCC power source. It
Similarly, the gate of the transistor Q4 is the first word line WL1.
, The drain is connected to the second bit line BL2, the source is connected to the drain of the transistor Q2, and is also connected to the Vcc power supply via the resistor R2.

The memory cell driver gate (memory cell node) is formed of 1Poly (first polysilicon layer), and the second word line WL2 is 2Poly above 1Poly.
(Second polysilicon layer). 1 Poly and 2
Capacitors C1 and C1 'are formed between the Poly and are respectively connected between the second word line WL2 and the memory cell driver gate.

Here, the physical hierarchical relationship between 1Poly and 2Poly and the layer names do not matter. Also, 1Poly, 2P
Oly may be replaced with a diffusion layer, a metal, or the like.

The 1-poly first word line WL1 is driven by a signal obtained by inverting the rising signal X- (-represents inversion) by the inverter I1. Also, 2 Pol
The second word line WL2 of y is the word line WL of 1Poly
It is driven by the logical OR inversion output of the NOR gate G1 to which the rising signal of 1 (row decoder output) X−, the write control signal WE, and the negative phase delay signal WE− of the WE by the inverter I2 are input.

FIG. 2 shows operation waveforms of the first embodiment. First, when the write control signal WE changes from the L level (GND level) to the H level (VCC level) and the writing is started,
The "H" side of the memory cell node has a power supply voltage level Vcc corresponding to the threshold voltage VT of the memory cell transfer gate.
It will be a lower level.

Next, when the write control signal WE changes from the H level to the L level to end the writing, the inverter I2
The second word line WL2 is rapidly changed from the L level (GND level) to the H level (VCC level) by the NOR gate G1.

At this time, the "H" side of the memory cell node is close to the floating state at a voltage higher than the level dropped from V CC by V T, so that the C with the second word line WL2 is
The node potential on the "H" side rises due to capacitive coupling of 1, C1 '. On the other hand, on the “L” side of the memory cell node, the potential does not change due to capacitive coupling because the memory cell driver gate is on.

After that, the potential of the second word line WL2 is slowly lowered. Therefore, the potential is not lowered due to capacitive coupling, and the potential remains high on the “H” side of the memory cell node.

FIG. 3 shows the configuration of the second embodiment of the present invention. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals, and different parts will be mainly described here.

In FIG. 3, the memory cell structure is exactly the same as that of the first embodiment. In this embodiment, 2Poly is formed on the memory cell driver gate (memory cell node) formed of 1Poly, and 1Poly and 2Poly are formed.
Capacitors C2 and C2 'are formed between y and are respectively connected between the second word line WL2 and the memory cell driver gate. 2Poly is not arranged separately for each first word line as shown in FIG. 1, but is arranged for all memory cells.

This 2Poly is the power supply voltage Vcc
Is detected and the end of data retention is detected, and for example, a logical product of a Vcc potential detection circuit D1 that changes the output φv from L to H and φd and the AND gate G2 that inputs the negative phase delay signal φv − by the inverter I3. Driven by output.

Also in this embodiment, the memory cell is of the HR type or the TFT type, and the physical vertical relationship between 1Poly and 2Poly and the layer name are not limited. Also, 1Poly, 2Po
ly may be replaced with a diffusion layer, a metal, or the like.

FIG. 4 shows operation waveforms of the second embodiment. First, during data retention, the power supply voltage drops from the VCC level to the VCCH level. Further, the potential on the "H" side of the memory cell node becomes the same as the power supply voltage by the HR or the TFT and holds data.

Next, even if the power supply voltage rises to Vcc and becomes the operating state, the potential on the "H" side of the memory cell node is H.
Since it is connected to the power source with high resistance by R or TFT, it takes time to rise to the VCC level. Therefore, it remains at the VCCH level for a while.

When the power supply voltage rises from VCCH to VCC,
The Vcc potential detection circuit (here, the circuit in which the output φv changes from L to H when the power supply voltage rises to the VCC level and the data retention ends) is detected and the output φv is detected.
Is changed from L level (GND level) to H level (VCC level).

Therefore, the inverter I3 and the AND gate G2 cause 2Poly of the memory cell array to suddenly change to L level.
From H to H, and the potential on the "H" side of the memory cell node remains high, as in the case of the first embodiment.

FIG. 5 shows the configuration of the third embodiment of the present invention. In FIG. 5, the same parts as those in FIG. 1 are designated by the same reference numerals, and different parts will be mainly described here.

In FIG. 5, the memory cell structure is exactly the same as that of the first embodiment. In this embodiment, the second word line WL2 of 2Poly is formed on the memory cell transfer gate (first word line WL1) formed of 1Poly, and the capacitor C3 is formed between 1Poly and 2Poly, and the first And the second word lines WL1 and WL2.

The 2 Poly second word line WL2 is driven by the logical OR inversion output of the NOR gate G3 which receives the write control signal WE and its anti-phase delay signal WE- by the inverter I4. In addition, between the source of the PMOS of the word driver WD1 which drives the 1-poly first word line WL1 by the rising signal X- and VCC, the second
A PMOS1 for inputting the potential of the word line WL2 into the gate is inserted.

Also in this embodiment, the memory cell is of the HR type or the TFT type, and the physical hierarchical relationship between 1Poly and 2Poly and the layer name are not limited. Also, 1Poly, 2Po
ly may be replaced with a diffusion layer, a metal, or the like. The bit lines BL1 and BL2 are PMOS2 and PMOS, respectively.
3 is pulled up and driven by the CMOS column switches SW1 and SW2 and the write circuits W1 and W2.

FIG. 6 shows operation waveforms of the third embodiment. First, when the write control signal WE changes from the L level (GND level) to the H level (VCC level) and the writing is started,
The "H" side of the memory cell node is at a level lower than VCC by the threshold voltage VT of the memory cell transfer gate.

Next, when the write control signal WE changes from H level to L level and the write is completed, the second word line WL2 is set to L by the inverter I4 and the NOR gate G3.
The level (GND level) suddenly changes to the H level (VCC level).

When the second word line WL2 becomes H level,
PMOS1 is off, first word line (1Poly) WL1
Becomes a floating state, and the second word line (2Po
ly) Due to capacitive coupling with WL2, the potential is momentarily raised to a potential higher than the Vcc potential. The memory cell transfer gate raises the level of the bit lines BL1 and BL2 into the memory cell as much as the gate potential rises. Therefore, the "H" potential of the memory cell node is written high.

FIG. 7 shows the configuration of the fourth embodiment of the present invention. 7, the same parts as those of FIG. 5 are designated by the same reference numerals, and different parts will be mainly described here.

In FIG. 7, the memory cell structure is exactly the same as that of the first embodiment. Also in this embodiment, the second word line WL2 of 2Poly is formed on the memory cell transfer gate (first word line WL1) formed of 1Poly, and the capacitor C4 is formed between 1Poly and 2Poly, and the first And the second word lines WL1 and WL2.

The second word line WL2 of 2Poly has a logical sum inverted output of the NAND gate G4 to which the write control signal WE- and its anti-phase delay signal WE by the inverter I5 are inputted, and a rising edge for selecting the first word line WL1. Signal X-
And a logical OR output of an OR gate G5 to which the inverted phase delay signal X is input by the inverter I6, and an inverted logical OR output of a NAND gate G6.

A signal obtained by inverting the output of the NAND gate G4 by the inverter I7 is gated to the PMOS1 inserted between the source of the PMOS of the word driver WD1 for driving the first word line WL1 of 1Poly and VCC. Is entered.

Also in this embodiment, the memory cell is of the HR type or the TFT type, and the physical hierarchical relationship between 1Poly and 2Poly and the layer name are not limited. Also, 1Poly, 2Po
ly may be replaced with a diffusion layer, a metal, or the like. The bit lines BL1 and BL2 are PMOS2 and PMOS, respectively.
3 is pulled up and driven by the CMOS column switches SW1 and SW2 and the write circuits W1 and W2.

FIG. 8 shows operation waveforms of the fourth embodiment. The operation is almost the same as that of the third embodiment, except that when the first word line WL1 rises, the second word line WL2 also rises at the same time.

That is, in this embodiment, the capacitance C4 is virtually invisible by moving the first word line WL1 at the same potential as the second word line WL2, and the rising speed of the first word line WL1 is accelerated. The second word line WL2 rises together with the first word line WL1 and then slowly falls, after which the same operation as in the third embodiment is performed.

From the above, according to the configuration of the first embodiment, the operation stability of the memory cell can be improved by raising the "H" level of the memory cell node immediately after the end of the write. Further, according to the second embodiment, the "H" level of the memory cell node at the end of data retention can be raised, and the operation stability of the memory cell can be further improved.

Further, according to the structure of the third embodiment, the operation stability of the memory cell can be improved by raising the "H" level of the memory cell node immediately before the end of writing.

Further, according to the configuration of the fourth embodiment, the effect that the operation speed during normal read is not delayed is obtained in addition to the effect of the third embodiment.

According to the configurations of the first and second embodiments, the memory cell current flowing into the memory cell from the bit line does not increase. Further, in the configurations of the third and fourth embodiments, the memory cell current instantaneously increases immediately before the end of writing, but does not increase in other cases. Therefore, the increase in power consumption can be minimized.

Further, according to the structures of the first and second embodiments, in addition to the above effects, the capacity of the memory cell node can be increased, and the operational stability of the memory cell can be further improved. it can.

Furthermore, in the first to fourth embodiments,
Improving the stability of the operation of the memory cell also makes it more resistant to soft errors and the like, and also makes it possible to expand the operating power supply voltage. In the second embodiment, the data holding power supply voltage can be expanded.

In addition, in the first to fourth embodiments, the voltage is increased only once by capacitive coupling, but the effect is further increased by performing the increase a plurality of times by the ring oscillator or the like. Further, in the first, third and fourth embodiments, the voltage is raised by capacitive coupling at the end of the write operation, but it may be performed during the write operation. In addition, the present invention is not limited to the above-described embodiments, and it goes without saying that the present invention can be similarly implemented even if various modifications are made without departing from the gist of the present invention.

[0056]

As described above, according to the present invention, H
(EN) Provided are a memory cell stabilizing circuit and method capable of stabilizing the operation of a memory cell immediately after writing or at the end of data retention without increasing power consumption in an R type or TFT type static RAM. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a memory cell stabilizing circuit according to the present invention.

FIG. 2 is a waveform diagram showing operation waveforms of the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of a memory cell stabilizing circuit according to the present invention.

FIG. 4 is a waveform diagram showing operation waveforms of the second embodiment.

FIG. 5 is a circuit diagram showing a configuration of a third embodiment of a memory cell stabilizing circuit according to the present invention.

FIG. 6 is a waveform diagram showing operation waveforms of the third embodiment.

FIG. 7 is a circuit diagram showing a configuration of a fourth embodiment of a memory cell stabilizing circuit according to the present invention.

FIG. 8 is a waveform diagram showing operation waveforms of the fourth embodiment.

[Explanation of symbols]

 WL1 first word line WL2 second word line BL1 first bit line BL2 second bit line Q1, Q2 driver gate transistor Q3, Q4 transfer gate transistor C1, C1 ', C2, C2', C3, C4 capacitance I1 to I7 inverter G1 NOR gate G2 AND gate G3 NOR gate G4 NAND gate G5 OR gate G6 NAND gate D1 VCC potential detection circuit WD1 word driver

Claims (8)

[Claims] 1. The potential of a memory cell node on the other side is first dropped after the potential on one side of the memory cell node is dropped to the "L" level from the "L" level write side of the bit line pair.
It is used in a static RAM for writing data by setting it to "H" level by a source follower operation of a transfer gate connected to a word line, is formed on a formation layer of the memory cell node, and is capacitively coupled with the memory cell node. And a level control means for changing this conductor from an "L" level to an "H" level in a write operation. 2. The memory cell stabilizing circuit according to claim 1, wherein the level control means changes the level of the conductor from “L” level to “H” even at the end of data retention. 3. The potential of the memory cell node on the other side is set to the first level after the potential on one side of the memory cell node is dropped to the "L" level from the "L" level write side of the bit line pair.
It is used in a static RAM for writing data by setting it to "H" level by the source follower operation of a transfer gate connected to a word line, and is formed in a conductor layer on the formation layer of the memory cell node,
A second word line capacitively coupled to the first word line; and a level control means for changing the second word line from an "L" level to an "H" level in a write operation. And a memory cell stabilization circuit. 4. The memory cell stability according to claim 3, wherein the level control means changes the second word line from “L” level to “H” even at the end of data retention. Circuit. 5. The potential of the memory cell node on the other side is first reduced after the potential on one side of the memory cell node is reduced to the “L” level from the “L” level write side of the bit line pair.
It is used in a static RAM for writing data by setting it to "H" level by a source follower operation of a transfer gate connected to a word line, is formed on a formation layer of the memory cell node, and is capacitively coupled with the memory cell node. A method for stabilizing a memory cell, characterized in that the conductor to be changed is changed from "L" level to "H" level in a write operation. 6. The method for stabilizing a memory cell according to claim 5, wherein the conductor is changed from the “L” level to the “H” level even after the data retention is completed. 7. The potential of one side of the memory cell node is first reduced to the “L” level from the “L” level write side of the bit line pair, and then the potential of the memory cell node on the other side is first changed.
It is used in a static RAM for writing data by setting it to "H" level by the source follower operation of a transfer gate connected to a word line, and is formed in a conductor layer on the formation layer of the memory cell node,
A method of stabilizing a memory cell, wherein a second word line capacitively coupled to the first word line is changed from an "L" level to an "H" level in a write operation. 8. The method of stabilizing a memory cell according to claim 7, wherein the second word line is changed from “L” level to “H” even at the end of data retention.