JPH08124376A - FIFO memory - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a FIFO memory, and an object of the present invention is to provide a FIFO memory capable of always performing highly reliable capacity monitoring. In a FIFO memory having a memory for storing data, a write counter for generating a write address of the memory, and a read counter for generating a read address of the memory, they are different from each other based on the write address of the write counter. A memory by generating the first and second windows and detecting at least a partial overlap between the first and second windows and the third window generated based on a predetermined read address of the read counter. Capacity monitoring. Preferably, the empty flag is set by the overlap of the first window corresponding to the smaller value of the write address and the third window of the read address, and the subsequent data read control is temporarily suspended. Further, the full flag is set by the overlap of the second window corresponding to the large value of the write address and the third window of the read address, and the subsequent data write control is temporarily suspended.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a FIFO memory,
More specifically, the present invention relates to a FIFO memory including a memory that stores data, a write counter that generates a write address of the memory, and a read counter that generates a read address of the memory. This kind of FIFO memory is used for the purpose of writing data by the first clock signal on the data writing side and reading it at an arbitrary phase by the second clock signal on the data reading side (for example, a data transmission device). Widely used.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional FIFO memory, in which 1 is a dual port RAM (DP-R).
AM), 2 is a write counter (CTR), 3 is a read counter (CTR), 11 and 12 are AND gate circuits (A),
30 is a capacity monitoring unit, 31 is an up / down counter (U /
DCTR), 32 and 33 are decoders (DEC), 41 is a serial / parallel converter (S / P), and 42 is a parallel / serial converter (P / S).

The serial / parallel converter 41 converts the input serial data SDI into the clock signal CK on the data writing side.
The parallel data DIN for each predetermined number of bits (1 word) is converted by A, and this is written to the dual port RAM 1 by the write clock signal WCK (= write pulse signal WP) generated for each word, and the writing is performed. The pulse signal WP increments the write counter 2 and the up / down counter 31 by +1.

The parallel / serial converter 42 converts the data stored in the dual port RAM 1 into a read clock signal RCK.
(= Read pulse signal RE), and the serial data S is read by the clock signal CKB on the data read side.
At the same time as being converted into DO, the read pulse signal RE is incremented by 1 in the read counter 3 and is incremented by 1 in the up / down counter 31.

In the capacity monitoring unit 30, the decoder 32 uses the count value CD of the up / down counter 31 as the R value.
Monitoring the buffer full state of AM1, CD = N
When (N is the storage capacity of the RAM 1), the buffer full signal FL is generated, and further data writing is blocked via the AND gate circuit 11. On the other hand, the decoder 33 monitors the buffer empty state of the RAM 1 based on the same count value CD, generates a buffer empty signal EP when CD = 0, and blocks further data reading via the AND gate circuit 12. . Therefore, under the above capacity monitoring, the data write phase does not overtake the data read phase, and the data read phase does not overtake the data write phase.

FIG. 10 is a timing chart of a conventional FIFO memory. At the beginning, the read pulse signal RE is generated in a phase that is sufficiently behind the write pulse signal WP, and the count value CD of the up / down counter 31 is C.
The state of D = 2 → 1 → 2 → 1 is repeated. However, in this example, the clock signal CKB is interrupted on the way due to disconnection or disturbance, and therefore the write pulse signal WP and the read pulse signal RE have a new phase relationship (in this example, a very close phase relationship). Transition. The occurrence of such cases is not small in practice. Even in such a case, if the up / down counter 31 can continue the normal up / down operation by the write pulse signal WP and the read pulse signal RE approaching each other, the subsequent count value CD is CD = 3 →
2 → 3 → 2, which indicates the number of stored data accurately.

[0007]

However, in general, if the phases of the write pulse signal WP and the read pulse signal RE are close to each other, for example, the -1 operation due to the read pulse signal RE may be missed. If the -1 operation is missed at the position, the count value CD thereafter is CD = 3 → 4 →
It becomes 3 → 4, and the number of stored data is no longer accurately indicated. As a result, there is stored data for which no data has been actually written, which seriously affects the system. Moreover, since there is no other suitable means for detecting such an erroneous monitoring state, the conventional FIFO memory lacks operational reliability.

The up / down operation of the up / down counter 31 is controlled by one of the clock signals CKA or C.
Although there is also a method of using the KB, if the clock signal CKA or CKB is temporarily interrupted due to disconnection or disturbance, the same malfunction state as described above cannot be avoided.
An object of the present invention is to provide an F that can always perform reliable capacity monitoring.
To provide IFO memory.

[0009]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the FIFO memory of the present invention (1) is a FIFO memory including a memory for storing data, a write counter for generating a write address of the memory, and a read counter for generating a read address of the memory. The first and second windows different from each other are generated based on the write address of the counter, and at least the third window generated based on the predetermined read address of the read counter is generated. The memory capacity is monitored by detecting a partial overlap.

The FIFO memory of the present invention (10) is
In a FIFO memory provided with a memory for storing data, a write counter for generating a write address of the memory, and a read counter for generating a read address of the memory, first and second different from each other based on the read address of the read counter.
By generating the second window and detecting at least a partial overlap between the first and second windows and the third window generated based on the predetermined write address of the write counter, the memory The capacity is monitored.

[0011]

In the present invention (1), for example, the third window signal S with RAD = 0 is replaced with the first window signal WINE with WAD = 0, 1 and the second window signal WINF with WAD = N-1, N. And the signal WIN
The memory capacity is monitored by detecting at least a partial overlap between E or the signal WINF and the signal S.

According to the present invention (1), since the capacity of the memory 1 is inseparably integrated based on the actual address signal (control), the data reading control and the capacity monitoring control are not separated, and the reliability is always maintained. High capacity monitoring is possible. Preferably,
As shown in FIG. 3, the first window signal WINE corresponding to a small value of the write address signal WAD (for example, WAD = 0, 1) and the third value corresponding to a predetermined value of the read address signal RAD (for example, RAD = 0). The empty flag signal EFLG is set due to the overlap with the window signal S of 1. and the subsequent data read control is temporarily suspended. Therefore, even if the data reading phase shifts to the buffer empty side, the data reading phase is automatically delayed,
Transition to a new preferred data reading phase.

Further preferably, the write address signal WAD
Has reached a predetermined value (for example, WAD = 4), the empty flag signal EFLG is reset, and the data read control is started accordingly. Therefore, even if the data reading phase shifts to the buffer empty side, the data reading phase is automatically delayed until it becomes a constant delay with respect to the data writing phase, and the desired data reading phase is maintained.

Further, preferably, as shown in FIG. 4, an arbitrary read address signal RAD is set in the read counter 3 in accordance with the reset of the empty flag signal EFLG. Therefore, even if the data reading phase shifts to the buffer empty side, the data reading phase is automatically delayed and
The data read control can be restarted from the desired phase. Further, preferably, as shown in FIG. 5, the second window signal WINF corresponding to a large value of the write address signal WAD (for example, WAD = N−1, N) and the predetermined value of the read address signal RAD (for example, RAD = 0). ) And the third window signal S corresponding to
Is set and the subsequent data write control is temporarily suspended. Therefore, even if the data reading phase shifts to the buffer full side, the data writing phase is automatically delayed, and a transition is made to a new preferable data reading phase.

Further preferably, the read address signal RAD
Has reached a predetermined value (for example, RAD = 3), the full flag signal FFLG is reset, and the data write control is started accordingly. Therefore, even if the data reading phase shifts to the buffer full side, the data writing phase is automatically delayed until it leads the data reading phase by a certain amount, and the desired data reading phase is maintained.

Further, preferably, as shown in FIG. 6, an arbitrary write address signal WAD is set in the write counter 2 in accordance with the reset of the full flag signal FFLG. Therefore, even if the data reading phase shifts to the buffer full side, the data writing phase can be automatically delayed and the data writing control can be restarted from a desired phase. Further, preferably, as shown in FIG. 2, the empty flag signal EFLG can be forcibly set from the outside. Therefore, the data read control can be started (restarted) at any time and from any phase.

Preferably, as shown in FIGS. 7 and 8,
The write-side and read-side generated signals are generated in synchronization with the first and second clock signals CKA / CKB, respectively, and
Control signals WINE and W straddling between the write side and the read side
The INFs, S, etc. are configured to transfer to the clock signal CKB / CKA of the other side via one or more clock latch circuits. Therefore, each logical operation on the writing side and the reading side becomes reliable.

In the present invention (1), the predetermined read address (third window) of the read counter is set to the first and second write addresses (first and second window) of the write counter which are different from each other. ), The memory capacity was monitored by detecting a partial overlap of these addresses. Paying attention to the symmetry of this capacity monitoring method, conversely, the predetermined write address (third window) of the write counter is set to the first and second read addresses (first and second read addresses) of the read counter which are different from each other. It is obvious that the same capacity monitoring can be performed by sandwiching them with a (window) and detecting a partial overlap of these addresses.

Therefore, although not shown, in the present invention (10), for example, the third window signal S with WAD = 0
The first window signal WINE and R with RAD = 0,1
The capacity of the memory is monitored by sandwiching it with the second window signal WINF of AD = N−1, N and detecting at least a partial overlap between the signal WINE or the signal WINF and the signal S.

Preferably, the second window corresponding to a large value of the read address signal RAD (for example, RAD = N-1, N) after the data read phase is delayed by a predetermined amount or more with respect to the data write phase. And write address signal WAD
The empty flag is set by the overlap with the third window (for example, WAD = 0), and the subsequent data read control is temporarily suspended. Therefore, even if the data reading phase is shifted to the buffer empty side, the data reading phase is automatically delayed, and a transition is made to a new preferable data reading phase.

Further, preferably, after the data read phase is delayed by a predetermined amount or more with respect to the data write phase, a first window corresponding to a small value of read address signal RAD (for example, RAD = 0, 1) is provided. Write address signal WAD
The full flag is set due to the overlap with the third window (for example, WAD = 0), and the subsequent data write control is temporarily suspended. Therefore, even if the data reading phase shifts to the buffer full side, the data writing phase is automatically delayed, and a transition is made to a new preferable data reading phase.

[0022]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 shows the FIF of the embodiment.
In the block diagram of the O memory, 1 is a dual port RAM (DP-RAM), 2 is a write counter (CT).
R), 3 is a read counter (CTR), 4-8 is a timing signal generator (TSG), 9 and 10 are D-type flip-flops (FF), 11-18 are AND gate circuits (A), 19 , 20 are OR gate circuits (O).

The input parallel data DIN is written to the dual port RAM 1 by the write clock signal WCK (= write pulse signal WP) synchronized with the clock signal CKA, and the write pulse signal WP is added to the write counter 2+.
Do 1 On the other hand, the read clock signal RCK in which the data stored in the dual port RAM 1 is synchronized with the clock signal CKB.
The read pulse signal RE is read by (= read pulse signal RE), and the read pulse signal RE is incremented by 1 in the read counter 3.

The timing signal generator 4 is composed of the write counter 2
Based on the write address signal WAD of, the window signal WINE on the write start side is generated at the timing of WAD = 0, 1. Further, the timing signal generator 6 generates the window signal WINF on the write end side at the timing of WAD = N−1, N based on the write address signal WAD. On the other hand, the timing signal generator 7 generates the reference signal S on the read start side at the timing of RAD = 0 based on the read address signal RAD of the read counter 3. Further, the timing signal generator 5 generates the empty flag clear signal EFCLR at the timing of WAD = 4, and the timing signal generator 8 generates the full flag clear signal FFCLR at the timing of RAD = 3.

The clock signals CKA and CKB are free-running and are not in phase synchronization with each other. The clock frequencies CKA and CKB are basically substantially the same, but the relationship of CKA <CKB or CKA> CKB is continuously or temporarily generated due to frequency error, jitter, or wander. Along with this, the data reading phase for the dual port RAM 1 also changes variously. That is, when CKA <CKB, the data read control is fast and therefore the phase shifts to the buffer empty side, and when CKA> CKB, the data write control is fast and the phase shifts to the buffer full side.

The following is a timing chart (1) to () of FIG. 3 to FIG. 6 showing the capacity monitoring control and the accompanying reading phase shift control when the data reading phase is shifted to the buffer empty side or the buffer full side. This will be described with reference to 4).
FIG. 3 is a timing chart (1) of the FIFO memory of the embodiment and shows the operation when the data reading phase is shifted to the buffer empty side.

Although not shown, initially, WAD = 0 and RAD = 0 due to the generation of the system reset signal SR. In this case, the window signal WINE = 1,
The reference signal S = 1 and the AND gate circuit 15 is satisfied. The output of the AND gate circuit 15 is the OR gate circuit 1
9. The flip-flop 10 is set by the first clock signal CKB via the AND gate circuit 15, and the empty flag signal EFLG = 1. When the flip-flop 10 is of D type, the state of EFLG = 1 is OR
It is held via the gate circuit 19 and the AND gate circuit 16. The AND gate circuit 12 blocks the generation of the read pulse signal RE when EFLG = 1, whereby the data read control is kept waiting.

When the write address signal WAD = 4 eventually, the empty flag clear signal EFCL is generated from the timing signal generator 5, and this resets the flip-flop 10 via the AND gate circuit 16.
As a result, the empty flag signal EFLG becomes 0, and the waiting data reading control is started with a predetermined delay phase. In this case, the timing signal generator 5
If the decode value of is chosen to be much larger than "4",
It is possible to sufficiently delay the start phase of data read control. The decode value of the timing signal generator 5 may be set externally.

After that, for example, the clock frequency CKA <
When the data reading phase is shifted to the buffer empty side due to the relationship of CKB, the window signal WIN (WA
D = 1) and the reference signal S (RAD = 0) overlap and AN
The D gate circuit 15 is satisfied. The output of the AND gate circuit 15 sets the flip-flop 10 via the OR gate circuit 19 and the AND gate circuit 16, and the empty flag signal EFLG = 1. When the flip-flop 10 is a D type, the state of EFLG = 1 is held via the OR gate circuit 19 and the AND gate circuit 16. AN
The D gate circuit 12 prevents the subsequent generation of the read pulse signal RE when EFLG = 1, and the data read control is kept waiting.

When the write address signal WAD = 4, the empty flag clear signal EFCL is generated, which resets the flip-flop 10 via the AND gate circuit 16. As a result, the empty flag signal EFLG becomes 0, and the waiting data read control restarts the subsequent data read control. If the clock frequency CKA <CKB continues, the data reading phase will soon shift to the buffer empty side again. However, if the decode value of the timing signal generator 5 is set to a value sufficiently larger than “4”, the restart phase of the data read control can be delayed sufficiently.

A timer (TM) 21 may be provided instead of the timing signal generator 5 shown in FIG. The timer 21 in this example times out by counting a predetermined number of clock signals CKB after EFLG = 1, and generates an empty flag clear signal EFCL. With this configuration, simple control can be performed such that the data read phase is delayed by a predetermined time each time the data reading phase becomes the buffer empty.

FIG. 4 is a timing chart (2) of the FIFO memory of the embodiment and shows another operation when the data reading phase is shifted to the buffer empty side. In this example, as shown in FIG. 2, the AND gate circuit 1
4 is provided so that a predetermined value (“0” in this example) can be loaded into the read counter 3 under the condition of EFLG = 1 * EFCL = 1. In this way, the data read phase is restarted from RAD = 0 in FIG. 4, rather than from the subsequent RAD = 2 as in FIG. Therefore, the data read phase is further delayed. In this read frame, some data is double read, but the read from the next frame is normal. The predetermined value loaded to the read counter 3 may be any value other than "0", and this value may be set externally. In this way, the data read phase can be set arbitrarily.

As shown in FIG. 2, the flip-flop 10 may be forcibly set at an arbitrary timing by an external set signal PGS. In this way, data read control from an arbitrary data read address can be restarted at an arbitrary timing. FIG. 5 is a timing chart (3) of the FIFO memory of the embodiment and shows the operation when the data reading phase is shifted to the buffer full side.

When the data reading phase is shifted to the buffer full side due to the relationship of clock frequency CKA> CKB, the window signal WINF (WAD = N-1) and the reference signal S
(RAD = 0) overlaps and satisfies the AND gate circuit 17. The output of the AND gate circuit 17 sets the flip-flop 9 via the OR gate circuit 20 and the AND gate circuit 18, and the full flag signal FFLG = 1. When the flip-flop 9 is the D type, the state of FFLG = 1 is held via the OR gate circuit 20 and the AND gate circuit 18. The AND gate circuit 13 prevents the subsequent generation of the write pulse signal WP by FFLG = 1, whereby the data write control is kept waiting.

When the read address signal RAD = 3 eventually, a full flag clear signal FFCL is generated, which resets the flip-flop 9 via the AND gate circuit 18. As a result, the full flag signal FFLG becomes 0, and the waiting data write control restarts the subsequent data write control. In addition, the clock frequency CK
If the state of A> CKB continues, the data reading phase will be shifted to the buffer full side again soon. However, if the decode value of the timing signal generator 8 is set to a value sufficiently larger than “3”, the restart phase of the data write control can be delayed sufficiently.

Although not shown, a timer may be provided in the same manner as above, instead of providing the timing signal generator 8 of FIG. The timer in this case times out by counting a predetermined number of clock signals CKA after FFLG = 1, and generates a full flag clear signal FFCL. With such a configuration, simple control can be performed such that the data writing phase is delayed by a predetermined time each time the data reading phase becomes full.

FIG. 6 is a timing chart (4) of the FIFO memory of the embodiment, showing another operation when the data reading phase is shifted to the buffer full side. In this example, an AND gate circuit 13 is provided as shown in FIG.
Under the condition of FLG = 1 * FFCL = 1, the write counter 2 can be loaded with a predetermined value (“0” in this example). The data reading phase in this case is substantially the same as that in FIG. 5, but if the write counter 2 is loaded with an arbitrary value other than "0", the data write control is restarted from the arbitrary write address WAD. it can. The data writing of this frame is not normal, but the data writing from the next frame is normal.

Thus, under the capacity monitoring / control of the present embodiment, the data writing phase does not overlap with the data reading phase and does not overtake. Also, the data read phase does not overlap the data write phase and does not overtake it. Further, if the signal widths of the window signals WINE and WINF are selected to be larger, the data reading phase control with even more margin can be performed.

FIG. 7 is a block diagram of the timing signal generator of the embodiment. As an example, FIG. 7A shows a configuration in which four decoders DEC0 to DEC3 decode the write address signals WAD = 0 to 3 or WAD = N-3 to N, respectively, and take the logical sum of the decoded outputs. Shows.
This configuration is effective when the time widths of the output signals WINE, WINF, etc. are short.

FIG. 7B shows a configuration in which the RS flip-flop FF is forcibly set by the decode output of the decoder DEC0 and the flip-flop FF is forcibly reset by the decode output of DEC3. This configuration is effective when the time width of the output signals WINE, WINF, etc. is long. 7C shows a configuration in which the D flip-flop FF is set at the timing of the clock signal CKA by the decode output of the decoder DEC0, and the flip-flop FF is reset at the timing of the clock signal CKA by the decode output of DEC3. There is. This configuration is effective when the time width of the output signals WINE, WINF, etc. is long.

FIG. 8 is a block diagram of the control signal clock transfer system of the embodiment. FIG. 8A shows a configuration in which the control signal synchronized with the clock signal CKA is transferred to the control signal synchronized with the clock signal CKB by using the two D flip-flops FF. The number of D flip-flops FF may be one. In FIG. 8B, the rising edges of the control signal synchronized with the clock signal CKA are first captured by the two upper D flip-flops FF and the AND gate circuit A at the timing of the clock signal CKB. Set FF. Next, the two lower D flip-flops FF and A
The ND gate circuit A catches the falling edge of the control signal in synchronization with the clock signal CKA at the timing of the clock signal CKB, thereby resetting the output D flip-flop FF.

In the case of performing the clock transfer of the control signal, the time width of the control signal on the side synchronized with the clock signal CKA needs to be at least one cycle of the clock signal CKB. Thus, by using any one of the above clock transfer circuits, a FIFO memory with stable operation can be constructed.

Although the data memory is composed of the dual port RAM 1 in the above embodiment, it may be composed of an elastic memory or a normal RAM. Further, in the above embodiment, one reference signal S is generated at the timing of RAD = 0, but the present invention is not limited to this. The reference signal S may be continuously generated for any RAD = a to b (where 0 <a <b <N), or RAD = a, b (however,
It may be generated at two points of 0 <a <b <N).

Further, in the above embodiment, the reference signal S of the read counter 3 is changed to the different window signal WI of the write counter 2.
The capacity of the memory 1 was monitored by sandwiching between NE and WINF and detecting a partial overlap of these signals. However, if attention is paid to the symmetry of this capacitance monitoring method, conversely, the reference signal S (for example, WAD = 0) of the write counter 2 is changed to the different window signal WINE (for example, RA
D = 0, 1), WINF (for example, RAD = N-1, N)
It is clear that the same capacity monitoring can be performed by sandwiching the two with and detecting a partial overlap of these signals.

In this case, although not shown, the window signal WINF of the read counter 3 and the reference signal S of the write counter 2 overlap after the data read phase is delayed by a predetermined amount or more with respect to the data write phase. As a result, the empty flag signal EFLG is set, and the subsequent data read control is temporarily suspended. Further, the full flag signal FFLG is set because the window signal WIN of the read counter 3 and the reference signal S of the write counter 2 overlap each other after the data read phase is delayed by a predetermined amount or more with respect to the data write phase. Then, the subsequent data writing control is temporarily suspended.

Although the preferred embodiment of the present invention has been described above, it goes without saying that various changes in the structure and combination can be made without departing from the spirit of the present invention.

[0047]

As described above, according to the present invention, the first and the second different from each other based on the write address of the write counter.
Of the memory, and at the same time, the memory capacity is monitored by detecting at least a partial overlap between the first and second windows and the third window generated based on a predetermined read address of the read counter. Therefore, the data reading control and the memory capacity monitoring control are not separated, and even if the clock signal is interrupted or disturbed, a highly reliable FIFO memory operation is always guaranteed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a FIFO memory according to an embodiment.

FIG. 3 is a timing chart (1) of the FIFO memory according to the embodiment.

FIG. 4 is a timing chart (2) of the FIFO memory according to the embodiment.

FIG. 5 is a timing chart (3) of the FIFO memory according to the embodiment.

FIG. 6 is a timing chart (4) of the FIFO memory according to the embodiment.

FIG. 7 is a block diagram of a timing signal generation unit according to the embodiment.

FIG. 8 is a block diagram of a control signal clock transfer system according to the embodiment.

FIG. 9 is a block diagram of a conventional FIFO memory.

FIG. 10 is a timing chart of a conventional FIFO memory.

[Explanation of symbols]

 1 Memory 2 Write Counter 3 Read Counter 4 First Window Generation Unit 6 Second Window Generation Unit 7 Third Window Generation Unit

Claims (12)

[Claims] 1. A FIFO memory comprising: a memory for storing data; a write counter for generating a write address of the memory; and a read counter for generating a read address of the memory, based on a write address of the write counter. The first and second windows that are different from each other are generated, and the first and second windows are generated.
FIFO memory, wherein the capacity of the memory is monitored by detecting at least a partial overlap between the window and the third window generated based on a predetermined read address of the read counter. 2. A first corresponding to a small value of a write address.
2. The FIFO memory according to claim 1, wherein the empty flag is set when the third window of the read address overlaps the third window of the read address, and the subsequent data read control is temporarily suspended. 3. The FIF according to claim 2, wherein the empty flag is reset when the write address reaches a predetermined value, and the data read control is started accordingly.
O memory. 4. The FIFO memory according to claim 3, wherein an arbitrary read address is set in the read counter when the empty flag is reset. 5. A second address corresponding to a large value of the write address.
2. The FIFO memory according to claim 1, wherein the full flag is set by the overlapping of the third window of the read address and the third window of the read address, and the subsequent data write control is temporarily suspended. 6. The FIFO memory according to claim 5, wherein the full flag is reset when the read address reaches a predetermined value, and the data write control is started accordingly. 7. The FIFO memory according to claim 6, wherein an arbitrary write address is set in the write counter when the full flag is reset. 8. The FIFO memory according to claim 2, wherein the empty flag can be forcibly set from the outside. 9. The write-side and read-side generated signals are respectively generated in synchronization with the first and second clock signals, and
2. The FIFO memory according to claim 1, wherein the control signal extending between the writing side and the reading side is configured to be transferred to the clock signal of the other side via one or more clock latch circuits. 10. A FIFO memory including a memory for storing data, a write counter for generating a write address of the memory, and a read counter for generating a read address of the memory, which are different from each other based on the read address of the read counter. The first and second windows are generated, and the first and second windows are generated.
FIFO memory, wherein the capacity of the memory is monitored by detecting at least a partial overlap between the above window and a third window generated based on a predetermined write address of the write counter. 11. The second window corresponding to a large value of the read address and the third window of the write address overlap each other after the data read phase is delayed by a predetermined amount or more with respect to the data write phase. 11. The FIFO memory according to claim 10, wherein the empty flag is thereby set and the subsequent data read control is temporarily suspended. 12. The first window corresponding to a small value of the read address and the third window of the write address overlap each other after the data read phase is delayed by a predetermined amount or more with respect to the data write phase. 11. The FIFO memory according to claim 10, wherein the full flag is set and the subsequent data write control is temporarily suspended.